CHAPTER 3 SIMULATION TOOLS AND

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1 CHAPTER 3 SIMULATION TOOLS AND Simulation tools used in this simulation project come mainly from Integrated Systems Engineering (ISE) and SYNOPSYS and are employed in different areas of study in the simulation part of the project. Simulation tools from ISE include GENESISe, MDRAW, MESH3D and DESSIS. They are mainly applied in the study of a three-dimensional (3-D) structure device simulation. Due to the lack of proper oxidation models, 3-D process simulation becomes inadequate. The next best thing will be to employ pseudo-3d process simulation to simulate and analyze the corner inversion and rounding effects in a tri-gate structure using non-uniform junction doping profile (From TSUPREM4 tif file) in which the methodology will be covered in the later section of this chapter. Due to the fact that it is the first time that a Gate-All-Around (GAA) device is being fabricated using 0.13um technology node locally, some simulations have to be carried out to predict certain implantation conditions of the GAA electrical wafers so that success of fabrication is increased. Using the simulation tools namely TSUPREM4 and MEDICI from SYNOPSYS, the predictions are made using a calibrated 0.13um simulation deck from Chartered Semiconductors Manufacturing. 22

2 The methodology of calibrating a simulation deck before any significant predictions can be made will be elaborated in this chapter as well. In addition, this chapter proposes to discuss the different simulation software used in this project as follows. 3.1 ISE Simulation tools ISE is a world leading provider of Technology CAD (TCAD) software that covers the entire range from process simulation to device and circuit simulation. ISE tools are particularly suited for emerging technologies and complex applications including sub-100nm and non-planar CMOS, quantum devices and nanoelectronics. In this project, 3D mesh and device simulation tools were applied. The software used included GENESISe, MDRAW, MESH3D and DESSIS GENESISe GENESISe is ISE s primary user interface for TCAD simulation, providing access to all ISE software. It is a graphical user interface used to design, organize and run complete simulation projects. Apart from that, it comes with an integrated job scheduler to speed up simulations and take advantage of distributed, heterogeneous, corporate computing resources. Lastly, GENESISe provides the user with a convenient framework to drive the large variety of ISE simulation and visualization 23

3 tools and other third-party tools like TSUPREM4 that will be described in the methodology section in this chapter MDRAW MDRAW is part of the ISE TCAD environment and includes the following Boundary editor Doping and refinement editor Scripting engine that follows the TCL language syntax Meshing engine Each of these is used to create boundary, doping and refinement information and meshes adequate for device simulation. MDRAW contains two separate environments: a boundary editor and a doping and refinement editor. Both use the same graphical user interface (GUI) components and are applied in MDRAW to generate and modify TCAD models to meet specific simulation requirements MESH3D The mesh generator MESH3D is a dimension independent and modular Delaunay grid generator, which is suitable for semiconductor device simulation. 24

4 MESH generates high quality spatial discretizations for 3D devices using a predefined set of mixed-elements types. Taking some of the best meshing algorithms available and innovative ideas and procedures, MESH is a modular, dimensionindependent mesh generation tool kit. In 3-D, grids for complex nonplanar devices can be generated. MESH3D is also the grid generation engine that is used inside MDRAW. By default, MDRAW generates a mesh without obtuse angles and MESH3D produces less restrictive Delaunay meshes. MESH3D is fully integrated into the ISE environment. The DF-ISE boundary representation is used as input for MESH3D. Impurity concentrations and userrequired element sizes can be described using dimension-independent syntax. The same description of analytical profiles can be used in 3D. The grid can be adapted to analytical profiles or profiles generated by DIOS and TSUPREM4, which is a powerful feature of this software DESSIS DESSIS simulates numerically the electrical behavior of a single semiconductor device in isolation or several physical devices combined in a circuit. Terminal currents, voltages and charges are computed based on a set of physical device equations that describes the carrier distribution and conduction mechanisms. 25

5 In this project, device simulator, DESSIS is used to simulate a 3-D tri-gate structure that incorporates a TSUPREM4 doping profile. 3.2 SYNOPSYS Simulation tools Synopsys is the world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms to the global electronic market, enabling the development of complex systems-on-chips (SoCs). With the range of TCAD software provided, Synopsys has satisfied a long-identified need in IC design, technology development and semiconductor fabrication. Growing industry acceptance of TCAD (technology computer-aided design) simulation tools namely TSUPREM4 and MEDICI has broadened their use from the Research and Development scientist to the front-line engineer. Through the use of the process and device simulators, TSUPREM4 and MEDICI, certain implantation conditions are set while processing the electrical wafers for Gate-All-Around transistors Taurus-TSUPREM4 Taurus-TSUPREM4 is the industry-standard process simulation tool that is widely used by semiconductor companies to optimize IC fabrication processes. With the most advanced models commercially available, Taurus-TSUPREM4 simulates the process steps encountered in today s semiconductor devices and predicts the resulting 26

6 device structure, eliminating the need for costly experiments. Thus, Taurus- TSUPREM4 can help to optimize device geometry and doping to reduce product development cycles and shorten product time to market. It provides the following benefits: Predict one and two dimensional device structure characteristics by accurately simulating ion implantation, diffusion, oxidation, silicidation, epitaxy, etching and deposition. Determine basic electrical device characteristics, such as sheet resistance, threshold voltage and C-V curve (including quantum mechanical correction) Create process structures for two dimensional device analysis using SYNOPSYS Taurus-MEDICI Taurus-MEDICI Taurus-MEDICI is SYNOPSYS industry-standard device simulation tool that predicts electrical, thermal and optical characteristics of semiconductor devices. A wide variety of devices can be modeled in one, two or three dimensions including MOSFETS, power devices and multiple gate structures. With the most advanced physical models commercially available, Taurus-MEDICI allows device designs to be 27

7 optimized for best performance without fabrication, eliminating the need for costly experiments. It provides the following features: Analyze electrical, thermal and optical characteristics of your devices through simulation without having to manufacture the actual devices Reduce the number of potential wafers used in the actual experiment Understand internal device operation through potential, electric field, current density Optimize device designs without and find ideal structural parameters 3.3 Simulation Methodology using SYNOPSYS TCAD tools Before any TCAD calibration, it is very crucial to build simulation decks that are as detailed as possible to the actual process. Hence, the initial stage of calibration always begins with data and information collection to construct reliable simulation decks for calibration. With these essential data and information, simulation decks for process and device simulations can be built using SYNOPSYS process simulator (TSUPREM4) and device simulator (MEDICI). The following sub-sections would highlight more of the information required to construct reliable simulation decks before any significant process predictions can be made. These sub-sections include Process Flow, Recipes, Physical Device Structures, Implantation Profiles and Grid Setting. 28

8 Construction of Simulation Decks based on Process Flow and Recipes in TSUPREM4 Ensure that the Simulated CMOS Device Structure in the process is based on In-Line Measurements and TEM Availability of SIMS? NO UT-MARLOWE to generate As-Implanted Doping Profiles YES Selection of Appropriate Implantation Tables in TSUPREM4 Initial Grid Setting Significant Variation in Simulated Vtlin/Idsat if Grid Lines Increased? YES Increased Grid Lines Setting NO Fixed Grid Setting and Simulation Deck Ready for Calibration Fig. 3.1 Flow chart for setting up a simulation deck for prediction of process conditions 29

9 3.3.1 Process Flow With the aim of achieving balanced accuracy and optimum resources, it is very important to identify the essential steps to be included in the simulation process. The essential and critical steps include basically oxidation, annealing cycles and implantation. All the other wafer preparation steps such as wafer clean steps can be neglected due to the fact that there is no significant thermal cycle involved that can affect the final implantation profiles in the simulated CMOS devices. Fig. 3.1 illustrate a flow chart that is required for a typical sub-0.13 µm technology CMOS device process to be calibrated. Usually NMOS device and PMOS device are constructed and simulated separately in two simulation decks so as to eliminate unnecessary masking steps in simulated process Recipes The simulated CMOS devices electrical characteristics depend on the final doping profiles of all the implantation, thus critical process steps like oxidation, thermal annealing and deposition steps which involved thermal cycles have to be accurately represented in the simulation decks. Start temperature, final temperature, ramp rate or anneal time, and flow of gases are the important parameters that need to be referenced from the actual recipes. The thermal cycles of these recipes can be 30

10 implemented using DIFFUSION statement in TSUPREM4, which is a command for high temperature diffusion in both oxidizing and non-oxidizing ambient. Choice of ambient includes dry O 2, wet O 2, steam and inert, whereas choice of gas flows includes O 2, H 2, N 2 ad HCl It is important to follow as detailed as possible to the recipes, including the ramping up and down of temperature. All thermal steps starting from 550 C have to be included for accuracy. The amount of gas flows for each gas input has to be reflected in the simulation with the correct proportion as shown in Fig Fig. 3.2 A typical gate oxide recipe implemented in a simulation deck Physical Device Structures There is an absolute need to evaluate the actual and final dimensions of the processed CMOS devices to make the simulation as close to the actual experiment as possible. These dimensions can be obtained from all the in-line measurements that are 31

11 being carried out during the manufacturing process. The physical parameters are gate oxide thickness, physical gate length, sacrificial oxide thickness (before any implantation) and spacer dimensions. Alternatively, images from Transmission Emission Microscopy (TEM) can also be used to provide reference for construction of the simulated CMOS device structures. The device dimensions such as polysilicon gate length, gate oxide thickness and spacer dimensions are very important as they could affect the electrical performance significantly. For example in simulation, a 1% change in either physical gate length or gate oxide thickness will result in approximately a 1% change in Idsat. For CMOS devices with 0.13 µm gate length and 2 nm gate oxide, 1% variation in these key parameters imply metrology requirements of 1.3 nm for the polysilicon length and 0.02 nm for the oxide thickness. Spacer dimensions would affect all the implantation steps that are performed after spacer formation (eg. source/drain implantation), hence determine the profiles and concentrations of these impurities away from the channel regions. Thus correct representation of space dimensions in simulations can simplify the calibration of the lateral influence of the source/drain implantation, which determined the short channel effect. The physical thickness of sacrificial oxide prior to any implantation also needs to be correctly measured, so as to generate the correct implantation profiles in the simulations. 32

12 3.3.4 Implantation Profiles In order to closely approximate the actual device performance in simulations, it is very important to have the correct implantation profiles in the TCAD process simulator. Since there are many built-in implantation tables or databases for selection in TSUPREM4, one of the first steps to calibration is always to identify the correct implantation tables/databases to be used for the various implantation conditions in the process. The most reliable way to select the appropriate implantation tables/databases in TSUPREM4 is to take reference from the various measured doping profiles from Secondary Ion Mass Spectroscopy (SIMS). It would be ideal if SIMS profiles of the various dopants before and after key process steps with thermal cycles are available. This would allow accurate calibration of the implantation profiles of the dopants as well as the impact of diffusion of the various thermal cycles. However, these doping profiles might not be readily available due to the high cost and long time needed to generate the SIMS profiles. Hence the next best alternative is to use ion implantation simulator to generate possible implantation profiles. These time-consuming and tedious Monte-Carlo simulations of the implantation are performed according to the implantation sequence, so as to take into account the damage from previous implantation. One of 33

13 the better-used ion implantation simulators is UT-MARLOWE. It is a software platform for simulation of ion implantation into crystalline and amorphous materials, extensively modified from MARLOWE Version 12 (developed by Mark Robinson and coworkers at Oak Ridge National Laboratory). These generated implantation profiles are then compared with the implantation profiles from the selected implantation tables, so as to ensure that the implantation profiles used in simulations can be closer to reality Grid Setting A grid structure must be defined before process simulation can start. It can be done by explicitly specifying the locations and spacing of grid lines, or automatically by generating a grid given the width and the location of mask edges. All the griddefining commands are listed under MESH and LINE statement in TSUPREM4. MESH statement specifies a grid spacing scale factor and other default values for controlling automatic grid generation. LINE statement specifies a horizontal or vertical mesh line in a non-uniform rectangular grid. Usually simulations with finer grid setting would provide more accurate results since there would be more grids for statistical computation. However, the tradeoff would be longer simulation time. Thus grid setting becomes an important procedure that would optimize accuracy and simulation time. 34

14 For initial grid setting, finer grids should be set at the polysilicon gate-gate oxide-channel interface because the doping profiles at these sensitive regions would affect many electrical characteristics such as Vt of long and nominal channel devices, C-V, etc. There should be sufficient grid points, especially at the bottom of polysilicon gate, in order to have accurate doping profiles that would affect the polysilicon depletion effect. The horizontal grid lines have to be defined finer in the channel region under gate oxide (as it is the path for conduction of electrons/holes) as well as the region for the source-drain pn junction. The vertical grid lines have to be defined finer at the gate edges, as source-drain pn junction needs to be accurately represented in simulations in order to calibrate for the effective electrical gate length. In conclusion, more vertical and horizontal grid lines need to be dedicated to regions around the pn junction and polysilicon gate-gate oxide-channel interface, or any other sensitive regions as the different process demands. Thus grid setting for simulation deck is very unique to each process, depending on the CMOS device structure as well as implantation conditions that effectively determined the final pn junction. In order to minimize unnecessary simulation time, alternate vertical and horizontal grid lines can be removed in the non-critical regions. This is done with ELIMINATE statement, which eliminate mesh nodes along lines in a grid structure over a specified rectangular region. Grid setting can be adjusted according to the requirements of simulation and the simulation time/resources, by adding more 35

15 vertical and horizontal grid lines in the critical regions. Grid optimization can be performed through analyzing simulated Vt/Idsat for different grid settings. More grid lines would not be useful if the variation in simulated Vt/Idsat is insignificant. It is recommended that the total number of nodes in a simulated structure be less than 5000 nodes in order to achieve efficient simulations. 3.4 Simulation Methodology using ISE TCAD tools The software from Industrial Systems Engineering (ISE) namely MDRAW, MESH3D and DESSIS [19] were used in this work. As 3D process simulation is inadequate due to the lack of proper oxidation models, the next alternative is to carry out a pseudo 3-D simulation where 2-D process simulation data in different regions is used to construct the 3-D device structure. Firstly the 2-D geometry is created using a boundary editor, MDRAW from ISE. The boundary editor is used to create, modify and visualize a device structure. Then using interfise command, it converts the TSUPREM4 file type formats to DF- ISE format to be incorporated into the 2-D geometry. Then the structure is extended to form the channel region. Together with different 2-D cross sections that are extended, the different boundaries are combined to form the final 3-D structure. A summary of the simulation methodology is shown in Fig

16 Fig. 3.3 Simulation methodology showing a partial 3D simulation obtained with a realistic doping profile imported from TSUPREM4 Then the device simulator, DESSIS is used to simulate the electrical characteristics of the structure in 3-D as shown in Fig. 3.4 S G BOX D Sub Fig. 3.4 Final pseudo 3-D simulation structure with a realistic 2-D doping profile from TSUPREM4 showing the corner of the fin being rounded. 37