System-level Test and Validation of Hardware/Software Systems

Transcription

1 M. Sonza Reorda Z. Peng M. Violante (Eds.) System-level Test and Validation of Hardware/Software Systems With 55 Figures Springer

2 Table of Contents Table of Figures List of Contributors ix xi 1 Introduction Z. Peng, M. Sonza Reorda and M. Violante 1 Acknowledgments 3 2 Modeling Permanent Faults J.P. Teixeira Abstract Introduction Definitions High-level Quality Metrics System and Register-transfer-level Fault Models for Permanent Faults Observability-based Code Coverage Metrics Validation Vector Grade Implicit Functionality, Multiple Branch Conclusions 22 Acknowledgments 23 References 23 3 Test Generation: A Symbolic Approach F. Fummi and G. Pravadelli Abstract Introduction Binary Decision Diagrams Methodology The Random-based Approach The Symbolic Approach Hardware Design Language to Binary Decision Diagram Translation Functional Vector Generation for a Single Process Functional Vector Generation for Interconnected Processes The Testing Framework Fault Model Definition Automatic Test Pattern Generation Engines Experimental Results Concluding Remarks 44 Acknowledgments 45 References 45

3 vi Table of Contents 4 Test Generation: A Heuristic Approach О. Goloubeva, M. Sonza Reorda and M. Violante Abstract Introduction Assumptions High-level Test Generation High-level Fault Models High-level Test Generation Testing Hardware/Software Systems testgen Results Results Starting from Random Vectors Results Starting from Designer Vectors Result Discussion Validating Application-specific Processors Design Flow Experimental Results Results of the Processor Customization Results of the Test Vector Generation Conclusions 63 References 64 5 Test Generation: A Hierarchical Approach G. Jervan, R. Ubar, Z. Peng and P. Eles Abstract Introduction Modeling with Decision Diagrams State of the Art Modeling Digital Systems by Binary Decision Diagrams Modeling with a Single Decision Diagram on Higher Levels Hierarchical Test Generation with Decision Diagrams Scanning Test Conformity Test Conclusions 80 References 81 6 Test Program Generation from High-level Microprocessor Descriptions E. Sanchez, M. Sonza Reorda and G. Squillero Abstract Introduction Microprocessor Test-program Generation Methodology Description Architectural Models Register-transfer-level Models Case Study Processor Description Automatic Tool Description 96

4 Table of Contents vii Experimental Setup Experimental Results High-level Metrics Comparison Conclusions 104 Acknowledgments 105 References Tackling Concurrency and Timing Problems I.G.Harris Abstract Introduction Synchronization Techniques A Class of Synchronization Errors A Fault Model for Synchronization Errors Detection of Synchronization Faults Fault Coverage Computation Experimental Results Conclusions 118 Acknowledgments 118 References An Approach to System-level Design for Test G. Jervan, R. Ubar, Z. Peng and P. Eles Abstract Introduction Hybrid Built-in Self-test Hybrid Built-in Self-test Cost Optimization Hybrid Built-in Self-test for Multi-core Systems Built-in Self-test Time Minimization for Systems with Independent Built-in Self-test Resources Built-in Self-test Time Minimization for Systems with Test Pattern Broadcasting Conclusions 146 References System-level Dependability Analysis A. Bobbio, D. Codetta Raiteri, M. De Pierro and G. Francheschinis Abstract Introduction Introduction to Fault Trees Fault Tree Example Modeling Dependencies in the Failure Mode Using Dynamic Gates Giving a Compact Representation of Symmetric Systems through Parameterization Modeling the Repair Process Through the Repair Box 158

5 viii Table of Contents 9.4 Reliability Analysis Qualitative Analysis Quantitative Analysis Importance Measures Qualitative and Quantitative Analysis of the Examples Minimal Cut-sets Detection Quantitative Analysis Conclusions 171 Acknowledgments 172 References 172 Index 175