ADVANCES IN ELECTRONIC TESTING CHALLENGES AND METHODOLOGIES. Edited by. DIMITRIS GIZOPOULOS University of Piraeus, Greece.

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1 ADVANCES IN ELECTRONIC TESTING CHALLENGES AND METHODOLOGIES Edited by DIMITRIS GIZOPOULOS University of Piraeus, Greece 4y Springer

2 Foreword xiii by Vishwani D. Agrawal Preface xvii by Dimitris Gizopoulos Contributing Authors xxiii Dedication xxv Chapter 1 Defect-Oriented Testing 1 by Robert C. Aitken 1.1 History of Defect-Oriented Testing Classic Defect Mechanisms Shorts Opens Parametric Changes Defect Mechanisms in Advanced Technologies i Copper-related Defects Optical Defects Design-related Defects Defects and Faults Uses of Fault Models Single Stuck-at Faults Bridging Faults Open Fault Models Timing-related or Delay Faults IDDQ Models 27

3 vi 1.5 Defect-Oriented Test Types Logic Tests Current-based Tests Delay Test Very Low Voltage Stress Testing Experimental Results Fault Coverage, Scan vs. Functional Effectiveness of I DDQ, Scan, At-speed Tests Statistical Post Processing Future Trends and Conclusions 39 Acknowledgments 40 References 40 Chapter 2 Failure Mechanisms and Testing in Nanometer Technologies 43 by Jaume Segura, Charles Hawkins and Jerry Soden 2.1 Scaling CMOS Technology Device Scaling Interconnect Scaling Parameter Variations Noise Failure Modes in Nanometer Technologies Bridge Defects Open Circuit Defects Parametric Failures Test Methods for Nanometer ICs Impact of Technology Scaling on Testing Dealing with Background Current Increase Noise-tolerant Techniques Impact of Variation on Delay Conclusion 73 References 73 Chapter 3 Silicon Debug 77 by Doug Josephson and Bob Gottlieb 3.1 Introduction Silicon Debug History Silicon Debug Process Post-silicon Validation 80

4 Advances in Electronic Testing: Challenges and Methodologies vii 3.4 Debug Flow Step 1: Control the Failure Step 2: Isolate the Failing Circuit Step 3: Root Cause the Failure Step 4: Try to Expand the Problem Circuit Failures Speedpaths Mintime Races Charge Sharing Interconnect Noise Leakage Manufacturability A Case Study in Silicon Debug Future Challenges for Silicon Debug Conclusion 106 Acknowledgements 107 References 107 Chapter 4 Delay Testing 109 by Adam Cron 4.1 Introduction Why Delay Testing Why Now Delay Test Basics Transition Delay Basics Path Delay Basics Test Application Scan Architectures Last-Shift-Launch System-Clock-Launch Hybrid Launch BIST and Delay Testing Philosophy and Delay Test Application Delay Test Details Clock Domain Issues I/O Issues Vector Generation Last-Shift-Launch System-Clock-Launch Fault Model Tweaks Selecting Faults 127

5 7.7.2 Requirements for SOC At-speed Test Functional Tests for At-speed Testing Scan Design and Scan Control Clock Control for At-speed Testing Handling Violating Paths Test Control Through I/Os Pattern Generation Techniques Design for Memory and Logic BIST BIST Overview Design Techniques for Memory BIST Design Techniques for Logic BIST Functional BIST SOC BIST Architecture Conclusion 257 Acknowledgements 259 References 259 Chapter 8 Embedded Memory Testing 263 by R. Dean Adams 8.1 Introduction The Memory Design Under Test Static Memory Register Files Dual Port Memories Content Addressable Memories Dynamic Random Access Memories Memory Faults Memory Test Patterns Pattern Nomenclature Key March Patterns Memory Data Backgrounds CAM Test Patterns Self Test Advanced Memories & Technologies Conclusions 298 References 298 Chapter 9 Mixed-Signal Testing and DfT 301 by Stephen Sunter 9.1 A Brief History Functional vs. Structural Test 303

6 Advances in Electronic Testing: Challenges and Methodologies xi Testing Design-for-Test Fault Modeling The State of the Art Testing DfT Fault Modeling Advances in the Last 10 Years Testing DfT Fault Modeling Emerging Techniques and Directions Testing DfT EDA Tools for Mixed-Signal Testing Testing DfT Fault Modeling Future Directions 332 References 334 Chapter 10 RF Testing 337 by Randy Wolf, Mustapha Slamani, John Ferrario and Jayendra Bhagat 10.1 Introduction Testing RFICs RF IC Categories RF Test Challenges RF Test Cost Reduction Factors Resources and Test Time Cost Handler Test Hardware Universal Test Board RF Test Function Sub-Circuit Design Complete Test Architecture Hardware Development Process High Frequency Simulation Tools Schematic Simulation D RF Board Simulation D RF Socket and Package Modeling 365

7 xii 10.7 Device Under Test Interface Sockets Wafer Probes Conclusions 368 Acknowledgements 368 References 368 Chapter 11 Loaded Board Testing 371 by Kenneth P. Parker 11.1 The Defect Space at Board Test What is a "Defect"? What is a "Fault"? The "PCOLA/SOQ" Model Test Coverage In-Circuit Test (ICT) Unpowered Shorts Tests Unpowered Analog Tests Powered In-Circuit Digital Tests Boundary-Scan Tests Powered Mixed-Signal Tests Pros and Cons of ICT Loaded Board Inspection Systems Automatic Optical Inspection (AOI) Automatic X-Ray Inspection (AXI) Pros and Cons of Inspection The Future of Board Test 405 References 406 Index 407