An Incremental Temporal Partitioning Method for Real-Time Reconfigurable Systems

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1 A Icremetal Temporal Partitioig Method for Real-Time Recofigurable Systems HAMID R. AHMADIFAR, FARHAD MEHDIPOUR*, MORTEZA S. ZAMANI*, ** Departmet MEHDI of Iformatics, SEDIGHI* ad KAZUAKI MURAKAMI** Graduate School of Iformatio Egieerig Faculty Guila Uiversity, Rasht, p.b IRAN *IT ad Computer Egieerig Departmet Amirkabir Uiversity of Techology #424 Hafez Ave.,Tehra IRAN Sciece ad Electrical Egieerig Kyushu Uiversity 6-1 Kasuga-Koe, Kasuga, Fukuoka JAPAN Abstract: I this paper, a temporal partitioig algorithm is preseted which partitios data flow graphs i a realtime domai. Timig costrait is a critical factor i temporal partitioig of real-time recofigurable desig. A icremetal algorithm is preseted to partitio data flow graphs while meetig the timig costraits by obtaiig the target umber of partitios. I additio, the proposed algorithm attempts to miimize the logic resources used for implemetig the real-time applicatio. I this algorithm, selectig the appropriate odes ad movig them betwee subsequet partitios results i more area balaced partitios ad less umber of partitios. Key-Words: Recofigurable computig system, Temporal partitioig, Real-time system, Data flow graph. 1 Itroductio Recetly, field-programmable gate arrays (FPGA) have played a importat role i the realizatio of realtime recofigurable applicatios. We discuss here the partitioig problem for ru-time recofigurable systems (RTR). I the task of implemetig a algorithm o recofigurable hardware, two approaches could be distiguished [1]. I the first case, we have to fit a algorithm with a optioal time costrait i a existig system made from a host CPU coected to a recofigurable logic array. I this case, the goal of a optimal implemetatio is to miimize oe or more of the followig criteria: processig time, memory badwidth, umber of recofiguratios ad power cosumptio. I the secod case, we have to implemet a algorithm with a required time costrait o a system throughout the desig exploratio phase. The desig parameter is the size of the logic array that is used to implemet the data-path part of the algorithm. Here, a optimal implemetatio is the oe that leads to the miimal area of the recofigurable array. Previous works i the field of temporal partitioig ad sythesis for RTR architecture [2 10] assume that the recofigurable resources are limited. I this case, the goal is to miimize the processig time ad/or the memory badwidth requiremets. Amog the previous works, there is a GARP project called GARP [2]. The goal of GARP is the hardware acceleratio of loops i a C program by the use of a data path sythesis tool amely GAMA [3] ad the GARP recofigurable processor. GARP is a processor tightly coupled to a custom FPGA-like array ad desiged specially to speed-up the executio of geeral case loops. The logic array has a DMA feature ad is tailored to implemet 32-bit wide arithmetic ad logic operatios with cotrol logic. All this allows to miimize the recofiguratio overhead. GAMA is a fast mappig ad placemet tool for the data-path implemetatio

2 o FPGAs. It is based o a library of patters for all possible data-path operators. SPARCS [4,5] is a CAD tool developed for applicatio developmet o multi-fpga recofigurable computig architectures. Such architectures eed both spatial ad temporal partitioig; a geetic algorithm is used to solve the spatial partitioig problem. The mai objective used here is the data memory badwidth. Other works propose a strategy to automate the desig process that cosiders all possible optimizatios (partitioig ad task schedulig) that ca be carried out from a particular recofigurable system [6,7]. Shirazi et al. ad Luk et al. [8,9] proposed both a model ad a methodology to take advatage of commo operators i successive partitios. We proposed a similaritybased temporal partitioig algorithm which itegrated temporal partitioig ad physical desig to address the log recofiguratio overhead time [10]. I this paper, we propose a icremetal temporal partitioig which cosiders the real-time domai time costraits ad the amout of logic resources used to implemet cofiguratios. First we try to fid the miimal area that ca meet the timig costrait. This is differet from searchig the miimal memory badwidth or executio time to meet the resources costrait. I Sectio 2 of this paper, the problem formulatio is preseted. Sectio 3 explais the temporal partitioig algorithm proposed for partitioig of a data flow graph cosiderig the real time costrait. I Sectio 4, details of our proposed temporal partitioig algorithm are preseted. Sectio 5 discusses experimetal results ad fially, Sectio 6 cocludes the paper. 2 Problem Formulatio Temporal partitioig ca be stated as partitioig a data flow graph ito a umber of partitios such that each partitio ca fit ito a target device ad also, depedecies amog the graph odes are ot violated. Curretly, the temporal partitioig is ofte doe at boudaries of algorithm operatios [11]. Temporal partitioig algorithms usually take a data flow graph (DFG) as iput. The proposed methods are ofte based o elemetary arithmetic ad logic operatios of the algorithm (such as adder, subtractor, multiplier etc.). I other words, the odes of DFG represet predesiged modules i a library. Temporal partitioig leads to a register trasfer level (RTL) decompositio of the data flow graph (DFG). The partitioig for a real-time applicatio could be cosidered as a time costraied resource allocatio problem. To formulate the problem, firstly, the algorithm ca be modeled as a acyclic DFG where the set of vertices correspods to the arithmetic ad logical operators ad the set of directed edges represets the data depedecies betwee operatios. Secodly, the applicatio has a critical time costrait T. The problem to be solved is: For a give FPGA family, oe must fid the set of partitios or sub-graphs of DFG where: Υ = DFG i=1 ( is the umber of partitios ad P i is the ith partitio) ad the data depedecies modeled by the set of vertices ad also requires the miimal amout of FPGA resources. Our method, which partitios a DFG of a real time applicatio ad attempts to use miimal area, is depicted i Fig Temporal Partitioig for a Real- Time Applicatio I order to reduce the search domai, we first estimate the miimum umber of partitios ad the appropriate target device size. To do this, we use a library of modules based o the target device. The mai costrait for real-time applicatios is the eed for real-time processig. For a give FPGA device with recofiguratio time of µ Full, the followig iequality has to be satisfied: T > ( 1) µ Full + T P (1) Where is the umber of partitios (-1 is the umber of recofiguratios), T is the upper limit of processig time (time costrait) ad T P is the total executio time of DFG. T P could be determied by a full FPGA implemetatio of a DFG with o area costrait (Fig. 1). Usig the above iequality, the maximum umber of partitios is obtaied as follows: T T = P + 1 µ Full (2) I additio we obtai the correspodig miimum device size: DFGSize DeviceSize = = Size( Module( i)) (3) Υ N i= 1 P i

3 where N is the umber of modules i DFG ad Size(Module(i)) is the umber of CLBs 1 for Module(i) i the target-depedet library. O the other had, the miimum FPGA size should be larger tha the size of the largest module i the library plus its required memory size. Therefore, the iitial miimum partitio size ca be determied as follows: DFGSize DeviceSize = Max(, Size( Module( k)) + Memory( Module( k)) (4) Where k is the idex of the largest module i DFG ad Memory(Module(k))is the required umber of CLBs for trasferrig data betwee module k ad its depedet descet modules i DFG. From the aalysis of the value of, i order to realize the implemetatios, proper decisio ca be made, therefore differet cases could be cosidered: 1) > 1 : This meas that it is possible to realize a temporal partitioig. I this case, reductio of logic area is possible. 2) = 1 : I this case, oly a full FPGA implemetatio without recofiguratio ca meet the costraits. 3) < 1 : This meas that the recofigurable implemetatio of DFG caot meet the time costrait. 4 Our Temporal Partitioig Algorithm I a recofigurable system, cofiguratios are swapped i/out at ru-time duratio. The umber of recofiguratios is a importat factor to determie the overall ru-time. Recofiguratio overhead time is usually the domiat time factor. We propose a icremetal temporal partitioig algorithm for realtime recofigurable applicatios. I this algorithm, first we determie the maximum umber of partitios. Appropriate device size is determied with respect to the umber of partitios. The, a iterative partitioig process tries to perform the partitioig to obtai desired the umber of partitios after a iitial partitioig. This icremetal algorithm icreases the device size for the ext iteratio util the requested umber of partitios is achieved. Fially, a post processig algorithm attempts to miimize the required device size. The geeral outlie of our proposed method is depicted i Fig Iitial Partitioig I the first stage of the proposed method, a iitial temporal partitioig algorithm is performed. I order to esure that all computatios will be performed correctly whe the circuit is decomposed ito stages, certai temporal costraits must be satisfied [12]. For example, a ode ca be executed if all of its predecessors have already bee executed. I [12, 13], i the first stage, a level assigmet is performed accordig to the as soo as possible (ASAP) algorithm. ASAP schedules a data flow graph i a attempt to miimize latecy by topologically sortig of the odes of the graph. I the partitioig stage of the DFG, the level umber of modules, their sizes ad the size of the target hardware are the most importat factors which should be cosidered. Fig.1. Geeral outlie of our icremetal temporal partitioig method 1 - The target FPGA cotais a square array of logic blocks called cofigurable logic blocks (CLB s) embedded i a uiform mesh of routig resources. 4.2 Icremetal Temporal Partitioig Iitial partitioig of the DFG is doe based o the required umber of partitios which is the critical costrait i a real-time system. After the iitial temporal partitioig, a icremetal algorithm tries to achieve the desired umber of partitios. Iitial partitioig is doe based o the iitial partitio size determied i the first stage ad the target device size costrait. Therefore, it is possible that the umber of partitios obtaied is more that the requested umber. I the secod stage, the appropriate device size is

4 determied based o the iitial partitio size ad the extra logic area to reach the target partitio umber. For example, if the umber of partitios achieved from the iitial curret partitioig is ad the desired umber of partitios is, the ew device size of the ext iteratio ca be computed as follows: + P( i) i= 1 DeviceSizeew = DeviceSizecurret + (5) I the ext iteratio, a icremetal temporal partitioig is doe by swappig modules betwee subsequet partitios. This algorithm attempts to icrease the area balacig of partitios which results i less umber of partitios. I the proposed icremetal temporal partitioig algorithm, cadidate odes i each partitio are first selected ad the, they are moved to the previous partitio util the area costrait is met. I additio, a post processig is doe to miimize the device size used for the implemetatio. Our proposed temporal partitioig algorithm pseudo code is depicted i Fig. 2. Temporal partitioig ca be doe iteratively which cosume more compilatio time. Usig the icremetal method takes much less time for geeratig the partitios. 5 Experimetal Results I our preseted temporal partitioig algorithm the iput is take as a DFG. A library cosistig of the required modules has bee developed. Fig. 3 illustrates the CAD flow we used for geeratig the modules. At the begiig, each module was described i VHDL ad was the sythesized by Leoardo Spectrum sythesis tool to obtai a structural descriptio of the module based o logic gates. The SIS sythesis package [14] was used to perform techologyidepedet logic optimizatio of each module circuit. Next, each circuit was techology-mapped ito 4- LUTs ad flip flops by FlowMap [15]. The output of FlowMap is a etlist of LUTs ad flip flops i.blif format. T-VPack [16,17] the packed this etlist of 4- LUTs ad flip flops ito more coarse-graied logic blocks, ad geerated a etlist i.et format. We used VPR [16] as a popular tool for placemet ad routig of the cofiguratios. Temporal Partitioig Algorithm for Real-Time Applicatios: -Determie target umber of partitios () accordig to Equatio 2; -Determie miimum ad maximum ode size (MaxNodeSize ad MiNodeSize); -Determie total size of DFG based o Equatio 3 (DFGSize); - DeviceSize= Iitial Device Size (Equatio 4); -Alig DeviceSize to MiNodeSize (DeviceSize= (DeviseSize/MiNodeSize +1)*MiNodeSize); - Perform the Iitial temporal Partitioig - While (umber of partitios obtaied > ) - Compute the ew device size accordig to Equatio 5 - Alig DeviceSize to MiNodeSize; - Perform the icremetal temporal partitioig process ad attempt to preserve the area balacig of partitios. Icremetal Temporal Partitioig Algorithm: For i = 0 to umber of partitios -1 For j= i+1 to umber of partitios CadidatesNodeNo= FidCadidates(j) // This fuctio returs the umber of cadidate odes ad a list of cadidate odes of partitio j. For k= 0 to CadiatesNodeNo Add kth cadidate ode from cadidate ode list to partitio i Determie partitio size of partitio i if size of partitio i is larger tha DeviceSize remove the ode curretly added from partitio i FidCadidates (j){ For i= 0 to umber of members of partitio j if all parets of a ode which is member of partitio j are partitioed add the ode to cadidates list icrease the cadidates ode umber retur cadidates ode umber ad cadidates odes list } Fig. 2. Pseudo code for icremetal temporal partitioig algorithm preseted for real-time applicatios The architecture of the target programmable device was chose to be a Xilix Virtex (XCV100) FPGA. VPR uses a architecture profile i which the architecture details ca be specified. Table 1 shows some of the modules stored i the library ad their sizes i terms of the umber of CLB s used. To our kowledge, there is ot ay commo use or stadard bechmarks for static data flow graphs. We chose five static data flow graphs [12] ad applied our tool to them from.

5 Fig. 3. Geeratig library cells i.et format We implemeted the proposed temporal partitioig algorithm ad fed the data flow graphs to it. I our experimets, we assumed that the upper time limit to applicatio executio is 30 microsecod ad the time eeded for full recofiguratio is 10 microsecod. Table 2 shows the results of the experimets. I this table, the total DFG size, the umber of target partitios to be achieved, the iitial device size, the iitial umber of partitios, the umber of iteratios for icremetal algorithm, differet device sizes durig the icremetal partitioig algorithm, fial device size, average partitios size, ad deviatio from average partitio size is depicted. We cosider the deviatio from average partitio size as a balacig factor for the cofiguratios geerated. Smaller deviatio represets the more balaced partitios which ca result i less umber of cofiguratios. Table 1. Some 16-bit operatios ad the umber of CLB s used i Xilix Virtex100 FPGA Operatio Type No. of CLB s Used ADD 11 SUB 10 XOR 4 CMP 5 MUX 4 MULT 195 ROT 4 6 Coclusio Timig is the mai costrait i real time implemetatio of a recofigurable system. Temporal partitioig is a importat stage of recofigurable system desig which attempts to partitio a DFG by cosiderig the timig ad resource costraits ad depedecies betwee odes i the DFG. I this paper, we proposed a icremetal temporal partitioig algorithm. This method starts with estimatig the iitial umber of partitios ad iitial device size ad the rus icremetally to achieve the target umber of partitios to meet the real-time system costrait. I additio, this algorithm tries to obtai a miimum device size. The proposed icremetal temporal partitioig algorithm icreases the device size util the target umber of partitios is obtaied. This algorithm attempts to icrease the balacig of partitios by movig the cadidate odes betwee subsequet partitios. This results i less deviatio from average partitio size ad less umber of partitios. Table 2. Results of recofigurable real-time implemetatios of DFGs Data Flow Graph DFG1 DFG2 DFG3 DFG4 DFG5 Total DFG size Number of target partitios Iitial device size Iitial umber of partitios Number of iteratios Device sizes 360, 304, 370, 410, 320, durig algorithm ruig , , 470 Fial device size Average Partitio Size Deviatio from average size (Balacig factor) Refereces [1] X. Zhag, K.W. Ng, A review of high-level sythesis for dyamically recofigurable FPGA s, Microprocessors ad Microsystems, Elsevier, vol. 24, 2000, pp [2] T.J. Callaha, J. Hauser, J. Wawrzyek, The GARP architecture ad C compiler, IEEE Computer, vol. 33, o. 4, 2000, pp [3] T.J. Callaha, P. Chog, A. DeHo, J. Wawrzyek, Fast module mappig ad placemet for data paths i FPGA s, Proceedigs of the ACM/SIGDA Sixth Iteratioal

6 Symposium o Field Programmable Gate Arrays, Moterey, CA, February 1998, pp [4] S.V. Sriivasa, S. Govidaraja, R. Vemuri, Fiegraied ad coarse-graied behavioral partitioig with effective utilizatio of memory ad desig space exploratio for multi-fpga architectures, IEEE Trasactios o VLSI Systems, vol. 9, o. 1, 2001, pp [5] M. Kaul, R. Vemuri, Optimal temporal partitioig ad sythesis for recofigurable architectures, Iteratioal Symposium o Field-Programmable Custom Computig Machies, April 1998, pp [6] R. Maestre, F. Kurdahi, M. Feradez, R. Hermida, N. Bagherzadeh, H.Sigh, A framework for recofigurable computig: task schedulig ad cotext maegemet, IEEE Trasactios o VLSI Systems, vol. 9, o. 6, 2001, pp [7] M. Karthikeya, P. Gajjala, B. Diesh, Temporal partitioig ad schedulig data flow graphs for recofigurable computer, IEEE Trasactios o Computers, vol. 48, o. 6, 1999, pp [8] N. Shirazi, W. Luk, P.Y.K. Cheug, Automatig productio of rutime recofiguratio desigs, i: K.L. Pocek, J. Arold (Eds.), Proceedigs of IEEE Symposium o FPGA s Custom Computig Machies, IEEE Computer Society Press, 1998, pp [9] W. Luk, N. Shirazi, P.Y.K. Cheug, Modelig ad optimizig rutime recofiguratio systems, i: K.L. Pocek, J. Arold (Eds.), Proceedigs of IEEE Symposium o FPGA s Custom Computig Machies, IEEE Computer Society Press, 1996, pp [10] F. Mehdipour, M. Saheb Zamai, M. Sedighi, A Itegrated Temporal Partitioig ad Physical Desig Framework for Static Compilatio of Recofigurable Computig System, The Iteratioal Joural of Microprocessors ad Microsystems, Elsevier, 2005, Accepted for publishig. [11] C. Taougast, Y. Berviller, P. Bruet, S. Weber, H. Rabah, Temporal partitioig methodology optimizig FPGA resources for dyamically recofigurable embedded real-time system, The Iteratioal Joural of Microprocessors ad Microsystems, vol. 27, 2003, pp [12] C. Bobda, Sythesis of dataflow graphs for recofigurable systems usig temporal partitioig ad temporal placemet, Ph.D thesis, Faculty of Computer Sciece, Electrical Egieerig ad Mathematics, Uiversity of Paderbor, [13] G.D. Micheli, Sythesis ad optimizatio of digital circuits, McGraw-Hill, [14] Setovich E M, SIS: A system for sequetial circuit aalysis, Tech. Report No.UCB/ERLM92/41, Uiversity of Califoria, Berkeley, [15] J. Cog, Y. Dig, Flowmap: A optimal techology mappig algorithm for delay optimizatio i lookup-table based FPGA desigs, IEEE Trasactios o CAD, 1994, pp [16] V. Betz, J. Rose, A. Marquardt, Architecture ad CAD for deep-submicro FPGAs, Kluwer Academic Publishers, [17] V. Betz, VPR ad T-VPack1 user s maual (Versio 4.30),