IN-MEMORY ASSOCIATIVE COMPUTING

Transcription

1 IN-MEMORY ASSOCIATIVE COMPUTING AVIDAN AKERIB, GSI TECHNOLOGY

2 AGENDA The AI computational challenge Introduction to associative computing Examples An NLP use case What s next?

3 THE CHALLENGE IN AI COMPUTING AI Requirement 32 bit FP Multi precision mining, etc. Scaling Sort-search speech, classify image/video Neural network learning Neural network inference, data Data center Top-K, recommendation, Heavy computation Non linearity, Softmax, exponent, normalize Bandwidth Use Case Example Required for speed and power

4 CURRENT SOLUTION Question CPU Answer General Purpose GPU Very Wide Bus DRAM Tens of Cores Bottleneck when register file data needs to be replaced on a regular basis Limits performance Increases power consumption Thousands of Cores Does not scale with the search, sort, and rank requirements of applications like recommender systems, NLP, speech recognition, and data mining that requires functions like Top-K and Softmax.

5 GPU VS CPU VS FPGA

6 GPU VS CPU VS FPGA VS APU

7 GSI S SOLUTION APU ASSOCIATIVE PROCESSING UNIT Question Millions Processors Simple CPU Simple & Narrow Bus Answer APU Associative Memory Computes in-place directly in the memory array removes the I/O bottleneck Significantly increases performances Reduces power

8 IN-MEMORY COMPUTING CONCEPT

9 THE COMPUTING MODEL FOR THE PAST 8 YEARS Read Write Address Decoder Read Write ALU Sense Amp /IO Drivers

10 THE CHANGE IN-MEMORY COMPUTING NOR NOR Read Read Read Write Write Read Simple Controller Patented in-memory logic using only Read/Write operations Any logic/arithmetic function can be generated internally

11 CAM/ ASSOCIATIVE SEARCH Records in the combines key goes to the read enable Values Duplicate vales with inverse data =match RE RE RE RE KEY: Search Duplicate the key with inverse. Move the original key next to the inverse data

12 TCAM SEARCH WITH STANDARD MEMORY CELLS Don t care Don t care Don t care 2

13 TCAM SEARCH WITH STANDARD MEMORY CELLS in the combines key goes to the read enable Insert zero instead of don t-care Duplicate data. Inverse only to those which are not don t care = match =match RE RE RE RE KEY: Search Duplicate the key with inverse. Move The original Key next to the inverse data 3

14 COMPUTING IN THE BIT LINES Vector A Vector B C=f(A,B) Each bit line becomes a processor and storage millions of bit lines = millions of processors

15 NEIGHBORHOOD COMPUTING Shift vector C=f(A,SL(B,)) Parallel shift of bit cycle sections Enables neighborhood operations such as convolutions

16 SEARCH & COUNT Search Count = 3 Search (binary or ternary) all bit lines in cycle 28 M bit lines => 28 Peta search/sec Key applications for search and count for predictive analytics: Recommender systems K-nearest neighbors (using cosine similarity search) Random forest Image histogram Regular expression

17 DATABASE SEARCH AND UPDATE Content-based search, record can be placed anywhere Update, modify, insert, delete is immediate Exact Match CAM/TCAM Similarity Match In-Place Aggregate

18 TRADITIONAL STORAGE CAN DO MUCH MORE Standard memory cell Standard memory cell bit 2 bits 2 input NOR, TCAM cell 3 Bits 3 input NOR, 2 Input NOR + Output 4 State CAM Standard memory cell Standard memory cell

19 CPU/GPGPU VS APU

20 ARCHITECTURE

21 SECTION COMPUTING TO IMPROVE PERFORMANCE MLB section 24 rows Memory control Connecting Mux MLB section Connecting mux... Instr. Buffer 2

22 COMMUNICATION BETWEEN SECTIONS Shift between sections enable neighborhood operations (filters, CNN etc.) Store, compute, search and move data anywhere 22

23 APU CHIP LAYOUT 2M bit processors or 28K vector processors runs at G Hz with up to 2 Peta OPS peak performance

24 EVALUATION BOARD PERFORMANCE Precision : Unlimited : from bit to 6 bits or more. 6.4 TOPS (FP) 8 Peta OPS for one bit computing or 6 bit exact search Similarity Search, Top-k, min, max, Softmax, O() complexity in μs, any size of K compared to ms with current solutions In-memory IO 2 Petabit/sec > X GPGPU/CPU/FPGA Sparse matrix multiplication > X GPGPU/CPU/FPGA

25 APU SERVER 64 APU chips, GByte DDR, From TFLOPS Up to 28 Peta OPS with peak performance 28TOPS/W O() Top-K, min, max, 32 Peta bits/sec internal IO < K Watts > X GPGPs on average Linearly scalable Currently 28nm process and scalable to 7nm or less Well suited to advanced memory technology such as non volatile ReRAM and more

26 EXAMPLE APPLICATIONS

27 K-NEAREST NEIGHBORS (K-NN) Simple example: N = 36, 3 groups, 2 dimensions (D = 2 ) for X and Y K = 4 Group Green selected as the majority For actual applications: N = Billions, D = Tens, K = Tens of thousands

28 K-NN USE CASE IN AN APU Item Item2 Item N Item N Item 3 Item Item 2 Features of item Features of item 2 Features of item N Item features and label storage Q Compute cosine distances for all N in parallel ( μs, assuming D=5 features) Computing Distribute data Area 2 ns (to all) K Mins at O() complexity ( 3μs) In-Place ranking Majority Calculation With the data base in an APU, computation for all N items done in.5 ms, independent of K

29 LARGE DATABASE EXAMPLE USING APU SERVERS Number of items: billions Features per item: tens to hundreds Latency: msec Throughput: Scales to M similarity searches/sec k-nn: Top, nearest neighbors

30 EXAMPLE K-NN FOR RECOGNITION Image Convolution Layer Feature Extractor (Neural Network) K-NN Classifier (Associative Memory) Text BOW, Word Embedding

31 K-MINS: O() ALGORITHM MSB LSB KMINS(int K, vector C){ M :=, V := ; FOR b = msb to b = lsb: D := not(c[b]); N := M & D; cnt = COUNT(N V) IF cnt > K: M := N; ELIF cnt < K: V := N V; ELSE: // cnt == K V := N V; EXIT; ENDIF ENDFOR } C C C 2 N

32 K-MINS: THE ALGORITHM V N V N M D C[] KMINS(int K, vector C){ M :=, V := ; FOR b = msb to b = lsb: D := not(c[b]); N := M & D; cnt = COUNT(N V) IF cnt > K: M := N; ELIF cnt < K: V := N V; ELSE: // cnt == K V := N V; EXIT; ENDIF ENDFOR } cnt=

33 K-MINS: THE ALGORITHM V N V N M D C[] KMINS(int K, vector C){ M :=, V := ; FOR b = msb to b = lsb: D := not(c[b]); N := M & D; cnt = COUNT(N V) IF cnt > K: M := N; ELIF cnt < K: V := N V; ELSE: // cnt == K V := N V; EXIT; ENDIF ENDFOR } cnt=8

34 K-MINS: THE ALGORITHM KMINS(int K, vector C){ M :=, V := ; FOR b = msb to b = lsb: D := not(c[b]); N := M & D; cnt = COUNT(N V) IF cnt > K: M := N; ELIF cnt < K: V := N V; ELSE: // cnt == K V := N V; EXIT; ENDIF ENDFOR } final output V C O() Complexity

35 DENSE (XN) VECTOR BY SPARSE NXM MATRIX Input Vector Sparse Matrix Output Vector APU Representations and Computing Column Row Search all columns for row = 2 :Distribute -2 : 2 Cy Search all columns for row = 3 :Distribute 3 : 2 Cy Search all columns for row = 4 :Distribute - : 2 Cy Multiply in Parallel : Cy Shift and Add all belonging to same column Complexity including IO : O (N +logβ) where β is the number of nonzero elements in the sparse matrix N << M in general for recommender systems

36 SPARSE MATRIX MULTIPLICATION PERFORMANCE ANALYSIS G3 circuit matrix.5m X.5M sparse matrix Roughly 8M nonzero elements 2 GFLOPS with GPGPU solution APU solution provides 64 TFLOPS using the same amount of power as the GPGPU solution above > 5x improvement with APU solution

37 ASSOCIATIVE MEMORY FOR NATURAL LANGUAGE PROCESSING (NLP) Q&A, dialog, language translation, speech recognition etc. Requires learning things from the past needs memory More memory, more accuracy i.e. Dan put the book in his car,.. Long story here. Mike took Dan s car Long story here. He drove to SF Q : Where is the book now? A: Car, SF

38 END-TO-END MEMORY NETWORKS End-To-End Memory Networks, (Weston et. al., NIPS 25). (a): Single hope, (b) 3 hops

39 Q&A : END TO END NETWORK

40 REQUIREMENTS FOR AUGMENTED MEMORY Vertical Embedding Multiplication Input features selectedto next coloumn, Columns to any and other horizontal location or sumlocation based on content Compute softmax to selected Output Cosine Similarity Search + Top-K

41 APU MEMORY FOR NLP 2 N- Control I O m i M T i Broadcast input I to selected columns Compute any function at selected columns Generate output Generate tags for selection i m i i m i

42 GSI SOLUTION FOR END TO END Constant time of 3 µsec per iteration, any memory size.

43 PROGRAMING MODEL

44 PROGRAMMING MODEL Application (C++, Python) HOST Framework (TensorFlow ) Graph Execution and Tasks Scheduling APU (Associative Processing Unit Hardware) Device

45 A TF EXAMPLE: MATMUL a = tf.placeholder(tf.int32, shape=[3,4]) b = tf.placeholder(tf.int32, shape=[4,6]) c = tf.matmul(a, b) # shape = [3,6] matmul c a b

46 A TF EXAMPLE: MATMUL GRAPH PREPARATION a = tf.placeholder(tf.int32, shape=[3, 4]) b = tf.placeholder(tf.int32, shape=[4, 6]) c = tf.matmul(a, b) APU DEVICE SPACE host apu device (tf+eigen) gnl_create_array(a) gnl_create_array(b) gnl_create_array(c) L4 a b c apuc s L MMB

47 A TF EXAMPLE: MATMUL GVML_SET, GVML_MUL with tf.session() as sess: result = sess.run(c, feed_dict= {a: [[ ] b: [[ ] [ -3 4] [ ] [ ]], [ ] [ ]]}) APU DEVICE SPACE gnlpd_dma_6b_start(gnlpd_sys_2_vmr, ) L a b c dma keeps loading data to apuc dma copy L4 to L gvml_set_6( ) gnlpd_mat_mul(c,a,b) gvml_set_6( ) gvml_mul_s6( ) apuc controller c while matmul is being computed in apuc X gvml_mul_s6( ) L MMB

48 TENSORFLOW ENHANCEMENT: FUSED OPERATIONS a = tf.placeholder(tf.int32, shape=[3,4]) b = tf.placeholder(tf.int32, shape=[4,6]) c = tf.matmul(a, b) # shape = [3,6] d = tf.nn.top_k(c, k=2) # shape = [3,2] fused The two operations are computed inside the apuc top_k Data stays in L d No IO operations between them Saves valuable data transfer time and power fused(matmul,top_k) matmul c a b

49 A TF EXAMPLE: MATMUL CODE EXAMPLE APU DEVICE c L MMB APL_FRAG add_u6(rn_reg x, RN_REG y, RN_REG t_xory, RN_REG t_ci) { SM_XFFFF: RL = SB[x]; // RL[-5] = x SM_XFFFF: RL = SB[y]; // RL[-5] = x y { SM_XFFFF: SB[t_xory] = RL; // t_xory[-5] = x y SM_XFFFF: RL = SB[x, y]; // RL[-5] = x&y } // Add init state: // : RL = co[] //..5: RL = x&y { (SM_X << ): SB[t_ci] = NRL; // t_ci[5,9,3] = x&y (SM_X << ): RL = SB[t_xory] & NRL; // RL[] = Cout[] = x&y ci(x y) // 5,9,3: RL = Cout[5,9,3] = x&y ci(x y) } { } { } { }... (SM_X << 4): RL = SB[t_xory]; (SM_X << 2): SB[t_ci] = NRL; // Propagate Cin (SM_X << 2): RL = SB[t_xory] & NRL; // Propagate Cout (SM_X << 5): RL = SB[t_xory] & NRL; // Propagate Cout (SM_X << 3): SB[t_ci] = NRL; // Propagate Cin (SM_X << 3): RL = SB[t_xory] & NRL; // Propagate Cout (SM_X << 6): RL = SB[t_xory] & NRL; // Propagate Cout (SM_X << 5): GL = RL; // RL[4,8,2] = Cout[4,8,2] = x&y &(x y) (SM_X << 4): SB[t_ci] = NRL; // t_ci[8,2,6] = Cout[7,, 5] SM_X: SB[t_ci] = GL; // t_ci[8,2,6] = Cout[7,, 5] (SM_X << 7): RL = SB[t_xory] & NRL; // Propagate Cout (SM_X << 5): GL = RL;

50 FUTURE APPROACH NON VOLATILE CONCEPT

51 SOLUTIONS FOR FUTURE DATA CENTERS CPU Register File L/L2/L3 DRAM ASSOCIATIVE High endurance Full computing (floating points etc.) requires read & write : Low endurance Data search engines (read most of the time) Standard SRAM Based STT-RAM RAM Based PC-RAM Based ReRam Based Flash HDD Volatile Non Volatile Mid endurance Machine learning, malware detection detection etc., : Much more read and much less write

52 THANK YOU