Read Only Memory ROM

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Diana Maxwell
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1 Read Only Memory ROM A read only memory have address inputs and data outputs With m address lines you can access the 2 m different memory addresses At each address, there is one data word with n bits Usually, the ROM also has an Output Enable (OE) input A m-1 ROM Dn-1 A m-2 D n-2 A 1 A 0 2 m x n D 1 D 0

2 Read Only Memory ROM Exemple of a ROM Read only memory: ROM 4M 512k 8 bit CE OE Chip Enable activates the chip Output Enable connects memory to outputs (otherwise they are in the three-state mode)

3 A small ROM Possible memory content 8x4 ROM A 2 A 1 A 0 D 3 D 2 D 1 D 0 A 2 A 1 A 0 D 3 D 2 D 1 D

4 ROM Pullup 1 V DD GND Address Adress Content Innehåll x 1 x 0 z 3 z 2 z 1 z x 0 x Ord 0 GND Ord 1 Ord 2 GND Ord 3 OE OE=Output Enable z 3 z 2 z 1 z 0

5 ROM implementation of combinatorical functions x n-1 x 1 x 0 f(x n-1,,x 1,x 0 ) z m-1 z 1 z 0 Adress Address Content Innehåll x n-1 x 1 x 0 z m-1 z 1 z A ROM having n inputs with m outputs can be used to implement a combinatorial function with m outputs and 2 n min-terms

6 ROM implementation of sequence circuit x n-1 x 4 x 3... f(x n-1,,x 1,x 0 ) z m-1 z 4 z 3... Adress Address Innehåll Content x n-1 x 3 x 2 x 1 x 0 z m-1 z 3 z 2 z 1 z x 0 z 0 CP A Moore-machine = one ROM and a register with D-flipflops With feedbacks a ROM can be used to generate sequences and implement state machines

7 Read and Write Memory Random Access Memory RAM RAM-memory has also a Write (WR) input which allows us to enter a data word at a given address D n-1 D 0 are both inputs and outputs. A m-1 RAM Dn-1 A m-2 D n-2 A 1 A 0 OE WR 2 m x n D 1 D 0

8 Read-Write-Memory Random Access Memory RAM Read/Write memory: SRAM 4M 512k 8 bit RD WR CS RD WR Chip Select activates the chip RD read from memory, data outputs are active WR write to memory (at write the data outputs are in the three-state mode )

9 SRAM Static Random Access Memory A SRAM-memory consits of a matrix of SRAM-cells To write Data is used at input! Sel is set to 1 and the value that is on Data is stored in the cell Data Sel Strongest! To read Data is used as output! Sel is set to 1, and the value from the cell is present at the output

10 SRAM Data 1 Data 0 A matrix is formed by 2 m x n SRAM-cells Sel 0 Sel 1

11 SRAM-memory tristate buffers are used to ensure that you just either reads or writes Data inputs Write Sel 0 Sel 1 d n 1 d n 2 d 0 Address a 0 a 1 a m 1 m -to-2 m decoder Sel 2 Sel 2 m 1 Read Data outputs q n 1 q n 2 q 0

12 DRAM Dynamic RAM SRAM memorycell needs 4 transistors and it becomes too costly to implement a large memory DRAM memorycell is using only one transistor and one capacitor

13 DRAM Memorycell DRAM-cell consists of only one transistor and one capacitor Skrivning To load the cell the word line is set to 1 The cell now optains the value from the bit line Word Line C 1-bit DRAM cell Bit Line

14 DRAM Memorycell To read is a little bit more complex You do not want to lose the information when reading! The bit-line is set at a voltage between the High and Low To read the cell the word line is set to 1 The bitline now adjusts it s voltage to a voltage up or down An extra circuit (per bit line) senses the current change direction to create a real 0 or 1 Aftervards the charge in the capacitor C must be restored! Word Line C 1-bit DRAM cell Bit Line

15 DRAM Memory Memorymodule with 8 chips Chip 256Mbit (32M 8)

16 SRAM vs DRAM SRAM takes up more space but a DRAM requires a simpler access logic and is therefore faster (but also more expensive) DRAM is used for random access memories in our regular computers When you remove the power you loses the contents of SRAM or DRAM memory!

17 Volatile memorys Memory types Memories lose their information if power is disconnected static RAM (SRAM) dynamic RAM (DRAM) Non-volatile memorys Memories keep their information if power is disconnected Flash (blockwise writing) EPROM, EEPROM (bytewise writing) We need a combination of different memories in an electrotechnical design!

18 Non-volatile memory Flash-memory low cost and low power consumption can be erased and updated but it takes much more time than in a RAM-memory

then reprogrammed. Hence the "window" on the top side of the chip.

19 EPROM Erasable Programmable ROM Programmable ROM (can be programmed with a chip programmer) Erasable - can be erased using ultraviolet light and then reprogrammed. Hence the "window" on the top side of the chip. When working with modern electronic equipment you will not have to meet the EPROM.

20 Memory technologies Technology Accesstime Cost $/GB SRAM 1 ns 1000 DRAM 50 ns 100 HDD 10 ms 1 Fast memory is expensive and inexpensive memories are slow! Principle numbers.

21 Logic in a microprocessor There are both combinatorial and sequential logic in a processor. Control logik is a statemachine while the ALU are mostly combinatorial.

22 Registry element Symbol D in WR Clock Dut D in Dut > WR WR / hold WR = 1 synchronous writing WR = 0 hold 1 logic element in a FPGA

23 Register Symbol WR > 32 bit register is 32 logic elements in a FPGA

Program counter -register Register: hoppadress JA Jump/Run Clock > 4 Register: programräknare MUX PC ADD 32 bit instruktion All processors have a program counter pointing out where the next

24 Program counter -register Register: hoppadress JA Jump/Run Clock > 4 Register: programräknare MUX PC ADD 32 bit instruktion All processors have a program counter pointing out where the next instruction is to be fetched in the memory. Program memory: Byteaddressed An instruction is 4 bytes PC, Program Counter counts up with "4" after each instruction. At the program jumps PC is loaded with the jump address JA (Jump Address) and then the program continues from there.

25 Register with threestateoutpot Symbol WR > OE Symbol bidirectional (inputs and outputs are connected together) > WR OE

26 Register and Databus OE > WR OE > WR Databus Several bidirectional registers with three state outputs can be connected to each other to form a common data bus.

27 Register and Databuss OE > WR OE > WR Databus Data can now be controlled to be copied between all registers on the data bus.

28 Dubble port register Symbol WR > OE1 OE2 More Dubble portregisters can be paired with each other for two common output buses.

29 Mikrocomputer - architecture The computer registers. A bit dubbleport Register File

30 Mikrocomputer - add Example Add instruction 1. The instruction add R1,R2,R3 is fetched from memory (as binary code) 2. The instruction is decoded

31 Mikrocomputer - add Example Add instruction 1. The instruction add R1,R2,R3 is fetched from memory (as binary code) 2. The instruction is decoded

32 Mikrocomputer - add Example Add instruction 3. Register R2 and R3 are add with the ALU 4. The Result is written to register R1

33 Mikrocomputer - add Example Add instruction 3. Register R2 and R3 are add with the ALU 4. The Result is written to register R1 it requires several clock pulse periods for the implementation of an instruction. (maybe you could arrange a Pipeline? )

Register file The processor has a 32 32 bit register file (with dual port registers). It can therefore be simultaneously read from any two registers or write to a register per clock pulse.

34 Register file The processor has a bit register file (with dual port registers). It can therefore be simultaneously read from any two registers or write to a register per clock pulse. The computer instruction add, means the sum add R1, R2,R3 R2+R3 is put in R1 A register file whith 32 registers are 32 2 = 1024 logic elements in a FPGA A 32 bit adder are 32 logicelements in a FPGA R0 R bit register file ADD

35 Possible instruction format 32 bit instruction add r1, r2, r3 5 bit 1 of 32 reg 5 bit 1 of 32 reg 5 bit 1 of 32 reg Operatingcode we want to add

Address connections Data connections Selection connections

Address connections Data connections Selection connections Interface (cont..) We have four common types of memory: Read only memory ( ROM ) Flash memory ( EEPROM ) Static Random access memory ( SARAM ) Dynamic Random access memory ( DRAM ). Pin connections common