VLSI Physical Design: From Graph Partitioning to Timing Closure
|
|
- Dinah Reed
- 6 years ago
- Views:
Transcription
1 Chapter Netlist and System Partitioning Original Authors: Andrew B. Kahng, Jens, Igor L. Markov, Jin Hu
2 Chapter Netlist and System Partitioning. Introduction. Terminology. Optimization Goals. Partitioning Algorithms.. Kernighan-Lin (KL) Algorithm.. Extensions of the Kernighan-Lin Algorithm.. Fiduccia-Mattheyses (FM) Algorithm. Framework for Multilevel Partitioning.. Clustering.. Multilevel Partitioning. System Partitioning onto Multiple FPGAs
3 . Introduction System Specification ENTITY test is port a: in bit; end ENTITY test; Architectural Design Functional Design and Logic Design Partitioning Chip Planning Circuit Design Placement Physical Design Clock Tree Synthesis DRC LVS ERC Physical Verification and Signoff Fabrication Packaging and Testing Signal Routing Timing Closure Chip
4 . Introduction Circuit: Cut c b Cut c a Block A Block B Block A Block B Cut c a : four external connections Cut c b : two external connections
5 . Terminology Block (Partition) Graph G : Nodes,,. Cells Graph G : Nodes,,. Collection of cut edges Cut set: (,), (,), (,),
6 . Optimization Goals Given a graph G(V,E) with V nodes and E edges where each node v V and each edge e E. Each node has area s(v) and each edge has cost or weight w(e). The objective is to divide the graph G into k disjoint subgraphs such that all optimization goals are achieved and all original edge relations are respected.
7 . Optimization Goals In detail, what are the optimization goals? Number of connections between partitions is minimized Each partition meets all design constraints (size, number of external connections..) Balance every partition as well as possible How can we meet these goals? Unfortunately, this problem is NP-hard Efficient heuristics are developed in the 90s and 90s. They are high quality and in low-order polynomial time.
8 Chapter Netlist and System Partitioning. Introduction. Terminology. Optimization Goals. Partitioning Algorithms.. Kernighan-Lin (KL) Algorithm.. Extensions of the Kernighan-Lin Algorithm.. Fiduccia-Mattheyses (FM) Algorithm. Framework for Multilevel Partitioning.. Clustering.. Multilevel Partitioning. System Partitioning onto Multiple FPGAs
9 .. Kernighan-Lin (KL) Algorithm Given: A graph with n nodes where each node has the same weight. Goal: A partition (division) of the graph into two disjoint subsets A and B with minimum cut cost and A = B = n. Example: n = Block A Block B 9
10 .. Kernighan-Lin (KL) Algorithm Terminology Cost D(v) of moving a node v D(v) = E c (v) E nc (v), where E c (v) is the set of v s incident edges that are cut by the cut line, and E nc (v) is the set of v s incident edges that are not cut by the cut line. Node : D() = -= High costs (D > 0) indicate that the node should move, while low costs (D < 0) indicate that the node should stay within the same partition. Node : D() = -= 0
11 .. Kernighan-Lin (KL) Algorithm Terminology Gain of swapping a pair of nodes a und b g = D(a) + D(b) - * c(a,b), where D(a), D(b) are the respective costs of nodes a, b c(a,b) is the connection weight between a and b: If an edge exists between a and b, then c(a,b) = edge weight (here ), otherwise, c(a,b) = 0. The gain g indicates how useful the swap between two nodes will be The larger g, the more the total cut cost will be reduced
12 .. Kernighan-Lin (KL) Algorithm Terminology Node : Gain of swapping a pair of nodes a und b D() = -= g = D(a) + D(b) - * c(a,b), where D(a), D(b) are the respective costs of nodes a, b c(a,b) is the connection weight between a and b: If an edge exists between a and b, then c(a,b) = edge weight (here ), Node : D() = -= otherwise, c(a,b) = 0. g (,) = D() + D() - * c(a,b) = + = => Swapping nodes and would reduce the cut size by
13 .. Kernighan-Lin (KL) Algorithm Terminology Node : Gain of swapping a pair of nodes a und b D() = -= g = D(a) + D(b) - * c(a,b), where D(a), D(b) are the respective costs of nodes a, b c(a,b) is the connection weight between a and b: If an edge exists between a and b, then c(a,b) = edge weight (here ), Node : D() = -= otherwise, c(a,b) = 0. g (,) = D() + D() - * c(a,b) = + 0 = => Swapping nodes and would reduce the cut size by
14 .. Kernighan-Lin (KL) Algorithm Terminology Gain of swapping a pair of nodes a und b The goal is to find a pair of nodes a and b to exchange such that g is maximized and swap them.
15 .. Kernighan-Lin (KL) Algorithm Terminology Maximum positive gain G m of a pass The maximum positive gaing m corresponds to the best prefix of m swaps within the swap sequence of a given pass. These m swaps lead to the partition with the minimum cut cost encountered during the pass. G m is computed as the sum of Δg values over the first m swaps of the pass, with m chosen such that G m is maximized. m G m = g i i=
16 .. Kernighan-Lin (KL) Algorithm One pass Step 0: V = n nodes {A, B} is an initial arbitrary partitioning Step : i = Compute D(v) for all nodes v V Step : Choose a i and b i such that g i = D(a i ) + D(b i ) * c(a i b i ) is maximized Swap and fix a i and b i Step : If all nodes are fixed, go to Step. Otherwise Compute and update D values for all nodes that are not connected to a i and b i and are not fixed. i = i + Go to Step Step : m Find the move sequence...m ( m i), such that = i = If G m > 0, go to Step. Otherwise, END Step : Execute m swaps, reset remaining nodes Go to Step G m g is maximized i
17 .. Kernighan-Lin (KL) Algorithm Example Cut cost: 9 Not fixed:,,,,,,,
18 .. Kernighan-Lin (KL) Algorithm Example Cut cost: 9 Not fixed:,,,,,,, Costs D(v) of each node: D() = D() = D() = D() = D() = D() = D() = D() = Nodes that lead to maximum gain
19 .. Kernighan-Lin (KL) Algorithm Example Cut cost: 9 Not fixed:,,,,,,, Costs D(v) of each node: D() = D() = D() = D() = D() = D() = D() = D() = g = +-0 = Swap (,) G = g = Nodes that lead to maximum gain Gain after node swapping Gain in the current pass 9
20 .. Kernighan-Lin (KL) Algorithm Example Cut cost: 9 Not fixed:,,,,,,, D() = D() = D() = D() = D() = D() = D() = D() = g = +-0 = Swap (,) G = g = Nodes that lead to maximum gain Gain after node swapping Gain in the current pass 0
21 .. Kernighan-Lin (KL) Algorithm Example Cut cost: 9 Not fixed:,,,,,,, Cut cost: Not fixed:,,,,, D() = D() = D() = D() = D() = D() = D() = D() = g = +-0 = Swap (,) G = g =
22 .. Kernighan-Lin (KL) Algorithm Example Cut cost: 9 Not fixed:,,,,,,, Cut cost: Not fixed:,,,,, D() = D() = D() = D() = D() = D() = D() = D() = D() = - D() = D() = - D()=- D() = D()=- g = +-0 = Swap (,) G = g =
23 .. Kernighan-Lin (KL) Algorithm Example Cut cost: 9 Not fixed:,,,,,,, Cut cost: Not fixed:,,,,, D() = D() = D() = D() = D() = D() = D() = D() = g = +-0 = Swap (,) G = g = D() = - D() = D() = - D()=- D() = D()=- g = +-0 = Swap (,) G = G + g = Nodes that lead to maximum gain Gain after node swapping Gain in the current pass
24 .. Kernighan-Lin (KL) Algorithm Example Cut cost: 9 Not fixed:,,,,,,, Cut cost: Not fixed:,,,,, Cut cost: Not fixed:,,, Cut cost: Not fixed:, D() = D() = D() = D() = D() = D() = D() = D() = D() = - D() = D() = - D()=- D() = D()=- D() = - D() = - D()=- D()=- Nodes that lead to maximum gain g = +-0 = Swap (,) G = g = g = +-0 = Swap (,) G = G + g = g = ---0 = - Swap (,) G = G + g = Gain after node swapping Gain in the current pass
25 .. Kernighan-Lin (KL) Algorithm Example Cut cost: 9 Not fixed:,,,,,,, Cut cost: Not fixed:,,,,, Cut cost: Not fixed:,,, Cut cost: Not fixed:, Cut cost: 9 Not fixed: D() = D() = D() = D() = D() = D() = D() = D() = D() = - D() = D() = - D()=- D() = D()=- D() = - D() = - D()=- D()=- D() = - D()=- g = +-0 = Swap (,) G = g = g = +-0 = Swap (,) G = G + g = g = ---0 = - Swap (,) G = G + g = g = ---0 = - Swap (,) G = G + g = 0
26 .. Kernighan-Lin (KL) Algorithm Example D() = D() = D() = D() = D() = D() = D() = D() = D() = - D() = D() = - D()=- D() = D()=- D() = - D() = - D()=- D()=- D() = - D()=- g = +-0 = Swap (,) G = g = g = +-0 = Swap (,) G = G + g = g = ---0 = - Swap (,) G = G + g = g = ---0 = - Swap (,) G = G + g = 0 Maximum positive gain G m = with m =.
27 .. Kernighan-Lin (KL) Algorithm Example D() = D() = D() = D() = D() = D() = D() = D() = D() = - D() = D() = - D()=- D() = D()=- D() = - D() = - D()=- D()=- D() = - D()=- g = +-0 = Swap (,) G = g = g = +-0 = Swap (,) G = G + g = g = ---0 = - Swap (,) G = G + g = g = ---0 = - Swap (,) G = G + g = 0 Maximum positive gain G m = with m =. Since G m > 0, the first m = swaps (,) and (,) are executed. Since G m > 0, more passes are needed until G m 0.
28 .. Extensions of the Kernighan-Lin (KL) Algorithm Unequal partition sizes Apply the KL algorithm with only min( A, B ) pairs swapped Unequal node weights Try to rescale weights to integers, e.g., as multiples of the greatest common divisor of all node weights Maintain area balance or allow a one-move deviation from balance k-way partitioning (generating k partitions) Apply the KL two-way partitioning algorithm to all possible pairs of partitions Recursive partitioning (convenient when k is a power of two) Direct k-way extensions exist
29 .. Fiduccia-Mattheyses (FM) Algorithm Single cells are moved independently instead of swapping pairs of cells --- cannot and do not need to maintain exact partition balance The area of each individual cell is taken into account Applicable to partitions of unequal size and in the presence of initially fixed cells Cut costs are extended to include hypergraphs nets with + pins While the KL algorithm aims to minimize cut costs based on edges, the FM algorithm minimizes cut costs based on nets Nodes and subgraphs are referred to as cells and blocks, respectively 9
30 .. Fiduccia-Mattheyses (FM) Algorithm Given: a hypergraph G(V,H) with nodes and weighted hyperedges partition size constraints Goal: to assign all nodes to disjoint partitions, so as to minimize the total cost (weight) of all cut nets while satisfying partition size constraints 0
31 .. Fiduccia-Mattheyses (FM) Algorithm Terminology Gain g(c) for cell c g(c) = FS(c) TE(c), a b e where the moving force FS(c) is the number of nets connected to c but not connected to any other cells within c s partition, i.e., cut nets that connect only to c, and c d the retention force TE(c) is the number of uncut nets connected to c. Cell : FS() = 0 TE() = g() = - The higher the gain g(c), the higher is the priority to move the cell c to the other partition.
32 .. Fiduccia-Mattheyses (FM) Algorithm Terminology Gain g(c) for cell c g(c) = FS(c) TE(c), a b e where the moving force FS(c) is the number of nets connected to c but not connected to any other cells within c s partition, i.e., cut nets that connect only to c, and c d the retention force TE(c) is the number of uncut nets connected to c. Cell : FS() = TE() = g() = Cell : FS() = 0 TE() = g() = - Cell : FS() = TE() = g() = 0 Cell : FS() = TE() = g() = 0 Cell : FS() = TE() = 0 g() = a b c d e
33 .. Fiduccia-Mattheyses (FM) Algorithm Terminology Maximum positive gain G m of a pass The maximum positive gain G m is the cumulative cell gain of m moves that produce a minimum cut cost. G m is determined by the maximum sum of cell gains g over a prefix of m moves in a pass m G m = g i i=
34 .. Fiduccia-Mattheyses (FM) Algorithm Terminology Ratio factor The ratio factor is the relative balance between the two partitions with respect to cell area It is used to prevent all cells from clustering into one partition. The ratio factor r is defined as r = area( A) area( A) + area( B) where area(a) and area(b) are the total respective areas of partitions A and B
35 .. Fiduccia-Mattheyses (FM) Algorithm Terminology Balance criterion The balance criterion enforces the ratio factor. To ensure feasibility, the maximum cell area area max (V) must be taken into account. A partitioning of V into two partitions A and B is said to be balanced if [ r area(v) area max (V) ] area(a) [ r area(v) + area max (V) ]
36 .. Fiduccia-Mattheyses (FM) Algorithm Terminology Base cell A base cell is a cell c that has the greatest cell gain g(c) among all free cells, and whose move does not violate the balance criterion. Base cell Cell : FS() = TE() = g() = Cell : FS() = 0 TE() = g() = - Cell : FS() = TE() = g() = 0 Cell : FS() = TE() = g() = 0
37 .. Fiduccia-Mattheyses (FM) Algorithm - One pass Step 0: Compute the balance criterion Step : Compute the cell gain g of each cell Step : i = Choose base cell c that has maximal gain g, move this cell Step : Fix the base cell c i Update all cells gains that are connected to critical nets via the base cell c i Step : If all cells are fixed, go to Step. If not: Choose next base cell c i with maximal gain g i and move this cell i = i +, go to Step Step : m Determine the best move sequence c, c,.., c m ( m i), so that = i = If G m > 0, go to Step. Otherwise, END Step : Execute m moves, reset all fixed nodes Start with a new pass, go to Step G m g is maximized i
38 .. Fiduccia-Mattheyses (FM) Algorithm Example A a b c d e B Given: Ratio factor r = 0, area(cell_) = area(cell_) = area(cell_) = area(cell_) = area(cell_) =. Step 0: Compute the balance criterion [ r area(v) area max (V) ] area(a) [ r area(v) + area max (V) ] 0, * = area(a) = 0, * +.
39 .. Fiduccia-Mattheyses (FM) Algorithm Example A B a b e c d Step : Compute the gains of each cell Cell : FS(Cell_) = TE(Cell_) = g(cell_) = Cell : FS(Cell_) = 0 TE(Cell_) = g(cell_) = - Cell : FS(Cell_) = TE(Cell_) = g(cell_) = 0 Cell : FS(Cell_) = TE(Cell_) = g(cell_) = 0 Cell : FS(Cell_) = TE(Cell_) = 0 g(cell_) = 9
40 .. Fiduccia-Mattheyses (FM) Algorithm Example A a b c d e B Cell: FS(Cell_) = TE(Cell_) = g(cell_) = Cell : FS(Cell_) = 0 TE(Cell_) = g(cell_) = - Cell : FS(Cell_) = TE(Cell_) = g(cell_) = 0 Cell : FS(Cell_) = TE(Cell_) = g(cell_) = 0 Cell : FS(Cell_) = TE(Cell_) = 0 g(cell_) = Step : Select the base cell Possible base cells are Cell and Cell Balance criterion after moving Cell : area(a) = area(cell_) = Balance criterion after moving Cell : area(a) = area(cell_) + area(cell_) + area(cell_) = Both moves respect the balance criterion, but Cell is selected, moved, and fixed as a result of the tie-breaking criterion. 0
41 .. Fiduccia-Mattheyses (FM) Algorithm Example A B a b c d e Step : Fix base cell, update g values Cell : FS(Cell_) = TE(Cell_) = 0 g(cell_) = Cell : FS(Cell_) = 0 TE(Cell_) = g(cell_) = - Cell : FS(Cell_) = 0 TE(Cell_) = g(cell_) = - Cell : FS(Cell_) = 0 TE(Cell_) = g(cell_) = - After Iteration i = : Partition A =, Partition B =,,,, with fixed cell.
42 .. Fiduccia-Mattheyses (FM) Algorithm Example A a b e B Iteration i = Cell : FS(Cell_) = TE(Cell_) = 0 g(cell_) = Cell : FS(Cell_) = 0 TE(Cell_) = g(cell_) = - Cell : FS(Cell_) = 0 TE(Cell_) = g(cell_) = - c d Cell : FS(Cell_) = 0 TE(Cell_) = g(cell_) = - Iteration i = Cell has maximum gain g =, area(a) = 0, balance criterion is violated. Cell has next maximum gain g = -, area(a) =, balance criterion is met. Cell has next maximum gain g = -, area(a) = 9, balance criterion is met. Move cell, updated partitions: A = {,}, B = {,,}, with fixed cells {,}
43 .. Fiduccia-Mattheyses (FM) Algorithm Example A Iteration i = a b c d e B Cell : g(cell_) = Cell : g(cell_) = 0 Cell : g(cell_) = - Iteration i = Cell has maximum gain g =, area(a) =, balance criterion is met. Move cell, updated partitions: A = {}, B = {,,,}, with fixed cells {,,}
44 .. Fiduccia-Mattheyses (FM) Algorithm Example B A Iteration i = a b e Cell : g(cell_) = 0 Cell : g(cell_) = - c d Iteration i = Cell has maximum gain g = 0, area(a) =, balance criterion is met. Move cell, updated partitions: A = {,}, B = {,,}, with fixed cells {,,,}
45 .. Fiduccia-Mattheyses (FM) Algorithm Example B A Iteration i = a b e Cell : g(cell_) = - c d Iteration i = Cell has maximum gain g = -, area(a) = 0, balance criterion is met. Move cell, updated partitions: A = {,,}, B = {,}, all cells {,,,,} fixed.
46 .. Fiduccia-Mattheyses (FM) Algorithm Example Step : Find best move sequence c c m G = g = G = g + g = 0 G = g + g + g = B a b e A G = g + g + g + g = G = g + g + g + g + g = 0. c d m Maximum positive cumulative gain = G m = g i = found in iterations, and. i The move prefix m = is selected due to the better balance ratio (area(a) = ); the four cells,, and are then moved. Result of Pass : Current partitions: A = {,}, B = {,,}, cut cost reduced from to.
47 Runtime difference between KL & FM Runtime of partitioning algorithms KL is sensitive to the number of nodes and edges FM is sensitive to the number of nodes and nets (hyperedges) Asymptotic complexity of partitioning algorithms KL has cubic time complexity per pass FM has linear time complexity per pass
48 Chapter Netlist and System Partitioning. Introduction. Terminology. Optimization Goals. Partitioning Algorithms.. Kernighan-Lin (KL) Algorithm.. Extensions of the Kernighan-Lin Algorithm.. Fiduccia-Mattheyses (FM) Algorithm. Framework for Multilevel Partitioning.. Clustering.. Multilevel Partitioning. System Partitioning onto Multiple FPGAs
49 .. Clustering To simplify the problem, groups of tightly-connected nodes can be clustered, absorbing connections between these nodes Size of each cluster is often limited so as to prevent degenerate clustering, i.e. a single large cluster dominates other clusters Refinement should satisfy balance criteria 9
50 .. Clustering a d d a d a,b,c b c e e b c,e Initital graph Possible clustering hierarchies of the graph 0 Springer 0
51 .. Multilevel Partitioning 0 Springer Verlag
52 . System Partitioning onto Multiple FPGAs FPGA FPGA FPGA FPGA FPGA FPGA RAM Logic Logic FPIC FPIC FPIC FPIC 0 Springer Verlag Reconfigurable system with multiple FPGA and FPIC devices Mapping of a typical system architecture onto multiple FPGAs
53 Summary of Chapter Circuit netlists can be represented by graphs Partitioning a graph means assigning nodes to disjoint partitions Total size of each partition (number/area of nodes) is limited Objective: minimize the number connections between partitions Basic partitioning algorithms Move-based, move are organized into passes KL swaps pairs of nodes from different partitions FM re-assigns one node at a time FM is faster, usually more successful Multilevel partitioning Clustering FM partitioning Refinement (also uses FM partitioning) Application: system partitioning into FPGAs Each FPGA is represented by a partition
Partitioning. Course contents: Readings. Kernighang-Lin partitioning heuristic Fiduccia-Mattheyses heuristic. Chapter 7.5.
Course contents: Partitioning Kernighang-Lin partitioning heuristic Fiduccia-Mattheyses heuristic Readings Chapter 7.5 Partitioning 1 Basic Definitions Cell: a logic block used to build larger circuits.
More informationUnit 5A: Circuit Partitioning
Course contents: Unit 5A: Circuit Partitioning Kernighang-Lin partitioning heuristic Fiduccia-Mattheyses heuristic Simulated annealing based partitioning algorithm Readings Chapter 7.5 Unit 5A 1 Course
More informationECE 5745 Complex Digital ASIC Design Topic 13: Physical Design Automation Algorithms
ECE 7 Complex Digital ASIC Design Topic : Physical Design Automation Algorithms Christopher atten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece7
More informationCAD Algorithms. Circuit Partitioning
CAD Algorithms Partitioning Mohammad Tehranipoor ECE Department 13 October 2008 1 Circuit Partitioning Partitioning: The process of decomposing a circuit/system into smaller subcircuits/subsystems, which
More informationUNIVERSITY OF CALGARY. Force-Directed Partitioning Technique for 3D IC. Aysa Fakheri Tabrizi A THESIS SUBMITTED TO THE FACULTY OF GRADUATE STUDIES
UNIVERSITY OF CALGARY Force-Directed Partitioning Technique for 3D IC by Aysa Fakheri Tabrizi A THESIS SUBMITTED TO THE FACULTY OF GRADUATE STUDIES IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE
More informationGenetic Algorithm for Circuit Partitioning
Genetic Algorithm for Circuit Partitioning ZOLTAN BARUCH, OCTAVIAN CREŢ, KALMAN PUSZTAI Computer Science Department, Technical University of Cluj-Napoca, 26, Bariţiu St., 3400 Cluj-Napoca, Romania {Zoltan.Baruch,
More informationVLSI Physical Design: From Graph Partitioning to Timing Closure
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5 Global Routing Original uthors: ndrew. Kahng, Jens, Igor L. Markov, Jin Hu VLSI Physical Design: From Graph Partitioning to Timing
More informationVLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 5 Global Routing Original uthors: ndrew. Kahng, Jens, Igor L. Markov, Jin Hu Chapter 5 Global Routing 5. Introduction 5.2 Terminology and Definitions 5.3 Optimization Goals 5. Representations of
More informationCS612 Algorithms for Electronic Design Automation. Global Routing
CS612 Algorithms for Electronic Design Automation Global Routing Mustafa Ozdal CS 612 Lecture 7 Mustafa Ozdal Computer Engineering Department, Bilkent University 1 MOST SLIDES ARE FROM THE BOOK: MODIFICATIONS
More informationCOMPARATIVE STUDY OF CIRCUIT PARTITIONING ALGORITHMS
COMPARATIVE STUDY OF CIRCUIT PARTITIONING ALGORITHMS Zoltan Baruch 1, Octavian Creţ 2, Kalman Pusztai 3 1 PhD, Lecturer, Technical University of Cluj-Napoca, Romania 2 Assistant, Technical University of
More informationChapter 5 Global Routing
Chapter 5 Global Routing 5. Introduction 5.2 Terminology and Definitions 5.3 Optimization Goals 5. Representations of Routing Regions 5.5 The Global Routing Flow 5.6 Single-Net Routing 5.6. Rectilinear
More informationCS 140: Sparse Matrix-Vector Multiplication and Graph Partitioning
CS 140: Sparse Matrix-Vector Multiplication and Graph Partitioning Parallel sparse matrix-vector product Lay out matrix and vectors by rows y(i) = sum(a(i,j)*x(j)) Only compute terms with A(i,j) 0 P0 P1
More informationGraph and Hypergraph Partitioning for Parallel Computing
Graph and Hypergraph Partitioning for Parallel Computing Edmond Chow School of Computational Science and Engineering Georgia Institute of Technology June 29, 2016 Graph and hypergraph partitioning References:
More informationA Linear-Time Heuristic for Improving Network Partitions
A Linear-Time Heuristic for Improving Network Partitions ECE 556 Project Report Josh Brauer Introduction The Fiduccia-Matteyses min-cut heuristic provides an efficient solution to the problem of separating
More informationEu = {n1, n2} n1 n2. u n3. Iu = {n4} gain(u) = 2 1 = 1 V 1 V 2. Cutset
Shantanu Dutt 1 and Wenyong Deng 2 A Probability-Based Approach to VLSI Circuit Partitioning Department of Electrical Engineering 1 of Minnesota University Minneapolis, Minnesota 55455 LSI Logic Corporation
More informationVLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 3 Chip Planning VLSI Physical Design: From Graph Partitioning to Timing Closure Original Authors: Andrew B. Kahng, Jens, Igor L. Markov, Jin Hu VLSI Physical Design: From Graph Partitioning to
More informationPreclass Warmup. ESE535: Electronic Design Automation. Motivation (1) Today. Bisection Width. Motivation (2)
ESE535: Electronic Design Automation Preclass Warmup What cut size were you able to achieve? Day 4: January 28, 25 Partitioning (Intro, KLFM) 2 Partitioning why important Today Can be used as tool at many
More informationAn Introduction to FPGA Placement. Yonghong Xu Supervisor: Dr. Khalid
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS UNIVERSITY OF WINDSOR An Introduction to FPGA Placement Yonghong Xu Supervisor: Dr. Khalid RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS UNIVERSITY OF WINDSOR
More informationMultilevel Graph Partitioning
Multilevel Graph Partitioning George Karypis and Vipin Kumar Adapted from Jmes Demmel s slide (UC-Berkely 2009) and Wasim Mohiuddin (2011) Cover image from: Wang, Wanyi, et al. "Polygonal Clustering Analysis
More informationVLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 7 Specialized Routing Original Authors: Andrew B. Kahng, Jens, Igor L. Markov, Jin Hu Chapter 7 Specialized Routing 7. Introduction to Area Routing 7. Net Ordering in Area Routing 7.3 Non-Manhattan
More informationLarge Scale Circuit Partitioning
Large Scale Circuit Partitioning With Loose/Stable Net Removal And Signal Flow Based Clustering Jason Cong Honching Li Sung-Kyu Lim Dongmin Xu UCLA VLSI CAD Lab Toshiyuki Shibuya Fujitsu Lab, LTD Support
More informationMultilevel Algorithms for Multi-Constraint Hypergraph Partitioning
Multilevel Algorithms for Multi-Constraint Hypergraph Partitioning George Karypis University of Minnesota, Department of Computer Science / Army HPC Research Center Minneapolis, MN 55455 Technical Report
More informationResearch Article Accounting for Recent Changes of Gain in Dealing with Ties in Iterative Methods for Circuit Partitioning
Discrete Dynamics in Nature and Society Volume 25, Article ID 625, 8 pages http://dxdoiorg/55/25/625 Research Article Accounting for Recent Changes of Gain in Dealing with Ties in Iterative Methods for
More informationEfficient FM Algorithm for VLSI Circuit Partitioning
Efficient FM Algorithm for VLSI Circuit Partitioning M.RAJESH #1, R.MANIKANDAN #2 #1 School Of Comuting, Sastra University, Thanjavur-613401. #2 Senior Assistant Professer, School Of Comuting, Sastra University,
More informationMulti-Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization
IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN, VOL XX, NO. XX, 2005 1 Multi-Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization Navaratnasothie Selvakkumaran and
More informationRequirements of Load Balancing Algorithm
LOAD BALANCING Programs and algorithms as graphs Geometric Partitioning Graph Partitioning Recursive Graph Bisection partitioning Recursive Spectral Bisection Multilevel Graph partitioning Hypergraph Partitioning
More informationHardware-Software Codesign
Hardware-Software Codesign 4. System Partitioning Lothar Thiele 4-1 System Design specification system synthesis estimation SW-compilation intellectual prop. code instruction set HW-synthesis intellectual
More informationThe Partitioning Problem
The Partitioning Problem 1. Iterative Improvement The partitioning problem is the problem of breaking a circuit into two subcircuits. Like many problems in VLSI design automation, we will solve this problem
More informationImplementation of Multi-Way Partitioning Algorithm
Implementation of Multi-Way Partitioning Algorithm Kulpreet S. Sikand, Sandeep S. Gill, R. Chandel, and A. Chandel Abstract This paper presents a discussion of methods to solve partitioning problems and
More informationKey terms and concepts: Divide and conquer system partitioning floorplanning chip planning placement routing global routing detailed routing
SICs...THE COURSE ( WEEK) SIC CONSTRUCTION Key terms and concepts: microelectronic system (or system on a chip) is the town and SICs (or system blocks) are the buildings System partitioning corresponds
More informationHypergraph Partitioning With Fixed Vertices
Hypergraph Partitioning With Fixed Vertices Andrew E. Caldwell, Andrew B. Kahng and Igor L. Markov UCLA Computer Science Department, Los Angeles, CA 90095-596 Abstract We empirically assess the implications
More informationIntroduction VLSI PHYSICAL DESIGN AUTOMATION
VLSI PHYSICAL DESIGN AUTOMATION PROF. INDRANIL SENGUPTA DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING Introduction Main steps in VLSI physical design 1. Partitioning and Floorplanning l 2. Placement 3.
More informationCan Recursive Bisection Alone Produce Routable Placements?
Supported by Cadence Can Recursive Bisection Alone Produce Routable Placements? Andrew E. Caldwell Andrew B. Kahng Igor L. Markov http://vlsicad.cs.ucla.edu Outline l Routability and the placement context
More informationLecture 19: Graph Partitioning
Lecture 19: Graph Partitioning David Bindel 3 Nov 2011 Logistics Please finish your project 2. Please start your project 3. Graph partitioning Given: Graph G = (V, E) Possibly weights (W V, W E ). Possibly
More informationBACKEND DESIGN. Circuit Partitioning
BACKEND DESIGN Circuit Partitioning Partitioning System Design Decomposition of a complex system into smaller subsystems. Each subsystem can be designed independently. Decomposition scheme has to minimize
More informationParallel Algorithm for Multilevel Graph Partitioning and Sparse Matrix Ordering
Parallel Algorithm for Multilevel Graph Partitioning and Sparse Matrix Ordering George Karypis and Vipin Kumar Brian Shi CSci 8314 03/09/2017 Outline Introduction Graph Partitioning Problem Multilevel
More informationPlace and Route for FPGAs
Place and Route for FPGAs 1 FPGA CAD Flow Circuit description (VHDL, schematic,...) Synthesize to logic blocks Place logic blocks in FPGA Physical design Route connections between logic blocks FPGA programming
More informationalgorithms, i.e., they attempt to construct a solution piece by piece and are not able to offer a complete solution until the end. The FM algorithm, l
The FMSAT Satisfiability Solver: Hypergraph Partitioning meets Boolean Satisfiability Arathi Ramani, Igor Markov framania, imarkovg@eecs.umich.edu February 6, 2002 Abstract This report is intended to present
More informationCircuit Placement: 2000-Caldwell,Kahng,Markov; 2002-Kennings,Markov; 2006-Kennings,Vorwerk
Circuit Placement: 2000-Caldwell,Kahng,Markov; 2002-Kennings,Markov; 2006-Kennings,Vorwerk Andrew A. Kennings, Univ. of Waterloo, Canada, http://gibbon.uwaterloo.ca/ akenning/ Igor L. Markov, Univ. of
More informationCIRCUIT PARTITIONING is a fundamental problem in
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 15, NO. 12, DECEMBER 1996 1533 Efficient Network Flow Based Min-Cut Balanced Partitioning Hannah Honghua Yang and D.
More informationL14 - Placement and Routing
L14 - Placement and Routing Ajay Joshi Massachusetts Institute of Technology RTL design flow HDL RTL Synthesis manual design Library/ module generators netlist Logic optimization a b 0 1 s d clk q netlist
More informationPenalized Graph Partitioning for Static and Dynamic Load Balancing
Penalized Graph Partitioning for Static and Dynamic Load Balancing Tim Kiefer, Dirk Habich, Wolfgang Lehner Euro-Par 06, Grenoble, France, 06-08-5 Task Allocation Challenge Application (Workload) = Set
More informationECE260B CSE241A Winter Placement
ECE260B CSE241A Winter 2005 Placement Website: / courses/ ece260b- w05 ECE260B CSE241A Placement.1 Slides courtesy of Prof. Andrew B. Slides courtesy of Prof. Andrew B. Kahng VLSI Design Flow and Physical
More informationMultilevel k-way Hypergraph Partitioning
_ Multilevel k-way Hypergraph Partitioning George Karypis and Vipin Kumar fkarypis, kumarg@cs.umn.edu Department of Computer Science & Engineering, University of Minnesota, Minneapolis, MN 55455 Abstract
More informationVLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 4 Global and Detailed Placement Original Authors: Andrew B. Kahng, Jens, Igor L. Markov, Jin Hu 1 Chapter 4 Global and Detailed Placement 4.1 Introduction 4. Optimization Objectives 4.3 Global
More informationAn Effective Algorithm for Multiway Hypergraph Partitioning
An Effective Algorithm for Multiway Hypergraph Partitioning Zhizi Zhao, Lixin Tao, Yongchang Zhao 3 Concordia University, zhao_z@cs.concordia.ca, Pace University, ltao@pace.edu, 3 retired Abstract In this
More informationGraph Partitioning for High-Performance Scientific Simulations. Advanced Topics Spring 2008 Prof. Robert van Engelen
Graph Partitioning for High-Performance Scientific Simulations Advanced Topics Spring 2008 Prof. Robert van Engelen Overview Challenges for irregular meshes Modeling mesh-based computations as graphs Static
More informationk-way Hypergraph Partitioning via n-level Recursive Bisection
k-way Hypergraph Partitioning via n-level Recursive Bisection Sebastian Schlag, Vitali Henne, Tobias Heuer, Henning Meyerhenke Peter Sanders, Christian Schulz January 10th, 2016 @ ALENEX 16 INSTITUTE OF
More informationA Network Flow Approach for Hierarchical Tree Partitioning
A Network Flow Approach for Hierarchical Tree Partitioning Ming-Ter Kuo Aptix Corporation San Jose, CA 95134 Chung-Kuan Cheng University of California, San Diego La Jolla, CA 92093 ABSTRACT Network flow
More informationReference. Wayne Wolf, FPGA-Based System Design Pearson Education, N Krishna Prakash,, Amrita School of Engineering
FPGA Fabrics Reference Wayne Wolf, FPGA-Based System Design Pearson Education, 2004 Logic Design Process Combinational logic networks Functionality. Other requirements: Size. Power. Primary inputs Performance.
More informationVLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement Techniques
VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement Techniques Shantanu Dutt and Wenyong Deng Department of Electrical Engineering, University of Minnesota, Minneapolis, MN 5555, USA
More informationGraphs and Network Flows ISE 411. Lecture 7. Dr. Ted Ralphs
Graphs and Network Flows ISE 411 Lecture 7 Dr. Ted Ralphs ISE 411 Lecture 7 1 References for Today s Lecture Required reading Chapter 20 References AMO Chapter 13 CLRS Chapter 23 ISE 411 Lecture 7 2 Minimum
More informationLecture 9: Load Balancing & Resource Allocation
Lecture 9: Load Balancing & Resource Allocation Introduction Moler s law, Sullivan s theorem give upper bounds on the speed-up that can be achieved using multiple processors. But to get these need to efficiently
More informationIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 2, FEBRUARY
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 2, FEBRUARY 2000 267 Short Papers Hypergraph Partitioning with Fixed Vertices Charles J. Alpert, Andrew E. Caldwell,
More informationAutomated system partitioning based on hypergraphs for 3D stacked integrated circuits. FOSDEM 2018 Quentin Delhaye
Automated system partitioning based on hypergraphs for 3D stacked integrated circuits FOSDEM 2018 Quentin Delhaye Integrated circuits: Let s go 3D Building an Integrated Circuit (IC) Transistors to build
More informationCprE 583 Reconfigurable Computing
CprE / ComS 583 Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #9 Logic Emulation Technology Recap FPGA-Based Router (FPX)
More informationPartitioning With Terminals: A New Problem and New Benchmarks
Partitioning With Terminals: A New Problem and New Benchmarks C. J. Alpert,A.E.Caldwell,A.B.KahngandI.L.Markov UCLA Computer Science Dept., Los Angeles, CA 90095-596 USA IBM Austin Research Laboratory,
More informationVLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement Techniques
To appear in Proc. IEEE/ACM International Conference on CAD, 996 VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement Techniques Shantanu Dutt and Wenyong Deng Department of Electrical
More informationA Divisive clustering technique for maximizing the modularity
A Divisive clustering technique for maximizing the modularity Ümit V. Çatalyürek, Kamer Kaya, Johannes Langguth, and Bora Uçar February 13, 2012 1 Introduction 2 Clustering Paradigms 3 Algorithm 4 Results
More informationPlacement Algorithm for FPGA Circuits
Placement Algorithm for FPGA Circuits ZOLTAN BARUCH, OCTAVIAN CREŢ, KALMAN PUSZTAI Computer Science Department, Technical University of Cluj-Napoca, 26, Bariţiu St., 3400 Cluj-Napoca, Romania {Zoltan.Baruch,
More informationMulti-Resource Aware Partitioning Algorithms for FPGAs with Heterogeneous Resources
Multi-Resource Aware Partitioning Algorithms for FPGAs with Heterogeneous Resources Navaratnasothie Selvakkumaran Abhishek Ranjan HierDesign Inc Salil Raje HierDesign Inc George Karypis Department of Computer
More informationLesson 2 7 Graph Partitioning
Lesson 2 7 Graph Partitioning The Graph Partitioning Problem Look at the problem from a different angle: Let s multiply a sparse matrix A by a vector X. Recall the duality between matrices and graphs:
More informationHardware/Software Codesign
Hardware/Software Codesign 3. Partitioning Marco Platzner Lothar Thiele by the authors 1 Overview A Model for System Synthesis The Partitioning Problem General Partitioning Methods HW/SW-Partitioning Methods
More informationIterative-Constructive Standard Cell Placer for High Speed and Low Power
Iterative-Constructive Standard Cell Placer for High Speed and Low Power Sungjae Kim and Eugene Shragowitz Department of Computer Science and Engineering University of Minnesota, Minneapolis, MN 55455
More informationPARALLEL PERFORMANCE DIRECTED TECHNOLOGY MAPPING FOR FPGA. Laurent Lemarchand. Informatique. ea 2215, D pt. ubo University{ bp 809
PARALLEL PERFORMANCE DIRECTED TECHNOLOGY MAPPING FOR FPGA Laurent Lemarchand Informatique ubo University{ bp 809 f-29285, Brest { France lemarch@univ-brest.fr ea 2215, D pt ABSTRACT An ecient distributed
More informationCHAPTER 1 at a glance
CHAPTER 1 at a glance Introduction to Genetic Algorithms (GAs) GA terminology Genetic operators Crossover Mutation Inversion EDA problems solved by GAs 1 Chapter 1 INTRODUCTION The Genetic Algorithm (GA)
More informationVLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter 8 Timing Closure VLSI Physical Design: From Graph Partitioning to Timing Closure Original Authors: Andrew B. Kahng, Jens, Igor L. Markov, Jin Hu VLSI Physical Design: From Graph Partitioning to
More informationA Recursive Coalescing Method for Bisecting Graphs
A Recursive Coalescing Method for Bisecting Graphs The Harvard community has made this article openly available. Please share how this access benefits you. Your story matters. Citation Accessed Citable
More informationComputer Engineering Mekelweg 4, 2628 CD Delft The Netherlands MSc THESIS. Design Partitioning for Custom Hardware Emulation
Computer Engineering Mekelweg 4, 2628 CD Delft The Netherlands http://ce.et.tudelft.nl/ 2008 MSc THESIS Design Partitioning for Custom Hardware Emulation Nikolaos Mitas Abstract Hardware verification is
More informationHypergraph-Partitioning-Based Decomposition for Parallel Sparse-Matrix Vector Multiplication
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 10, NO. 7, JULY 1999 673 Hypergraph-Partitioning-Based Decomposition for Parallel Sparse-Matrix Vector Multiplication UÈ mitv.cëatalyuè rek and
More informationParallel Multilevel Algorithms for Hypergraph Partitioning
Parallel Multilevel Algorithms for Hypergraph Partitioning Aleksandar Trifunović William J. Knottenbelt Department of Computing, Imperial College London, South Kensington Campus, London SW7 2AZ, United
More informationOn Covering a Graph Optimally with Induced Subgraphs
On Covering a Graph Optimally with Induced Subgraphs Shripad Thite April 1, 006 Abstract We consider the problem of covering a graph with a given number of induced subgraphs so that the maximum number
More informationTHE ISPD98 CIRCUIT BENCHMARK SUITE
THE ISPD98 CIRCUIT BENCHMARK SUITE Charles J. Alpert IBM Austin Research Laboratory, Austin TX 78758 alpert@austin.ibm.com Abstract From 1985-1993, the MCNC regularly introduced and maintained circuit
More informationAcyclic Multi-Way Partitioning of Boolean Networks
Acyclic Multi-Way Partitioning of Boolean Networks Jason Cong, Zheng Li, and Rajive Bagrodia Department of Computer Science University of California, Los Angeles, CA 90024 Abstract Acyclic partitioning
More informationA New K-Way Partitioning Approach. Bernhard M. Riess, Heiko A. Giselbrecht, and Bernd Wurth. Technical University of Munich, Munich, Germany
A New K-Way Partitioning Approach for Multiple Types of s Bernhard M. Riess, Heiko A. Giselbrecht, and Bernd Wurth Institute of Electronic Design Automation Technical University of Munich, 8090 Munich,
More informationMultiway Netlist Partitioning onto FPGA-based Board Architectures
Multiway Netlist Partitioning onto FPGA-based Board Architectures U. Ober, M. Glesner Institute of Microelectronic Systems, Darmstadt University of Technology, Karlstr. 15, 64283 Darmstadt, Germany Abstract
More informationOverview of Trilinos and PT-Scotch
29.03.2012 Outline PT-Scotch 1 PT-Scotch The Dual Recursive Bipartitioning Algorithm Parallel Graph Bipartitioning Methods 2 Overview of the Trilinos Packages Examples on using Trilinos PT-Scotch The Scotch
More informationCOE 561 Digital System Design & Synthesis Introduction
1 COE 561 Digital System Design & Synthesis Introduction Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Outline Course Topics Microelectronics Design
More informationLocal Search Approximation Algorithms for the Complement of the Min-k-Cut Problems
Local Search Approximation Algorithms for the Complement of the Min-k-Cut Problems Wenxing Zhu, Chuanyin Guo Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, Fuzhou
More informationImproved Algorithms for Hypergraph Bipartitioning
Improved Algorithms for Hypergraph Bipartitioning Andrew E. Caldwell, Andrew B. Kahng and Igor L. Markov* UCLA Computer Science Dept., Los Angeles, CA 90095-1596 {caldwell,abk,imarkov}@cs.ucla.edu Abstract
More informationChapter 6 Detailed Routing
hapter 6 Detailed Routing 6.1 Terminology 6.2 Horizontal and Vertical onstraint Graphs 6.2.1 Horizontal onstraint Graphs 6.2.2 Vertical onstraint Graphs 6.3 hannel Routing lgorithms 6.3.1 Left-Edge lgorithm
More informationEN2911X: Reconfigurable Computing Lecture 13: Design Flow: Physical Synthesis (5)
EN2911X: Lecture 13: Design Flow: Physical Synthesis (5) Prof. Sherief Reda Division of Engineering, rown University http://scale.engin.brown.edu Fall 09 Summary of the last few lectures System Specification
More informationMinimizing Clock Domain Crossing in Network on Chip Interconnect
Minimizing Clock Domain Crossing in Network on Chip Interconnect Parag Kulkarni 1, Puneet Gupta 2, Rudy Beraha 3 1 Synopsys 2 UCLA 3 Qualcomm Corp. R&D Outline Motivation The Router Coloring Problem Approaches
More informationEstimation of Wirelength
Placement The process of arranging the circuit components on a layout surface. Inputs: A set of fixed modules, a netlist. Goal: Find the best position for each module on the chip according to appropriate
More informationPlacement ABOUT THIS CHAPTER 11.1 INTRODUCTION CHAPTER. Chris Chu Iowa State University, Ames, Iowa
CHAPTER Placement 11 Chris Chu Iowa State University, Ames, Iowa ABOUT THIS CHAPTER Placement is the process of determining the locations of circuit devices on a die surface. It is an important stage in
More informationHypergraph-Partitioning Based Decomposition for Parallel Sparse-Matrix Vector Multiplication
Hypergraph-Partitioning Based Decomposition for Parallel Sparse-Matrix Vector Multiplication Ümit V. Çatalyürek and Cevdet Aykanat, Member, IEEE Computer Engineering Department, Bilkent University 06 Bilkent,
More informationMulti-Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization
Multi-Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization Navaratnasothie Selvakkumaran and George Karypis Department of Computer Science / Army HPC Research
More informationOptimality, Scalability and Stability Study of Partitioning and Placement Algorithms
Optimality, Scalability and Stability Study of Partitioning and Placement Algorithms Jason Cong, Michail Romesis, Min Xie Computer Science Department University of California at Los Angeles Los Angeles,
More information(Lec 14) Placement & Partitioning: Part III
Page (Lec ) Placement & Partitioning: Part III What you know That there are big placement styles: iterative, recursive, direct Placement via iterative improvement using simulated annealing Recursive-style
More informationGeneral Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs
General Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs Hongbing Fan Dept. of omputer Science University of Victoria Victoria B anada V8W P6 Jiping Liu Dept. of Math. & omp. Sci. University
More informationCHAPTER 6 DEVELOPMENT OF PARTICLE SWARM OPTIMIZATION BASED ALGORITHM FOR GRAPH PARTITIONING
CHAPTER 6 DEVELOPMENT OF PARTICLE SWARM OPTIMIZATION BASED ALGORITHM FOR GRAPH PARTITIONING 6.1 Introduction From the review, it is studied that the min cut k partitioning problem is a fundamental partitioning
More informationSilicon Virtual Prototyping: The New Cockpit for Nanometer Chip Design
Silicon Virtual Prototyping: The New Cockpit for Nanometer Chip Design Wei-Jin Dai, Dennis Huang, Chin-Chih Chang, Michel Courtoy Cadence Design Systems, Inc. Abstract A design methodology for the implementation
More informationCAD Flow for FPGAs Introduction
CAD Flow for FPGAs Introduction What is EDA? o EDA Electronic Design Automation or (CAD) o Methodologies, algorithms and tools, which assist and automatethe design, verification, and testing of electronic
More informationPhysical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006
Physical Design of Digital Integrated Circuits (EN029 S40) Sherief Reda Division of Engineering, Brown University Fall 2006 Lecture 09: Routing Introduction to Routing Global Routing Detailed Routing 2
More informationEffective Iterative Techniques for Fingerprinting Design IP
Effective Iterative Techniques for Fingerprinting Design IP Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu and Jennifer L. Wong UCLA Computer Science Dept.,
More informationMincut Placement with FM Partitioning featuring Terminal Propagation. Brett Wilson Lowe Dantzler
Mincut Placement with FM Partitioning featuring Terminal Propagation Brett Wilson Lowe Dantzler Project Overview Perform Mincut Placement using the FM Algorithm to perform partitioning. Goals: Minimize
More informationHIGH-LEVEL SYNTHESIS
HIGH-LEVEL SYNTHESIS Page 1 HIGH-LEVEL SYNTHESIS High-level synthesis: the automatic addition of structural information to a design described by an algorithm. BEHAVIORAL D. STRUCTURAL D. Systems Algorithms
More informationEE382V: System-on-a-Chip (SoC) Design
EE382V: System-on-a-Chip (SoC) Design Lecture 8 HW/SW Co-Design Sources: Prof. Margarida Jacome, UT Austin Andreas Gerstlauer Electrical and Computer Engineering University of Texas at Austin gerstl@ece.utexas.edu
More informationExact Algorithms for NP-hard problems
24 mai 2012 1 Why do we need exponential algorithms? 2 3 Why the P-border? 1 Practical reasons (Jack Edmonds, 1965) For practical purposes the difference between algebraic and exponential order is more
More information6. Tabu Search. 6.3 Minimum k-tree Problem. Fall 2010 Instructor: Dr. Masoud Yaghini
6. Tabu Search 6.3 Minimum k-tree Problem Fall 2010 Instructor: Dr. Masoud Yaghini Outline Definition Initial Solution Neighborhood Structure and Move Mechanism Tabu Structure Illustrative Tabu Structure
More information