Key terms and concepts: Divide and conquer system partitioning floorplanning chip planning placement routing global routing detailed routing

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1 SICs...THE COURSE ( WEEK) SIC CONSTRUCTION Key terms and concepts: microelectronic system (or system on a chip) is the town and SICs (or system blocks) are the buildings System partitioning corresponds to town planning. Floorplanning is the architect s job. Placement is done by the builder. Routing is done by the electrician.. Physical Design Key terms and concepts: Divide and conquer system partitioning floorplanning chip planning placement routing global routing detailed routing. CD Tools Key terms and concepts: goals and objectives for each physical design step System partitioning: Goal. Partition a system into a number of SICs. Objectives. Minimize the number of external connections between the SICs. Keep each SIC smaller than a maximum size. Floorplanning: Goal. Calculate the sizes of all the blocks and assign them locations. Objective. Keep the highly connected blocks physically close to each other. Placement: Goal. ssign the interconnect areas and the location of all the logic cells within the flexible blocks. Objectives. Minimize the SIC area and the interconnect density.

2 SECTION SIC CONSTRUCTION SICS... THE COURSE Design entry Part of an SIC design flow showing the system partitioning, floorplanning, placement, and routing steps. These steps may be performed in a slightly different order, iterated or omitted depending on the type and size of the system and its SICs. s the focus shifts from logic to interconnect, floorplanning assumes an increasingly important role. Each of the steps shown in the figure must be performed and each depends on the previous step. However, the trend is toward completing these steps in a parallel fashion and iterating, rather than in a sequential manner. Synthesis System partitioning Floorplanning Placement Routing VHDL/Verilog netlist chip block logic cells Global routing: Goal. Determine the location of all the interconnect. Objective. Minimize the total interconnect area used. Detailed routing: Goal. Completely route all the interconnect on the chip. Objective. Minimize the total interconnect length used... Methods and lgorithms Key terms and concepts: methods or algorithms are exact or heuristic (algorithm is usually reserved for a method that always gives a solution) The complexity O(f(n)) is important because n is very large algorithms may be constant, logarithmic, linear, or quadratic in time many VLSI problems are NP-complete we need metrics: a measurement function or objective function, a cost function or gain function, and possibly constraints

3 SICs... THE COURSE. System Partitioning. System Partitioning Key terms and concepts: partitioning we can t do What is the cheapest way to build my system? we can do How do I split this circuit into pieces that will fit on a chip? System partitioning for the Sun Microsystems SPRCstation SPRCstation SIC Gates /k-gate Pins Package SPRC IU (integer unit) 0 PG CIC SPRC FPU (floating-point unit) 0 PG FC Cache controller 0 PQFP G MMU (memory-management unit) 0 PQFP G Data buffer 0 PQFP G DM (direct memory access) controller 0 PQFP G Video controller/data buffer 0 PQFP G RM controller 00 PQFP G Clock generator PLCC G Type

4 SECTION SIC CONSTRUCTION SICS... THE COURSE. Estimating SIC Size System partitioning for the Sun Microsystems SPRCstation 0 SPRCstation 0 SIC Gates Pins Package Type SuperSPRC Superscalar SPRC M-transistors PG SuperCache cache controller M-transistors PG FC EMC memory control 0k-gate PG G MSI Mus Sus interface 0k-gate PG G DM Ethernet, SCSI, parallel port 0k-gate 0 PQFP SEC Sus to -bit bus 0k-gate 0 PQFP G DRI dual ISDN interface k-gate PQFP G MMCodec stereo codec k-gate PLCC FC FC G

5 SICs... THE COURSE. Estimating SIC Size Some useful numbers for SIC estimates, normalized to a µm technology Parameter Typical value Comment Scaling Lambda, λ 0. µm=0. (minimum feature size) In a µm technology, λ 0. µm. Effective gate length 0. to.0µm Less than drawn gate length, usually by about 0 percent. I/O-pad width (pitch) I/O-pad height to 0mil = to 0µm to 0mil = to 00µm For a µm technology, LM (λ=0. µm). Scales less than linearly with λ. For a µm technology, LM (λ=0.µm). Scales approximately linearly with λ. Large die 000 mil/side, 0 mil pproximately constant Small die 00 mil/side, 0 mil pproximately constant Standard-cell density. 0 gate/µm =.0gate/mil Standard-cell density 0 gate/µm =.0gate/mil For µm, LM, library = 0 gate/λ (independent of scaling). For 0. µm, LM, library = 0 gate/λ (independent of scaling). Gate-array utilization 0 to 0% For LM, approximately constant Gate-array density Standard-cell routing factor=(cell area+route area)/cell area Package cost 0 to 0% For LM, approximately constant (0. to 0.) standard cell density. to. (LM).0 to.0 (LM) $0.0/pin, penny per pin Wafer cost $k to $k average $k For the same process as standard cells pproximately constant Varies widely, figure is for low-cost plastic package, approximately constant Varies widely, figure is for a mature, LM CMOS process, approximately constant N λ λ λ /λ /λ

6 SECTION SIC CONSTRUCTION SICS... THE COURSE (a) (b) RM area/λ 0 multiplier area/λ word length/bits word depth/bits multiplier size = m n /bits Estmating circuit size (a) SIC memory size. These figures are for static RM constructed using compilers in a LM SIC process, but with no special memory design rules. The actual area of a RM will depend on the speed and number of read write ports. (b) Multiplier size for a LM process. The actual area will depend on the multiplier architecture and speed.. Power Dissipation Key terms and concepts: dynamic (switching current and short-circuit current ) and static (leakage current and subthreshold current) power dissipation.. Switching Current Key terms and concepts: I = C(dV/dt) power dissipation = 0. CV DD = IV = CV(dV/dt) for onehalf the period of the input, t=/( f) total power = P = fcv DD estimate power by counting nodes that toggle.. Short-Circuit Current Key terms and concepts: P = (/)β f t rf (V DD V tn ) short-circuit current is typically less than 0 percent of the switching current

7 SICs... THE COURSE. FPG Partitioning.. Subthreshold and Leakage Current Key terms and concepts: subthreshold current is normally less than pµm of gate width subthreshold current for 0 million transistors (each 0µm wide) is 0.m subthreshold current does not scale it takes about 0mV to reduce subthreshold current by a factor of 0 if V t = 0.V, at V GS =0 V we can only reduce I DS to 0.00 times its value at V GS =V t leakage current field transistors quiescent leakage current, I DDQ IDDQ test. FPG Partitioning.. TM Simulator Partitioning of the TM board using Lattice Logic isplsi 0 FPGs. Each FPG contains generic logic blocks (GLs) Chip # Size Chip # Size GLs GLs k-bit SRM GLs GLs k-bit SRM GLs 0 GLs GLs 0 GLs k-bit SRM 0 GLs.. utomatic Partitioning with FPGs Key terms and concepts: In ltera HDL you can direct the partitioner to automatically partition logic into chips within the same family, using the UTO keyword: DEVICE top_level IS UTO; % let the partitioner assign logic

8 SECTION SIC CONSTRUCTION SICS... THE COURSE byte number... bit number GFC/VPI VPI VPI VCI VCI PTI CLP HEC payload payload GFC = generic flow control VPI = virtual path identifier VCI = virtual channel identifier PTI = payload type identifier CLP = cell loss priority HEC = header error control The asynchronous transfer mode (TM) cell format. The TM protocol uses -byte cells or packets of information with a data payload and header information for routing and error control.

9 SICs... THE COURSE. FPG Partitioning

10 0 SECTION SIC CONSTRUCTION SICS... THE COURSE. Partitioning Methods Key terms and concepts: Examples of goals: maximum size for each SIC maximum number of SICs maximum number of connections for each SIC maximum number of total connections between all SICs.. Measuring Connectivity Key terms and concepts: a network has circuit modules (logic cells) and terminals (connectors or pins) modelled by a graph with vertexes (logic cells) connected by edges (electrical connections, nets or signals) cutset net cutset edge cutset (for the graph) external connections internal connections net cuts edge cuts.. Simple Partitioning Example Key terms and concepts: two types of network partitioning: constructive partitioning and iterative partitioning improvement.. Constructive Partitioning Key terms and concepts: seed growth or cluster growth uses a seed cell and forms clusters or cliques a useful starting point.. Iterative Partitioning Improvement Key terms and concepts: interchange (swap two) and group (swap many) migration greedy algorithms find a local minimum group migration algorithms such as the Kernighan Lin algorithm (basis of min-cut methods) can do better.. The Kernighan Lin lgorithm Key terms and concepts: a cost matrix plus connectivity matrix models system measure is the cut cost, or cut weight careful to distinguish external edge cost and internal edge cost net-cut partitioning and edge-cut partitioning hypergraphs with stars, and hyperedges model connections better than edges the Fiduccia Mattheyses algorithm uses linked lists to reduce O( K L algorithm) and is very widely used base logic cell balance critical net.. The Ratio-Cut lgorithm Key terms and concepts: ratio-cut algorithm ratio set cardinality ratio cut

11 SICs... THE COURSE. Partitioning Methods net, signal, or wire D E terminal, or pin network C F edge module, cell, or block D E graph C F vertex, node, or point net cut (a) (b) logic module D G E H (c) C F net cutset=two nets I Only one wire is needed to connect several modules on the same net. three-terminal net requires three edges. edge cut D G E H (d) F C I single wire is modeled by multiple edges in the network graph. edge cutset=four edges Networks, graphs, and partitioning. (a) network containing circuit logic cells and nets. (b) The equivalent graph with vertexes and edges. For example: logic cell D maps to node D in the graph; net maps to the edge (, ) in the graph. Net (with three connections) maps to three edges in the graph: (, C), (, F), and (C, F). (c) Partitioning a network and its graph. network with a net cut that cuts two nets. (d) The network graph showing the corresponding edge cut. The net cutset in c contains two nets, but the corresponding edge cutset in d contains four edges. This means a graph is not an exact model of a network for partitioning purposes... The Look-ahead lgorithm Key terms and concepts: gain vector look-ahead algorithm

12 SECTION SIC CONSTRUCTION SICS... THE COURSE (a) (b) C 0 D 0 E F G H 0 D F E C L H I J G K I J K L SIC SIC SIC Partitioning example. (a) We wish to partition this network into three SICs with no more than four logic cells per SIC. (c) (b) partitioning with five external connections (nets,,,, and ) the minimum number. (c) constructed partition using logic cell C as a seed. It is difficult to get from this local minimum, with seven external connections (,,,,,,), to the optimum solution of b. F D H K I J G L C E

13 SICs... THE COURSE. Partitioning Methods x w z y One wire corresponds to one hyperedge in a hypergraph. x w z y hyperedge star C D C D (a) (b) hypergraph. (a) The network contains a net y with three terminals. (b) In the network hypergraph we can model net y by a single hyperedge (, C, D) and a star node. Now there is a direct correspondence between wires or nets in the network and hyperedges in the graph.

14 SECTION SIC CONSTRUCTION SICS... THE COURSE swap nodes and 0 0 edges cut= edges cut= (a) Gain from swapping i th pair of nodes, g i + after swapping nodes and, gain, g = = + 0 original configuration (b) i, number of pairs of nodes pretend swapped Total gain from swapping the first n pairs of nodes, G n G = g 0 + g + max (G n ) + 0 (c) n, number of pairs of nodes actually swapped Partitioning a graph using the Kernighan Lin algorithm. (a) Shows how swapping node of partition with node of partition results in a gain of g=. (b) graph of the gain resulting from swapping pairs of nodes. (c) The total gain is equal to the sum of the gains obtained at each step.

15 SICs... THE COURSE. Partitioning Methods C internal edge external edge 0 C= connectivity matrix (a) (b) Terms used by the Kernighan Lin partitioning algorithm. (a) n example network graph. (b) The connectivity matrix, C; the column and rows are labeled to help you see how the matrix entries correspond to the node numbers in the graph. For example, C (column, row ) equals because nodes and are connected. In this example all edges have an equal weight of, but in general the edges may have different weights.

16 SECTION SIC CONSTRUCTION SICS... THE COURSE gain=+ 0 0 (a) gain=+ gain=+ (d) (b) 0 gain=+ (e) 0 (c) 0 0 (f) n example of network partitioning that shows the need to look ahead when selecting logic cells to be moved between partitions. Partitionings (a), (b), and (c) show one sequence of moves, partitionings (d), (e), and (f) show a second sequence. The partitioning in (a) can be improved by moving node from to with a gain of. The result of this move is shown in (b). This partitioning can be improved by moving node to, again with a gain of. The partitioning shown in (d) is the same as (a). We can move node to with a gain of as shown in (e), but now we can move node to with a gain of.

17 SICs... THE COURSE. Summary.. Simulated nnealing Key terms and concepts: simulated-annealing algorithm uses an energy function as a measure probability of accepting a move is exp( E/T) E is an increase in energy function T corresponds to temperature we hill climb to get out of a local minimum cooling schedule T i+ = αt i good results at the expense of long run times Xilinx used simulated annealing in one verion of their tools.. Other Partitioning Objectives Key terms and concepts: timing, power, technology, cost and test constraints many of these are hard to measure and not well handled by current tools. Summary Key terms and concepts: The construction or physical design of a microelectronics system is a very large and complex problem. To solve the problem we divide it into several steps: system partitioning, floorplanning, placement, and routing. To solve each of these smaller problems we need goals and objectives, measurement metrics, as well as algorithms and methods The goals and objectives of partitioning Partitioning as an art not a science The simple nature of the algorithms necessary for VLSI-sized problems The random nature of the algorithms we use The controls for the algorithms used in SIC design

18 SECTION SIC CONSTRUCTION SICS... THE COURSE