HIGH-LEVEL SYNTHESIS
|
|
- Percival Sherman
- 6 years ago
- Views:
Transcription
1 HIGH-LEVEL SYNTHESIS Page 1 HIGH-LEVEL SYNTHESIS High-level synthesis: the automatic addition of structural information to a design described by an algorithm. BEHAVIORAL D. STRUCTURAL D. Systems Algorithms Processors Register transfers ALU s, RAM, etc. Logic Gates, flip-flops, etc. Transfer Transistors functions PHYSICAL D. Transistor layout Cell layout Module layout Floor plans Physical partitions High-level synthesis visualized on Gajski s Y- chart
2 HIGH-LEVEL SYNTHESIS Page 2 HARDWARE MODELS FOR HIGH-LEVEL SYNTHESIS All HLS systems need to restrict the target hardware. The search space is too large, otherwise. All synthesis systems have their own peculiarities; but most systems generate synchronous hardware and build it with the following parts: * functional units: they can perform one or more computations, e.g. addition, multiplication, comparison, ALU. i 1 i 2 f o f (i 1, i 2 )
3 HIGH-LEVEL SYNTHESIS Page 3 HARDWARE MODELS (Continued) * registers: they store inputs, intermediate results and outputs; sometimes several registers are taken together to form a register file. * multiplexers: from several inputs, one is passed to the output. i 0 i 1 i 2 i 3 c 1 c 0 o i k, k 2c 1 c 0
4 HIGH-LEVEL SYNTHESIS Page 4 HARDWARE MODELS (Continued) * busses: a connection shared between several hardware elements, such that only one element can write data at a specific time. * three-state (tri-state) drivers control the exclusive writing on the bus. i enable o
5 HIGH-LEVEL SYNTHESIS Page 5 HARDWARE MODELS (Continued) Parameters defining the hardware model for the synthesis problem: * clocking strategy: e.g. one- or two-phase clocks. * interconnect: e.g. allowing or disallowing buses. * clocking of functional units: allowing or disallowing of: + multicycle operations; + chaninig; + pipelined units.
6 HIGH-LEVEL SYNTHESIS Page 6 HARDWARE CONCEPTS: DATA PATH + CONTROL Hardware is normally partitioned into two parts: * the data path: a network of functional units, registers, multiplexers and buses. The actual computation takes place in the data path. * control: the part of the hardware that takes care of having the data present at the right place at a specific time, of presenting the right instructions to a programmable unit, etc. Often high-level synthesis concentrates on datapath synthesis. The control part is then realized as a finite state machine or in microcode.
7 HIGH-LEVEL SYNTHESIS Page 7 INPUT FORMAT The algorithm, that is the input for a high-level synthesis system, is often provided in textual form either: * in a conventional programming language, such as Pascal, or * in a hardware description language, which is more suitable to express the parallelism present in hardware. The description has to be parsed and transformed into an internal representation; here conventional compiler techniques can be used.
8 HIGH-LEVEL SYNTHESIS Page 8 INTERNAL REPRESENTATION Most systems use some form of a data-flow graph. A DFG may or may not contain information on control flow. A data-flow graph is built from: * vertices (nodes): representing computation, and * edges: representing precedence relations.
9 HIGH-LEVEL SYNTHESIS Page 9 DATA FLOW x := a * b; y := c + d; z := x + y; a b c d x y z
10 HIGH-LEVEL SYNTHESIS Page 10 TOKEN FLOW IN A DFG * A node in a DFG fires when tokens are present at its inputs. * The input tokens are consumed and an output token is produced. a b c d a b c d x y x y z a b c d z a b c d x y x y z z
11 HIGH-LEVEL SYNTHESIS Page 11 CONDITIONAL DATA FLOW By means of two special nodes: * selector T selector F * distributor distributor T F
12 HIGH-LEVEL SYNTHESIS Page 12 EXPLICIT ITERATIVE DATA FLOW Selector and distributor nodes can be used to describe iteration. a b T sel. F T distr. F a while a > b do a := a b;
13 HIGH-LEVEL SYNTHESIS Page 13 Loops require careful placement of initial tokens on edges.
14 HIGH-LEVEL SYNTHESIS Page 14 IMPLICIT ITERATIVE DATA FLOW * Iteration implied by stream of input tokens arriving at regular points in time. * Initial tokens act as buffers. a b a b a b a[0] a[1] a[0] b[1] a[1] c[1] c c c * Delay elements instead of initial tokens. a b T 0 c
15 HIGH-LEVEL SYNTHESIS Page 15 ITERATIVE DFG EXAMPLE + m 1 d 1 m 2 c 8 o 1 T 0 + c 2 c 4 c 6 + c 7 m 3 m 4 T 0 d 2 i 1 + c 1 c 3 c 5 A second-order filter section.
16 HIGH-LEVEL SYNTHESIS Page 16 HIGH-LEVEL TRANSFORMATIONS Restructuring data and control flow graphs prior to the actual mapping onto hardware. Examples: * Replacing division by 2 by shift. * Loop unrolling. * Replacing chain of adders by a tree. x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 y x 1 x 2 x 3 x 4 x 5 x 6 x 7 x y
17 HIGH-LEVEL SYNTHESIS Page 17 TERMINOLOGY Subtasks in high-level synthesis: * Scheduling: determine for each operation the time at which it should be performed such that no precedence constraint is violated. For an edge (v i, v j ): t j t i i * Allocation: specify the hardware resources that will be necessary. * Assignment: provide a mapping from each operation to a specific functional unit and from each variable to a register. Remarks: * The subproblems are strongly interrelated; they are, however, often solved separately. * Scheduling (except for a few versions) is NPcomplete heuristics have to be used.
18 HIGH-LEVEL SYNTHESIS Page 18 EXAMPLE The second-order filter section made acyclic: + o 2 (d 1 ) c 8 o 1 m 1 m 2 + c 2 c 4 i 2 (d 1 ) c 6 + c 7 m 3 o 3 (d 2 ) m 4 i 1 + c 1 c 3 i 3 (d 2 ) c 5 The schedule and operation assignment with an allocation of one adder and one multiplier: c 3 c 4 c 5 c 6 + c 1 c 2 c 7 c
19 HIGH-LEVEL SYNTHESIS Page 19 EXAMPLE (Continued) The resulting data path after register assignment: ROM d 1 i d 1 r 1 r 2 r 3 r o 1
20 HIGH-LEVEL SYNTHESIS Page 20 OPTIMIZATION CRITERIA Not surprisingly, the objective function to be optimized is similar to the one for the design of VLSI circuits in general. It is a combination of: * speed: how long does it take to perform the intended computation, * area: the addition of the areas of all functional units and registers, sometimes taking the area of interconnection into account. Often optimization is constrained: * Optimize area when the minimum speed is given time-constrained synthesis. * Optimize speed when maximum area is given area-constrained synthesis. * Optimize speed when a maximum for each resource type is given resource-constrained synthesis.
21 HIGH-LEVEL SYNTHESIS Page 21 SCHEDULING METHODS * As soon as possible (ASAP): + an operation can be scheduled when all its predecessors have been scheduled. + very simple, as data-flow graph need only to be traversed from inputs(s) to output(s). * As late as possible (ALAP): + similar to ASAP, but scheduling is now performed from output(s) to input(s). * List scheduling: + similar to ASAP; however, now an extra criterion is used for choosing between all operations that have all their predecessors scheduled.
22 HIGH-LEVEL SYNTHESIS Page 22 SCHEDULING METHODS (Continued) * Critical-path list scheduling: + sorting criterion is the length of the longest path from operation to output. + gives good results in practice! * Freedom-based scheduling: + compute both ASAP and ALAP schedules (longest-path computations from inputs to operation and from operation to outputs). + the difference in scheduling position gives the freedom or mobility of an operation (operations in the critical path have mobility zero). + take advantage of mobility to find a good position within scheduling range.
23 HIGH-LEVEL SYNTHESIS Page 23 FORCE-DIRECTED SCHEDULING * extension of freedom-based methods. * computes so-called distribution graph to model the global effects on hardware resources. a 1 + a 2 + a 1 a 2 + a 3 a 3 * a partial schedule ^, is a schedule where some transfers have a fixed time positions and others have a scheduling range. * the resource utilization for resource r of a partial schedule ^ at time t is given by the distribution function ^r(^, t).
24 HIGH-LEVEL SYNTHESIS Page 24 FORCE-DIRECTED SCHEDULING (Ctd.) * When fixing an operation s time, one makes a transition from partial schedule ^ to partial schedule ^. * For every operation a force F r (^, ^), is computed for every possible position within an operation s range. * Basic force function: F r (^, ^) trange(op) ^ r(^, t)(^ r(^, t) ^r(^, t)) * The lowest force determines which operation is scheduled and at which position.
25 HIGH-LEVEL SYNTHESIS Page 25 THE ASSIGNMENT PROBLEM Subtasks in assignment: * operation-to-fu assignment * value grouping * value-to-register assignment * transfer-to-wire assignment * wire to FU-port assignment In general: task-to-agent assignment Assumption: assignment follows scheduling. * Then the claim of a task on an agent is an interval minimum resource utilization can be found by left-edge algorithm. * In case of iterative algorithm, interval graph becomes circular-arc graph optimization is NP-complete.
26 HIGH-LEVEL SYNTHESIS Page 26 ASSIGNMENT BY CLIQUE PARTITIONING * Tasks are compatible when they can be executed on the same agent simultaneously compatiblity graph. * A clique is a maximal complete subgraph. * Clique partitioning divides the vertices of a graph into complete subgraphs. v 1 v 1 v 0 v 4 v 5 v 0 v 4 v 5 C 3 C 1 C 4 v 2 v 7 C 0 v 7 v 2 v 3 v 6 v3 C 2 v 6 (a) (b) A graph and its cliques
27 HIGH-LEVEL SYNTHESIS Page 27 TSENG AND SIEWOREK S CLIQUE-PARTITIONING ALGORITHM k := 0; G k c (V c k ;Ek c ) := G c(v c ;E c ); while Ec k 6= ; do begin end \nd v i ;v j with largest set of common neighbors"; N := \set of common neighbors of v i and v j "; s := i [ j; V k+1 c := V k c [fv sgnfv i ;v j g; Ec k+1 := ;; for each (v m ;v n ) 2 Ec k do if v m 6= v i ^ v m 6= v j ^ v n 6= v i ^ v n 6= v j then Ec k+1 := Ec k+1 [f(v m ;v n )g; for each v n 2 N do Ec k+1 := Ec k+1 [f(v n ;v s )g; k := k +1
28 HIGH-LEVEL SYNTHESIS Page 28 CLIQUE-PARTITIONING EXAMPLE v 1 v 0,1 v 0 v 4 v 5 v 4 v 5 v 2 v 7 v 2 v 7 v 3 v 6 v 3 v 6 (a) (b) v 0,1,2 v 0,1,2 v 4 v 5 v 4 v 5,6 v 7 v 7 v 3 v 6 v 3 (c) (d) v 0,1,2,3 v 0,1,2,3 v 4 v 5,6 v 4 v 5,6,7 v 7 (e) (f)
29 HIGH-LEVEL SYNTHESIS Page 29 HIGH-LEVEL TRANSFORMATIONS Restructuring data and control flow graphs prior to the actual mapping onto hardware. Examples: * Replacing division by 2 by shift. * Loop unrolling. * Replacing chain of adders by a tree. x 1 x 2 x 3 x 4 x 5 x 6 x 7 x y x 1 x 2 x 3 x 4 x 5 x 6 x 7 x y
High-Level Synthesis (HLS)
Course contents Unit 11: High-Level Synthesis Hardware modeling Data flow Scheduling/allocation/assignment Reading Chapter 11 Unit 11 1 High-Level Synthesis (HLS) Hardware-description language (HDL) synthesis
More informationUnit 2: High-Level Synthesis
Course contents Unit 2: High-Level Synthesis Hardware modeling Data flow Scheduling/allocation/assignment Reading Chapter 11 Unit 2 1 High-Level Synthesis (HLS) Hardware-description language (HDL) synthesis
More informationIntroduction to Electronic Design Automation. Model of Computation. Model of Computation. Model of Computation
Introduction to Electronic Design Automation Model of Computation Jie-Hong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Spring 03 Model of Computation In system design,
More informationHigh-Level Synthesis
High-Level Synthesis 1 High-Level Synthesis 1. Basic definition 2. A typical HLS process 3. Scheduling techniques 4. Allocation and binding techniques 5. Advanced issues High-Level Synthesis 2 Introduction
More informationCOE 561 Digital System Design & Synthesis Introduction
1 COE 561 Digital System Design & Synthesis Introduction Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Outline Course Topics Microelectronics Design
More informationHardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University
Hardware Design Environments Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Outline Welcome to COE 405 Digital System Design Design Domains and Levels of Abstractions Synthesis
More informationHigh Level Synthesis
High Level Synthesis Design Representation Intermediate representation essential for efficient processing. Input HDL behavioral descriptions translated into some canonical intermediate representation.
More informationSynthesis at different abstraction levels
Synthesis at different abstraction levels System Level Synthesis Clustering. Communication synthesis. High-Level Synthesis Resource or time constrained scheduling Resource allocation. Binding Register-Transfer
More informationDatapath Allocation. Zoltan Baruch. Computer Science Department, Technical University of Cluj-Napoca
Datapath Allocation Zoltan Baruch Computer Science Department, Technical University of Cluj-Napoca e-mail: baruch@utcluj.ro Abstract. The datapath allocation is one of the basic operations executed in
More informationTopics. Verilog. Verilog vs. VHDL (2) Verilog vs. VHDL (1)
Topics Verilog Hardware modeling and simulation Event-driven simulation Basics of register-transfer design: data paths and controllers; ASM charts. High-level synthesis Initially a proprietary language,
More informationLecture 20: High-level Synthesis (1)
Lecture 20: High-level Synthesis (1) Slides courtesy of Deming Chen Some slides are from Prof. S. Levitan of U. of Pittsburgh Outline High-level synthesis introduction High-level synthesis operations Scheduling
More information4DM4 Lab. #1 A: Introduction to VHDL and FPGAs B: An Unbuffered Crossbar Switch (posted Thursday, Sept 19, 2013)
1 4DM4 Lab. #1 A: Introduction to VHDL and FPGAs B: An Unbuffered Crossbar Switch (posted Thursday, Sept 19, 2013) Lab #1: ITB Room 157, Thurs. and Fridays, 2:30-5:20, EOW Demos to TA: Thurs, Fri, Sept.
More informationECE 587 Hardware/Software Co-Design Lecture 23 Hardware Synthesis III
ECE 587 Hardware/Software Co-Design Spring 2018 1/28 ECE 587 Hardware/Software Co-Design Lecture 23 Hardware Synthesis III Professor Jia Wang Department of Electrical and Computer Engineering Illinois
More informationCPE 426/526 Chapter 12 - Synthesis Algorithms for Design Automation (Supplement) Dr. Rhonda Kay Gaede UAH
CPE 426/526 Chapter 12 - Synthesis Algorithms for Design Automation (Supplement) Dr. Rhonda Kay Gaede UAH 1 12.4.5 Analysis of the Allocation Problem - Terminology Allocation is needed for,, and Two items
More informationHigh-Level Synthesis Creating Custom Circuits from High-Level Code
High-Level Synthesis Creating Custom Circuits from High-Level Code Hao Zheng Comp Sci & Eng University of South Florida Exis%ng Design Flow Register-transfer (RT) synthesis - Specify RT structure (muxes,
More informationCOMPUTER ARCHITECTURE AND ORGANIZATION Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital
Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital hardware modules that accomplish a specific information-processing task. Digital systems vary in
More informationOverview. CSE372 Digital Systems Organization and Design Lab. Hardware CAD. Two Types of Chips
Overview CSE372 Digital Systems Organization and Design Lab Prof. Milo Martin Unit 5: Hardware Synthesis CAD (Computer Aided Design) Use computers to design computers Virtuous cycle Architectural-level,
More informationDigital Design with FPGAs. By Neeraj Kulkarni
Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic
More informationSystem Level Design For Low Power. Yard. Doç. Dr. Berna Örs Yalçın
System Level Design For Low Power Yard. Doç. Dr. Berna Örs Yalçın References System-Level Design Methodology, Daniel D. Gajski Hardware-software co-design of embedded systems : the POLIS approach / by
More informationEE382M.20: System-on-Chip (SoC) Design
EE82M.20: SystemonChip (SoC) Design Lecture 1 Resource Allocation and Binding Source: G. De Micheli, Integrated Systems Center, EPFL Synthesis and Optimization of Digital Circuits, McGraw Hill, 2001. Andreas
More informationLecture Compiler Backend
Lecture 19-23 Compiler Backend Jianwen Zhu Electrical and Computer Engineering University of Toronto Jianwen Zhu 2009 - P. 1 Backend Tasks Instruction selection Map virtual instructions To machine instructions
More informationBased on slides/material by. Topic Design Methodologies and Tools. Outline. Digital IC Implementation Approaches
Based on slides/material by Topic 11 Peter Y. K. Cheung Department of Electrical & Electronic Engineering Imperial College London K. Masselos http://cas.ee.ic.ac.uk/~kostas J. Rabaey http://bwrc.eecs.berkeley.edu/classes/icbook/instructors.html
More informationCS250 VLSI Systems Design Lecture 9: Patterns for Processing Units and Communication Links
CS250 VLSI Systems Design Lecture 9: Patterns for Processing Units and Communication Links John Wawrzynek, Krste Asanovic, with John Lazzaro and Yunsup Lee (TA) UC Berkeley Fall 2010 Unit-Transaction Level
More informationECE 669 Parallel Computer Architecture
ECE 669 Parallel Computer Architecture Lecture 23 Parallel Compilation Parallel Compilation Two approaches to compilation Parallelize a program manually Sequential code converted to parallel code Develop
More informationComputer Architecture
Computer Architecture Lecture 1: Digital logic circuits The digital computer is a digital system that performs various computational tasks. Digital computers use the binary number system, which has two
More informationCS250 VLSI Systems Design Lecture 8: Introduction to Hardware Design Patterns
CS250 VLSI Systems Design Lecture 8: Introduction to Hardware Design Patterns John Wawrzynek, Jonathan Bachrach, with Krste Asanovic, John Lazzaro and Rimas Avizienis (TA) UC Berkeley Fall 2012 Lecture
More informationVHDL simulation and synthesis
VHDL simulation and synthesis How we treat VHDL in this course You will not become an expert in VHDL after taking this course The goal is that you should learn how VHDL can be used for simulation and synthesis
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
More informationWriting Circuit Descriptions 8
8 Writing Circuit Descriptions 8 You can write many logically equivalent descriptions in Verilog to describe a circuit design. However, some descriptions are more efficient than others in terms of the
More information: : (91-44) (Office) (91-44) (Residence)
Course: VLSI Circuits (Video Course) Faculty Coordinator(s) : Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology Madras Chennai 600036 Email Telephone : srinis@iitm.ac.in,
More informationECE 5775 (Fall 17) High-Level Digital Design Automation. More Binding Pipelining
ECE 5775 (Fall 17) High-Level Digital Design Automation More Binding Pipelining Logistics Lab 3 due Friday 10/6 No late penalty for this assignment (up to 3 days late) HW 2 will be posted tomorrow 1 Agenda
More informationVerilog for High Performance
Verilog for High Performance Course Description This course provides all necessary theoretical and practical know-how to write synthesizable HDL code through Verilog standard language. The course goes
More informationFPGA: What? Why? Marco D. Santambrogio
FPGA: What? Why? Marco D. Santambrogio marco.santambrogio@polimi.it 2 Reconfigurable Hardware Reconfigurable computing is intended to fill the gap between hardware and software, achieving potentially much
More informationCHAPTER - 2 : DESIGN OF ARITHMETIC CIRCUITS
Contents i SYLLABUS osmania university UNIT - I CHAPTER - 1 : BASIC VERILOG HDL Introduction to HDLs, Overview of Digital Design With Verilog HDL, Basic Concepts, Data Types, System Tasks and Compiler
More informationCopyright 2007 Society of Photo-Optical Instrumentation Engineers. This paper was published in Proceedings of SPIE (Proc. SPIE Vol.
Copyright 2007 Society of Photo-Optical Instrumentation Engineers. This paper was published in Proceedings of SPIE (Proc. SPIE Vol. 6937, 69370N, DOI: http://dx.doi.org/10.1117/12.784572 ) and is made
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
More informationThe Need of Datapath or Register Transfer Logic. Number 1 Number 2 Number 3 Number 4. Numbers from 1 to million. Register
The Need of Datapath or Register Transfer Logic Number 1 Number 2 Number 3 Number 4 Numbers from 1 to million Register (a) (b) Circuits to add several numbers: (a) combinational circuit to add four numbers;
More informationOverview. Design flow. Principles of logic synthesis. Logic Synthesis with the common tools. Conclusions
Logic Synthesis Overview Design flow Principles of logic synthesis Logic Synthesis with the common tools Conclusions 2 System Design Flow Electronic System Level (ESL) flow System C TLM, Verification,
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware 4.1 Introduction We will examine two MIPS implementations
More informationLecture 8: Synthesis, Implementation Constraints and High-Level Planning
Lecture 8: Synthesis, Implementation Constraints and High-Level Planning MAH, AEN EE271 Lecture 8 1 Overview Reading Synopsys Verilog Guide WE 6.3.5-6.3.6 (gate array, standard cells) Introduction We have
More informationEvolution of Implementation Technologies. ECE 4211/5211 Rapid Prototyping with FPGAs. Gate Array Technology (IBM s) Programmable Logic
ECE 42/52 Rapid Prototyping with FPGAs Dr. Charlie Wang Department of Electrical and Computer Engineering University of Colorado at Colorado Springs Evolution of Implementation Technologies Discrete devices:
More informationCOSC 243. Computer Architecture 1. COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 1
COSC 243 Computer Architecture 1 COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 1 Overview Last Lecture Flip flops This Lecture Computers Next Lecture Instruction sets and addressing
More informationEE 3170 Microcontroller Applications
EE 3170 Microcontroller Applications Lecture 4 : Processors, Computers, and Controllers - 1.2 (reading assignment), 1.3-1.5 Based on slides for ECE3170 by Profs. Kieckhafer, Davis, Tan, and Cischke Outline
More informationTechnology Dependent Logic Optimization Prof. Kurt Keutzer EECS University of California Berkeley, CA Thanks to S. Devadas
Technology Dependent Logic Optimization Prof. Kurt Keutzer EECS University of California Berkeley, CA Thanks to S. Devadas 1 RTL Design Flow HDL RTL Synthesis Manual Design Module Generators Library netlist
More informationESE534: Computer Organization. Tabula. Previously. Today. How often is reuse of the same operation applicable?
ESE534: Computer Organization Day 22: April 9, 2012 Time Multiplexing Tabula March 1, 2010 Announced new architecture We would say w=1, c=8 arch. 1 [src: www.tabula.com] 2 Previously Today Saw how to pipeline
More informationBEHAVIORAL SYNTHESIS: AN OVERVIEW
CHAPTER 6 BEHAVIORAL SYNTHESIS: AN OVERVIEW REINALDO A. BERGAMASCHI IBM Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, USA., Tel: 1 914 945 3903, Fax: 1 914 945 4469, e-mail:
More informationPrevious Exam Questions System-on-a-Chip (SoC) Design
This image cannot currently be displayed. EE382V Problem: System Analysis (20 Points) This is a simple single microprocessor core platform with a video coprocessor, which is configured to process 32 bytes
More informationSequential Circuits. inputs Comb FFs. Outputs. Comb CLK. Sequential logic examples. ! Another way to understand setup/hold/propagation time
Sequential Circuits! Another way to understand setup/hold/propagation time inputs Comb FFs Comb Outputs CLK CSE 37 Spring 2 - Sequential Logic - Sequential logic examples! Finite state machine concept
More informationCS294-48: Hardware Design Patterns Berkeley Hardware Pattern Language Version 0.5. Krste Asanovic UC Berkeley Fall 2009
CS294-48: Hardware Design Patterns Berkeley Hardware Pattern Language Version 0.5 Krste Asanovic UC Berkeley Fall 2009 Overall Problem Statement MP3 bit string Audio Application(s) (Berkeley) Hardware
More informationAbstract A SCALABLE, PARALLEL, AND RECONFIGURABLE DATAPATH ARCHITECTURE
A SCALABLE, PARALLEL, AND RECONFIGURABLE DATAPATH ARCHITECTURE Reiner W. Hartenstein, Rainer Kress, Helmut Reinig University of Kaiserslautern Erwin-Schrödinger-Straße, D-67663 Kaiserslautern, Germany
More informationDigital VLSI Testing Prof. Santanu Chattopadhyay Department of Electronics and EC Engineering India Institute of Technology, Kharagpur.
Digital VLSI Testing Prof. Santanu Chattopadhyay Department of Electronics and EC Engineering India Institute of Technology, Kharagpur Lecture 05 DFT Next we will look into the topic design for testability,
More informationChapter 9. Design for Testability
Chapter 9 Design for Testability Testability CUT = Circuit Under Test A design property that allows: cost-effective development of tests to be applied to the CUT determining the status of the CUT (normal
More informationFILTER SYNTHESIS USING FINE-GRAIN DATA-FLOW GRAPHS. Waqas Akram, Cirrus Logic Inc., Austin, Texas
FILTER SYNTHESIS USING FINE-GRAIN DATA-FLOW GRAPHS Waqas Akram, Cirrus Logic Inc., Austin, Texas Abstract: This project is concerned with finding ways to synthesize hardware-efficient digital filters given
More informationLuleå University of Technology Kurskod SMD098 Datum Skrivtid
Luleå University of Technology Kurskod SMD098 Datum 2001-12-17 Skrivtid 14.00 18.00 Tentamen i Beräkningstrukturer Antal uppgifter: 6 Max poäng: 35 Lärare: Jonas Thor Telefon: 2549 Tillåtna hjälpmedel:
More informationRTL Power Estimation and Optimization
Power Modeling Issues RTL Power Estimation and Optimization Model granularity Model parameters Model semantics Model storage Model construction Politecnico di Torino Dip. di Automatica e Informatica RTL
More informationUniversity of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences. Spring 2010 May 10, 2010
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2010 May 10, 2010 Final Exam Name: ID number: This is
More informationUnit 5F: Layout Compaction
Course contents Unit 5F: Layout Compaction Design rules Symbolic layout Constraint-graph compaction Readings: Chapter 6 Unit 5F 1 Design rules: restrictions on the mask patterns to increase the probability
More informationUnit 3: Layout Compaction
Unit 3: Layout Compaction Course contents Design rules Symbolic layout Constraint-graph compaction Readings: Chapter 6 Unit 3 1 Design rules: restrictions on the mask patterns to increase the probability
More informationFPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital
More informationController FSM Design Issues : Correctness and Efficiency. Lecture Notes # 10. CAD Based Logic Design ECE 368
ECE 368 CAD Based Logic Design Lecture Notes # 10 Controller FSM Design Issues : Correctness and Efficiency SHANTANU DUTT Department of Electrical & Computer Engineering University of Illinois, Chicago
More informationEECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs)
EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) September 12, 2002 John Wawrzynek Fall 2002 EECS150 - Lec06-FPGA Page 1 Outline What are FPGAs? Why use FPGAs (a short history
More informationBehavioural Transformation to Improve Circuit Performance in High-Level Synthesis*
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis* R. Ruiz-Sautua, M. C. Molina, J.M. Mendías, R. Hermida Dpto. Arquitectura de Computadores y Automática Universidad Complutense
More informationL2: Design Representations
CS250 VLSI Systems Design L2: Design Representations John Wawrzynek, Krste Asanovic, with John Lazzaro and Yunsup Lee (TA) Engineering Challenge Application Gap usually too large to bridge in one step,
More informationOutline. EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) FPGA Overview. Why FPGAs?
EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) September 12, 2002 John Wawrzynek Outline What are FPGAs? Why use FPGAs (a short history lesson). FPGA variations Internal logic
More informationThe Processor: Datapath and Control. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University
The Processor: Datapath and Control Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Introduction CPU performance factors Instruction count Determined
More informationTopics. ! PLAs.! Memories: ! Datapaths.! Floor Planning ! ROM;! SRAM;! DRAM. Modern VLSI Design 2e: Chapter 6. Copyright 1994, 1998 Prentice Hall
Topics! PLAs.! Memories:! ROM;! SRAM;! DRAM.! Datapaths.! Floor Planning Programmable logic array (PLA)! Used to implement specialized logic functions.! A PLA decodes only some addresses (input values);
More informationTDT4255 Computer Design. Lecture 4. Magnus Jahre. TDT4255 Computer Design
1 TDT4255 Computer Design Lecture 4 Magnus Jahre 2 Outline Chapter 4.1 to 4.4 A Multi-cycle Processor Appendix D 3 Chapter 4 The Processor Acknowledgement: Slides are adapted from Morgan Kaufmann companion
More informationEECS Components and Design Techniques for Digital Systems. Lec 20 RTL Design Optimization 11/6/2007
EECS 5 - Components and Design Techniques for Digital Systems Lec 2 RTL Design Optimization /6/27 Shauki Elassaad Electrical Engineering and Computer Sciences University of California, Berkeley Slides
More informationChapter 2 Logic Gates and Introduction to Computer Architecture
Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are
More informationHigh Level Synthesis. Shankar Balachandran Assistant Professor, Dept. of CSE IIT Madras
High Level Synthesis Shankar Balachandran Assistant Professor, Dept. of CSE IIT Madras shankar@cse.iitm.ac.in References and Copyright Tetbooks referred (none required) [Mic94] G. De Micheli Synthesis
More informationHW/SW Co-design. Design of Embedded Systems Jaap Hofstede Version 3, September 1999
HW/SW Co-design Design of Embedded Systems Jaap Hofstede Version 3, September 1999 Embedded system Embedded Systems is a computer system (combination of hardware and software) is part of a larger system
More informationEKT 422/4 COMPUTER ARCHITECTURE. MINI PROJECT : Design of an Arithmetic Logic Unit
EKT 422/4 COMPUTER ARCHITECTURE MINI PROJECT : Design of an Arithmetic Logic Unit Objective Students will design and build a customized Arithmetic Logic Unit (ALU). It will perform 16 different operations
More informationCAD of VLSI Systems. d Virendra Singh Indian Institute of Science Bangalore E0-285: CAD of VLSI Systems
CAD of VLSI Systems Introduction(Contd..) d Virendra Singh Indian Institute of Science Bangalore virendra@computer.org E0-8: CAD of VLSI Systems CAD of VLSI Systems Design of VLSI Systems Complex system
More informationIntroduction to CMOS VLSI Design (E158) Lecture 7: Synthesis and Floorplanning
Harris Introduction to CMOS VLSI Design (E158) Lecture 7: Synthesis and Floorplanning David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University
More informationDesign of Transport Triggered Architecture Processor for Discrete Cosine Transform
Design of Transport Triggered Architecture Processor for Discrete Cosine Transform by J. Heikkinen, J. Sertamo, T. Rautiainen,and J. Takala Presented by Aki Happonen Table of Content Introduction Transport
More informationOutline. Introduction to Structured VLSI Design. Signed and Unsigned Integers. 8 bit Signed/Unsigned Integers
Outline Introduction to Structured VLSI Design Integer Arithmetic and Pipelining Multiplication in the digital domain HW mapping Pipelining optimization Joachim Rodrigues Signed and Unsigned Integers n-1
More informationLecture #1: Introduction
Lecture #1: Introduction Kunle Olukotun Stanford EE183 January 8, 20023 What is EE183? EE183 is continuation of EE121 Digital Logic Design is a a minute to learn, a lifetime to master Programmable logic
More informationLecture 12 VHDL Synthesis
CPE 487: Digital System Design Spring 2018 Lecture 12 VHDL Synthesis Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 What is Synthesis?
More informationDesign Methodologies and Tools. Full-Custom Design
Design Methodologies and Tools Design styles Full-custom design Standard-cell design Programmable logic Gate arrays and field-programmable gate arrays (FPGAs) Sea of gates System-on-a-chip (embedded cores)
More informationControl and Datapath 8
Control and Datapath 8 Engineering attempts to develop design methods that break a problem up into separate steps to simplify the design and increase the likelihood of a correct solution. Digital system
More informationAdditional Slides to De Micheli Book
Additional Slides to De Micheli Book Sungho Kang Yonsei University Design Style - Decomposition 08 3$9 0 Behavioral Synthesis Resource allocation; Pipelining; Control flow parallelization; Communicating
More informationAnnouncements. This week: no lab, no quiz, just midterm
CSC258 Week 7 Announcements This week: no lab, no quiz, just midterm 2 Recap ALU Multiplication 3 To implement multiplication, we basically repeatedly do three things AND (one-bit multiplication) Addition
More informationSystem Level Design Flow
System Level Design Flow What is needed and what is not Daniel D. Gajski Center for Embedded Computer Systems University of California, Irvine www.cecs.uci.edu/~gajski System Level Design Flow What is
More informationLab 16: Data Busses, Tri-State Outputs and Memory
Lab 16: Data Busses, Tri-State Outputs and Memory UC Davis Physics 116B Rev. 0.9, Feb. 2006 1 Introduction 1.1 Data busses Data busses are ubiquitous in systems which must communicate digital data. Examples
More informationDIGITAL VS. ANALOG SIGNAL PROCESSING Digital signal processing (DSP) characterized by: OUTLINE APPLICATIONS OF DIGITAL SIGNAL PROCESSING
1 DSP applications DSP platforms The synthesis problem Models of computation OUTLINE 2 DIGITAL VS. ANALOG SIGNAL PROCESSING Digital signal processing (DSP) characterized by: Time-discrete representation
More informationPhiladelphia University Department of Computer Science. By Dareen Hamoudeh
Philadelphia University Department of Computer Science By Dareen Hamoudeh 1.REGISTERS WHAT IS REGISTER? register is a quickly accessible location available to a computer's central processing unit (CPU).
More informationField Programmable Gate Array (FPGA)
Field Programmable Gate Array (FPGA) Lecturer: Krébesz, Tamas 1 FPGA in general Reprogrammable Si chip Invented in 1985 by Ross Freeman (Xilinx inc.) Combines the advantages of ASIC and uc-based systems
More informationVLSI Test Technology and Reliability (ET4076)
VLSI Test Technology and Reliability (ET4076) Lecture 8 (1) Delay Test (Chapter 12) Said Hamdioui Computer Engineering Lab Delft University of Technology 2009-2010 1 Learning aims Define a path delay fault
More informationFolding. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall,
Folding ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2010 ldvan@cs.nctu.edu.tw http://www.cs.nctu.tw/~ldvan/ Outline Introduction Folding Transformation
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 18 Implementation Methods The Design Productivity Challenge Logic Transistors per Chip (K) 10,000,000.10m
More informationConstraint Analysis and Heuristic Scheduling Methods
Constraint Analysis and Heuristic Scheduling Methods P. Poplavko, C.A.J. van Eijk, and T. Basten Eindhoven University of Technology, Department of Electrical Engineering, Eindhoven, The Netherlands peter@ics.ele.tue.nl
More informationCHAPTER 3 METHODOLOGY. 3.1 Analysis of the Conventional High Speed 8-bits x 8-bits Wallace Tree Multiplier
CHAPTER 3 METHODOLOGY 3.1 Analysis of the Conventional High Speed 8-bits x 8-bits Wallace Tree Multiplier The design analysis starts with the analysis of the elementary algorithm for multiplication by
More informationREGISTER TRANSFER LANGUAGE
REGISTER TRANSFER LANGUAGE The operations executed on the data stored in the registers are called micro operations. Classifications of micro operations Register transfer micro operations Arithmetic micro
More informationComputer Organization
Register Transfer Logic Department of Computer Science Missouri University of Science & Technology hurson@mst.edu 1 Note, this unit will be covered in three lectures. In case you finish it earlier, then
More informationVHDL for Synthesis. Course Description. Course Duration. Goals
VHDL for Synthesis Course Description This course provides all necessary theoretical and practical know how to write an efficient synthesizable HDL code through VHDL standard language. The course goes
More informationLevels in Processor Design
Levels in Processor Design Circuit design Keywords: transistors, wires etc.results in gates, flip-flops etc. Logical design Putting gates (AND, NAND, ) and flip-flops together to build basic blocks such
More informationDec Hex Bin ORG ; ZERO. Introduction To Computing
Dec Hex Bin 0 0 00000000 ORG ; ZERO Introduction To Computing OBJECTIVES this chapter enables the student to: Convert any number from base 2, base 10, or base 16 to any of the other two bases. Add and
More informationCS6303 Computer Architecture Regulation 2013 BE-Computer Science and Engineering III semester 2 MARKS
CS6303 Computer Architecture Regulation 2013 BE-Computer Science and Engineering III semester 2 MARKS UNIT-I OVERVIEW & INSTRUCTIONS 1. What are the eight great ideas in computer architecture? The eight
More informationSoC Design for the New Millennium Daniel D. Gajski
SoC Design for the New Millennium Daniel D. Gajski Center for Embedded Computer Systems University of California, Irvine www.cecs.uci.edu/~gajski Outline System gap Design flow Model algebra System environment
More informationTECH. 9. Code Scheduling for ILP-Processors. Levels of static scheduling. -Eligible Instructions are
9. Code Scheduling for ILP-Processors Typical layout of compiler: traditional, optimizing, pre-pass parallel, post-pass parallel {Software! compilers optimizing code for ILP-processors, including VLIW}
More information