Post-Layout Timing-Driven Cell Placement Using an Accurate Net Length Model with Movable Steiner Points *

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1 Post-Layout mng-drven Cell Placement Usng an Accurate Net Length Model wth Movable Stener Ponts * Amr H. Ajam and Massoud Pedram Department of Electrcal Engneerng - Systems Unversty of Southern Calforna Los Angeles, CA {aajam, massoud}@zugros.usc.edu ABSRAC hs paper presents a new algorthm for tmngdrven cell placement usng the noton of movable Stener ponts that capture the net topology. he proposed algorthm mproves the tmng closure at the bacend of the EDA desgn flow. Unle conventonal flows that perform placement and routng n two separate steps and use rough estmates of the net lengths durng placement, our algorthm uses accurate net lengths by consderng the net topologes durng the Elmore delay calculaton step and dynamcally updates the routng durng the concurrent placement of Stener ponts and cells. he smultaneous placement and routng problem s formulated as a mathematcal program wth a small number of varables and solved by the Han-Powell method. Expermental results demonstrate the effectveness of the new approach compared to the conventonal flows. 1 Introducton he strong demand for complex hgh performance dgtal crcuts motvates a contnuous reducton of the mnmum feature sze n VLSI process technologes, whch n turn ntroduces new challenges. Specfcally, the nterconnect delay has become a domnant factor n delay calculatons. On the other hand, the strong demand for faster cloc speeds calls for more aggressve tmngdrven EDA tools. Inconsstency of the delay models that are used n dfferent stages of the EDA flow causes the tmng-closure problem (also nown as the soluton oscllaton problem) n conventonal flows. In contrast, unfcaton-based approaches, whch combne dfferent stages of optmzaton flow nto one ntegrated step, solve the tmng closure problem by usng unfed tmng and data models. o-date, the unfcaton-based approaches have mostly focused on the tmng-closure problem between the front-end (synthess) and bac-end (layout) of EDA flows [1]. hs paper presents a unfcaton-based approach to mprove the tmng-closure nsde the bac-end of an EDA flow, whch s caused by the nconsstency between the delay calculatons performed durng the placement and routng stages. In the past, ths nconsstency was gnored. However as the nterconnect delays become more domnant compared to the gate delays, ths conflct cannot be gnored anymore. mng drven placement has been studed extensvely n the lterature. Exstng technques may be classfed nto two major categores: net-based and path-based. *hs wor was supported n part by the SRC under contract number 98-DJ-606. In the net-based approach, after assgnng weghts to nets and updatng these weghts based on ther tmng crtcalty, the placement algorthm sees to mnmze the total weghted net length by placng the cells n an teratve manner [2] [3] [4] [5] [6] [7]. In the path-based approach, the placement algorthm chooses a fxed number of crtcal paths after performng tmng analyss on the crcut netlst and then sees to mnmze the delay of these paths by placng the cells [8] [9] [10] [11] [12] [13]. Path-based approaches formulate the tmng-drven placement problem more accurately than net-based approaches. Snce path-based approaches do not now the net topologes pror to the routng step, they often approxmate the net lengths usng models such as the mnmum boundng-box or the source-sn edge model [12] [14]. By performng global routng after the placement step, the exact topology of each net s determned due to the constructon of ts Stener routng tree. here are a number of dfferent Stener routers based on the objectve functon used. Earler wors tred to mnmze the cost (.e. the total edge length) of the resultng Stener routng tree [15]. More recent wors attempt to smultaneously mnmze the cost and the radus (the longest source-sn path length). In tmng-drven global routng (whch s our concern n ths paper), the objectve s to eep the crtcal-sn (CS) arrval tme delay to a mnmum whle mang the routng cost of the net as low as possble [16]. Standard bacend flow performs tmng-drven placement followed by tmng-drven global routng. In ths flow, the net length model used durng placement s based on the boundng-box model or clque model whereas durng global routng t s based on the CS-Stener routng trees. Due to ths nconsstency n determnng the net lengths, after performng the global routng the delay nformaton of crtcal paths may sgnfcantly change. Hence t becomes lely that newly created crtcal paths wll be ntroduced, whch n turn must be handled by another level of tmng-drven placement. hs soluton oscllaton happens to be costly n terms of the desgn tme. Worst of all, there s no guarantee that t wll eventually converge. In ths paper we use a placed and routed crcut as the ntal soluton. In contrast to the conventonal technques, whch estmate the length of the nets, our algorthm computes the net delays based on the exact length of each net by consderng ts topology as defned by the relatve arrangement of the Stener ponts n ts routng tree. Next, by smultaneously movng the Stener ponts and the cells on the most crtcal paths whle preservng the topology of each crtcal net, our algorthm mnmzes the arrval tmes of the prmary outputs by consderng the most crtcal paths. Optmzng the cycle tme s subject to satsfyng delay constrants on the fanout branches connected to the set of crtcal

2 G 1 paths so as to reduce the probablty of ntroducng new crtcal paths n the process. Our algorthm performs topologcal fx-ups durng the optmzaton routne to ensure the correct constructon of a mnmum crtcal-sn routng tree and lmt the potental ncrease n the total cost of the Stener trees. he remander of the paper s as follows. Secton 2 covers bacground ssues such as a revew of currently used delay models n tmng-drven placers and the delay model used n ths paper. Secton 3 ntroduces the problem formulaton, whle secton 4 descrbes the proposed algorthm and optmzaton technques. Expermental results and concludng remars are gven n sectons 5 and 6, respectvely. 2 Bacground 2.1 Wre length Model Path-based tmng-drven placers attempt to mnmze the delay of the crtcal path, whch n turn s dependent on the length of the nets on the path. hey often approxmate ths length usng the mnmum boundng box model. Consder net wth the source S 0 and n sns {S 1, S 2,, S n } (Fgure 1): Fgure 1: Mnmum-Boundng box for net. UR net and LL net denote the upper-rght corner and lower-left corners of the mnmum-boundng box, respectvely. he length of the boundng box s defned as the Manhattan dstance between these two corners tmes a varable ρ whch s a functon of the number of sns contaned n the boundng box and s used to adjust the estmaton error of ths nterconnect model [17]. he length of each net can be wrtten as: = ρ [( x x ) + ( y y )] (1) net UR LL UR LL Usng the boundng box model, however, gves rse to hgh naccuracy of delay estmates. hs fact motvates us to use a more detaled net length model, whch taes the topology of the net nto account. We now the exact topology of the Stener routng tree and can wrte the exact length of each source-to-sn path based on the locatons of the source node, the Stener ponts and the sn node. Assume the routng tree of net and ts equvalent lumped RC model as shown n Fgure 2: l 1 l 4 S 1 S 2 l 2 l 3 S 0 LL net G 4 G 2 r d1 C l1 S 1 S n R l1 C l4 UR net Fgure 2: A sample Stener tree of net. S 2 R l2 C l2 R l4 C l5 C l3 C n3 R l5 C n4 C n2 he exact net length l between gate G and Stener pont S j can be computed as: l = x x + y y (2) G S G S j j he lumped resstance and capactance for net are defned as: R.. l = rx lx+ ry l,.. y Cl = cx lx+ cy l (3) y where c x, c y, r x, r y are capactance per unt length n x and y drectons and resstance per unt length n x and y drectons, respectvely. We use the Elmore delay model to calculate the delay between two gates and model the nterconnect by usng a lumped crcut model. In Fgure 2, r d s the output resstance of the drver gate, C n s are the nput capactance of sns and C l s and R l s are the lumped capactance and resstance of each nterconnect segment, respectvely. 2.2 Delay Calculaton Consder a net wth a source node and sn nodes. Elmore delay seen from the source to the th sn s computed as follows: delay d R. C m nt j j j= 1 = 1 n = + (4) where m s the number of ntermedate nodes on the path from the source to the th sn, R j s the total sum of resstances from the source node up to the j th node on the path from the source to the th sn, and C j s the capactance seen at node j on the path plus the summaton of downstream capactances seen at n sde-branches gong out of the j th node. We denote the ntrnsc delay of the source gate as d nt. o use the exact value of both lumped capactances and resstances for ndvdual segments of nets, we need to consder the topology of each net, whch s nown after the routng phase. We consder two forms of delay calculaton based on ther complexty and accuracy Delay Formulaton I Assume we want to wrte the delay between source gate G 1 and sn gate G 2 n Fgure 2. By rearrangng the delay equaton, we obtan: dg (, G) = r ( C+ C ) + R ( C+ C ) d1 n 1 n = 1 = 2 = 2 = 2 + R ( C + C + C + C ) + R C + d n2 n4 3 n2 nt o smplfy the notaton we only consder the 1-D space (extenson to both x and y drectons s straghtforward). In general, by consderng Fgure 2, f there are movable Stener ponts on the path between two gates G and G j, the number of varable length net segments between them has a lower bound of 2+1 and an upper bound of 3+1, dependng on the number of fanouts gong out of each Stener pont. If we assume that there are p varable-length segments, then we can rewrte the propagaton delay d(,j) between gates G and G j based on the segment lengths by usng equatons (3) and (4) as follows: p p p d (, j) = α + κ ( M ) + K (6) j j = 1 = 1 j= 1 (5)

3 where α 1xp, κ 1xp, M pxp and K 1x1 are two constant vectors, a constant matrx, and a constant scalar value, respectvely. If we allow movable Stener ponts on the path between every par of cells, the number of varables used n equaton (6) wll be +2 (2+4 n 2-D space) Delay Formulaton II We mae an mportant observaton wth respect to the computaton of the d(,j) between G and G j. In practce r d s much larger than R l s where C l s are comparable to C n values. Consequently, t s more mportant to have an accurate value for C l s than for R l s. For ths reason, we use the Stener ponts to obtan accurate values for the capactance of partal nets (C l s), but use the mnmum boundng box to derve the resstance of the whole net. In ths way the delay equaton (5) s smplfed to: dg (, G) = r ( C + C ) + R C+ d (7) 1 2 d1 n net n nt = 1 = 2 = 2 where R net s computed usng the length of the mnmum boundng box as n equaton (1) and C l s are calculated from equaton (3) n whch each l s calculated from equaton (2). By ntroducng new notaton, the propagaton delay derved n equaton (7) can be smply wrtten as: d (, j) = α + β net+ κ (8) coordnates for all cells and Stener ponts along the crtcal path. We also now all the arrval tmes at the prmary nputs (PI s) and the requred tmes at the prmary outputs (PO s). By performng tmng analyss on the crcut, we dentfy the tmng-crtcal prmary output (CPO) by fndng the PO wth the most negatve slac. We also now the arrval tme at the output of the last gate on each path branchng nto the crtcal path and the requred tme at the nput of the frst gate on each path branchng out of the crtcal path. Let M defne the set of movable objects (whch are cells and Stener ponts that are on the crtcal path) and F n and F out denote the set of all mmedate fann and fanout nodes of the crtcal path, respectvely (notce that nodes may be gates or Stener ponts). he mathematcal programmng formulaton of the problem s as follows: Maxmze (r CPO - a CPO ) (11) s.t. a + d(, j) aj 0 (, j) E :, j M Fn rj d(, j) r 0 (, j) E :, j M r a rcpo acpo Fout a start PI r req PO xmn x xmax M y y y M mn max where α, β and κ are constants and l net s calculated from equaton (1). If we allow movable Stener ponts on the path between every two cells, the number of varables used n equaton (8) wll be +4 (2+8 n 2-D space). 2.3 mng Calculaton n the Crcut Let a drected graph G(V,E) represent the crcut netlst n whch vertex set V s a one-to-one correspondence wth the gates on the netlst, and edge set E represents the drected connectons between vertces. Assocated wth each arc between two vertces,j, there s a d(,j) value whch denotes the propagaton delay between,j. Also for each gate G on the net there s an assocated arrval tme a and a requred tme r. he worst-case arrval tme a j and the requred arrval tme r at the two end ponts of an arbtrary arc (,j) on the graph are gven by: a = max{ a + d(, j) (, j) E} (9) j r = mn{( r d(, j) (, j) E) (10) j Gven the arrval tmes at the crcut nputs, start, and requred tmes at the crcut outputs, req, we can easly compute the arrval and requred tmes for all the gates n the vertex set V. Based on these values, a slac s for vertex s defned as s = r -a. A negatve slac represents a tmng volaton over that vertex. A crtcal path Γ s a sequence of vertces (v s,.v e ) along a path from prmary nput v s to prmary output v e where all vertces have negatve slacs. 3 Mathematcal Problem Formulaton We start wth a placed and routed crcut, so we are gven the ntal where a CPO and r CPO are the arrval and requred tmes at the CPO and x mn, x max, y mn and y max are the coordnates of the lower left and upper rght corners of the chp. As we stated before, the arrval tmes at output of fann gates and requred tmes at nput of fanout gates and are nown values after a tmng analyss pass (Fgure 3). he frst and second sets of constrants smply descrbe the equatons used to capture the tmng calculaton n the crcut. he thrd set of constrants states that the slac on any path branchng out of the current crtcal path should be no more negatve than the slac of the crtcal path tself. hs constrant therefore mnmzes the chance that a new crtcal path wll be generated after optmzng the current crtcal path. Notce that ths constrant cannot guarantee that no new crtcal path wll be created because of the possblty that the fanout branches may reconverge n the crcut after they leave the current crtcal path. he remanng sets of constrants descrbe the boundary condtons for tmng calculaton and for placement. PI F n r =nown F out a =nown CPO Fgure 3: Fann and Fanout constrants (crtcal path s shown n thc lnes).

4 Consder a crcut wth N nodes (ncludng PI s, PO s, nternal gates, and Stener ponts for the nets connectng these gates). Suppose that the current crtcal path has n nodes (a PI, a PO, and n-2 movable nodes n between) and that the cardnaltes of the correspondng F n and F out sets are p and q, respectvely. hus the mathematcal optmzaton problem formulaton descrbed by system of equatons (11) only has n+p arrval tme varables, n requred tme varables, and 2n poston varables. As we saw n secton 2.2, d(,j) can be wrtten as a polynomal of partal sums of resstances and capactances on the ntermedate nodes of the path connectng gates G and G j. hese partal sums are functons of net segment lengths that comprse the arc (v,v j ) and ts fanout branches. In general d(,j) s a functon of the physcal coordnates of gate G, gate G j and all ntermedate Stener ponts over the arc (v,v j ). Note that d(,j) s not a polynomal (because of the absolute values presented by the Manhattan dstances between two ntermedate nodes). Observaton: Problem formulaton (11) s a non-convex program. Computng the Hessan matrx of the tmng constrants proves ths. More precsely, we can show that the Hessan s not postvesem defnte and hence the system of equatons (11) s a nonconvex optmzaton problem. Consequently, usng the smplex method or any nd of quadratc programmng technque cannot solve ths problem formulaton. Notce that by usng (8) n secton 2.2.2, we ntroduce more varables nto formulaton (11), so usng (8) nstead of (6) has lttle mpact on reducng the computaton tme for solvng the optmzaton problem. For these reasons we wll use delay formulaton I of secton for calculatng the delay between two gates. Each length l s the absolute value of the dfference between the x-coordnates of the two endponts of the correspondng net segment. Note that one or both of the x- coordnates can be varables. We approxmate the absolute value functon wth a dfferentable smooth functon as follows: l = x x ( x x ) + β (12) 2 j j β s called the regularzaton factor, whch has a very small magntude and s set based on the requred precson of the fnal results [18]. By substtutng equaton (12) nto equaton (6), the constrants n problem formulaton (11) wll become a functon of arrval tmes and requred tmes at each gate on the crtcal path and ts frst neghbors and the physcal coordnates of the Stener ponts and the cells on the crtcal path. 4 Problem Optmzaton We frst provde the theoretcal bacground to motvate the way we solve problem formulaton (11). 4.1 Bacground heorem 1: (Kuhn-ucer s frst order necessary condton) Consder the followng problem: Mn f(x) (13) s.t. g(x) 0 Let α be a relatve mnmum pont for problem (13) and suppose α s a regular pont for the constrants. here s a vector λ E M such that: f ( α ) + λ g( α ) = 0 λ g ( α ) = 0 (14) he Lagrangan for system of equatons (14) can be defned as L(x)=f(x)+λ g(x). As noted before problem formulaton (11) s non-convex,.e. the Hessan of ts Lagrangan s not postve defnte. For ths reason we try to convexfy the Lagrangan n the local sub-space and fnd a descent drecton toward the global mnmum. One common way s to defne a mert functon that s defned for the purpose of measurng the progress toward the global optmum. he mert functon must be defned so as to be a mnmum at the soluton of the orgnal problem, and at the same tme, ts value to decrease at each optmzaton step. Another effectve method approxmates the Lagrangan matrx such that the new matrx s postve sem-defnte and updates t teratvely durng optmzaton steps. 4.2 Optmzaton echnque he bass of our optmzaton technque s the quas-newton method, whch s a structured, modfed Newton algorthm usng an approxmaton and successve updates of the Lagrangan matrx. he teratve process s stated as follows: 1 x+ 1 x B gx ( ) Lx (, λ) α λ = + 1 λ gx ( ) 0 gx ( ) (15) where B s a postve sem-defnte approxmaton for Lagrangan L and wll be updated at each teraton. By solvng the above lnear system of equatons, we fnd the values of x and λ for the next step. hs process s then repeated. α s a factor defned by the specfed mert functon to mprove the convergence rate of the teraton. In the quas-newton method, the value of α s usually set to 1. he value of matrx B can be updated as follows: B qq Bpp B +1 = B + q p p B p = + 1, = ( + 1, λ+ 1) (, λ+ 1) p x x q Lx Lx (16) It has been shown that f the ntal guess s suffcently close to the soluton (x,λ), ths method converges to ths soluton super lnearly. However, t s obvous that ths closeness condton s unsatsfactory when loong for a general method to solve system (13). Also notce that after updatng Matrx B, there wll be no guarantee that the matrx remans postve sem-defnte. he Han-Powell method s a varant of the quas-newton method n whch a quadratc mert functon s used to update α as well as B. It can be shown that durng the Han-Powell method, the matrx B always remans postve sem-defnte and that the Han-Powell method s a globally convergent method snce the search drecton gven by the mert functon s a descent drecton [19].

5 4.3 opology Correcton Due to the movements of Stener ponts along the crtcal path durng the optmzaton steps, t s possble to fnd that some of the fanout net lengths become large. hs may occur, for example, n order to shorten a partcular source to sn path n the routng tree at the expense of ncreasng the overall routng length. hs stuaton s descrbed by an example n Fgure 4. Assume that gate G 2 has a very large nput capactance n comparson to the other gates, whch s possble when usng a rch lbrary of gates. At the same tme assume that because of some physcal constrants mposed by other fanns of gate G 2 or because we may ncrease the output load of G 2, t s not possble to move gate G 2 toward gate G 1. Havng relatvely small drver strength for gate G 1 forces us to reduce the length of the path between gate G 1 and G 2 as much as possble, whch n turn forces gate G 1 to move toward G 2 and hence ncreases l 4 and (Fgure 4b). G 1 G 2 (a) Fgure 4: (a) he orgnal net topology and (b) the net topology after movng cells and Stener ponts. Notce that the topology of the routng tree subsequently needs to be changed to mprove the delay and wre length. Indeed by overlappng l 4 and routes and removng the shared part of one of them and ntroducng a new Stener pont we wll mprove the delay of the crtcal path as well as reduce the total wre lengths (Fgure 5). In general we can do ths nd of fx-up when t does not volate the tmng constrants at the outputs of gates and G 4. G 4 l 4 G 4 G 1 l 4 G 4 l 4 (b) G 1 G 2 Fgure 5: Routng tree after topology correcton. 4.4 Flow of the Proposed Method he complete flow of the proposed algorthm wll be as follows: 1. Start wth an ntal soluton produced by a tmng-drven placement and global routng tool. 2. Perform tmng analyss on the crcut to extract the most crtcal paths. 3. Construct the problem formulaton (11) usng the physcal locaton of each cell and Stener pont on the crtcal path and the arrval tmes at each gate as the system varables. 4. Perform one step of the quas-newton or Han-Powell teraton methods. G 2 5. Correct the topology of fanout nets as descrbed n secton Update problem formulaton (11) to reflect any net topology changes n step Go bac to step 4 and repeat unless a satsfactory result has been generated. 8. Stop f all the crtcal path delays are optmzed; otherwse, go bac to step 2 and repeat. 5 Expermental Results o show the effectveness of the proposed algorthm, we appled t to a number of benchmar crcuts. he experments were done on a 700MHz P-III wth 256MB of memory. he results are reported on able 1. In the frst three columns the netlst nformaton of each crcut s gven. o test our algorthm we frst place the crcuts wth a smulated annealng based placer (mberwolf 1.0) followed by a tmng-drven placement step [12] that uses the boundng-box estmaton for each net. hen we perform a C-ER global routng over the crcut [15]. he delay (ns), area (mm 2 ) and runnng tme (sec) after these steps are reported under P&R columns of the able 1. Note that the reported delay s the propagaton delay after placement and routng usng the topology of the constructed Stener trees and based on the exact net lengths. Our results after dong tmng-drven placement wth movable Stener ponts are gven n the PGR columns. As one can see, there s a tmng performance mprovement between 9 to 14 percent, at the cost of a slght ncrease n the chp area. As was expected, the run tme s hgher for PGR due to the nonlnearty of the optmzaton objectve and the teratve nature of the Han- Powell method. Even though the runnng tme of one pass of P&R flow s shorter, performng the global routng stage wll change the tmng nformaton of the crcut due to the nconsstency of the delay model n the placement and routng stages. Hence, for obtanng the same performance mprovement as PGR, we need to perform multple teratons of P&R, whch can be more costly n terms of runnng tme than PGR and there s no guarantee that ths teratve process converges at the end. In contrast, the PGR flow s a one-shot optmzaton process based on a stable and rather effcent optmzaton method. 6 Concluson hs paper presented a new algorthm for performng tmng-drven placement wth global routng nformaton usng the noton of movable Stener ponts. he proposed algorthm uses accurate net lengths by consderng the net topologes durng the Elmore delay calculaton step and dynamcally updates the routng durng the concurrent placement of Stener ponts and cells. he smultaneous placement and routng problem was formulated as a mathematcal program wth a small number of varables and solved by the Han- Powell method. Expermental results demonstrated the effectveness of the new approach compared to the conventonal flows. Future wor conssts of ntegratng ths algorthm wth a post-layout buffer nserton technque.

6 Crcut #cells #cells P & R PGR CP area delay runtme area delay runtme Delay Imp. % C C C C C C des bomed Area Inc.% able 1: Comparng PGR wth conventonal P&R flow. References: [1] A. Sale, J. Lou, M. Pedram, A Smultaneous Routng ree and Fanout Optmzaton Algorthm, Proc. Intl. Conf. on CAD, pp , [2] A.E. Dunlop, V.D. Agrawal, D.N. Deutsch, M.F. Jul, P. Koza, M. Wesel, Chp Layout Optmzaton usng Crtcal Path Weghtng, Proc. Desgn Automaton Conf., pp , [3] P. Hauge, R. Nar, E. Yoffa, Crcut Placement for Predctable Performance, Proc. Intl. Conf. on CAD, pp , [4] S. Ou, M. Pedram, mng-drven Placement Based on Parttonng wth Dynamc Cut-Net Control, Proc. Desgn Automaton Conf, pp , [5]. Gao, P.M. Vdya, C.L. Lu, A Performance Drven Macro- Cell Placement Algorthm, Proc. Desgn Automaton Conf., pp , [6] M. Mare-Sadowsa, S. Ln, mng Drven Placement, Proc. Int. Conf. On CAD, pp , [7] M. Sarrafzadeh, D. Knol, G. ellez, Unfcaton of Budgettng and Placement, Proc. Desgn Automaton Conference, pp , [8] W. Donath, R. Norman, B. Agrawal, S. Bello, S. Han, J. Kurtzberg, P. Lowy, R. MacMllan, mng Drven Placement usng Complete Path Delays, Proc. Desgn Automaton Conf., pp , [9] W. Swartz, C. Sechen, mng Drven Placement for Large Standard Cell Crcuts, Proc. Desgn Automaton Conf., pp , [10] A. Srnvasan, An Algorthm for Performance-Drven Intal Placement for Small-Cell ICs, Proc. Int. Conf. on CAD, pp , [11] M.A.B. Jacson, E.S. Kuh, Performance-Drven Placement of Cell Based IC s, Proc. Desgn Automaton Conf., pp , [12]. Kode, M. Ono, S. Waabayash, Y. Nshmaru, N. Yoshda, A New Performance Drven Placement Method wth Elmore Delay Model for Row Based VLSI, Proc. Asa and South Pacfc DAC, pp , [13] J.M. Kelnhans, G. Sgl, F.M. Johannes, K. Anterch, GORDIAN: VLSI Placement by Quadratc Programmng and Slcng Optmzaton, IEEE rans. Computer-Aded Desgn, vol.10, No.3, pp , Mar [14] B.M. Ress, G.C. Ettelt, SPEED: Fast and Effcent mng Drven Placement, Proc. Intl Symp. of Crcuts and Systems pp , [15] A.B. Kahng, G. Robbns, A New Class of Iteratve Stener ree Heurstcs wth Good Performance, IEEE rans. Computer-Aded Desgn, vol.11, pp , July [16] K.D. Boese, A.B. Kahng, B.A. McCoy, G. Robns, Near- Optmal Crtcal Sn Routng ree Constructon, IEEE rans. Computer-Aded Desgn, vol.14, No.12, pp , [17] W. Chen, C. Hseh, M. Pedram, Smultaneous Gate Szng and Placement, IEEE rans. Computer-Aded Desgn, vol. 19, No.2, pp , Feb [18] C.J. Alpert,.F. Chan, A.B. Kahng, I.L. Marov, P. Mulet, Faster Mnmzaton of Lnear Wrelength for Global Placement, IEEE rans. Computer-Aded Desgn, vol.17, No.1, Jan [19] D. Luenberger, Lnear and Nonlnear Programmng, 2 nd edton, Addson-Wesley Pub. Company, 1984.

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