A Min-Cost Flow Based Detailed Router for FPGAs

Transcription

1 A Mn-Cost Flow Based Detaled Router for FPGAs eokn Lee Dept. of ECE The Unversty of Texas at Austn Austn, TX Yongseok Cheon Dept. of Computer cences The Unversty of Texas at Austn Austn, TX Martn D. F. Wong Dept. of ECE Unversty of Illnos at Urbana-Champagn Urbana, IL ABTRACT Routng for FPGAs has been a very challengng problem due to the lmtaton of routng resources. Although the FPGA routng problem has been researched extensvely, most algorthms route one net at a tme, and t can cause the netorderng problem. In ths paper, we present a detaled routng algorthm for FPGAs based on mn-cost flow computatons. Usng the mn-cost flow approach, our algorthm routes all the nets connected to a common logc module smultaneously. At each stage of the network flow computaton, we guarantee optmal result n terms of routablty and delay cost. For further mprovement, we adopt an teratve refnement scheme based on the Lagrangan relaxaton technque. The Lagrangan relaxaton approach transforms the routng problem nto a sequence of Lagrangan subproblems. At each teraton of the algorthm, Lagrangan subproblems are solved by our mn-cost flow based routng algorthm. Any volaton of congeston constrants s reflected n the value of correspondng Lagrangan multpler. The Lagrangan multplers are ncorporated nto the cost of each routng rosource node and gude the router. Because our mn-cost flow based algorthm mnmzes cost functon whle t maxmzes the flow, our algorthm fnds congeston-free routng solutons wth mnmum total delay. Comparson wth VPR router shows that our router uses less or equal number of routng tracks wth smaller crtcal path delay as well as total routng delay. Keywords FPGA routng, mn-cost flow algorthm, Lagrangan relaxaton 1. INTRODUCTION Due to ther low manufacturng cost and tme, feld programmable logc arrays (FPGAs) have been very popular for rapd system prototypng, logc emulaton, and reconfgurable computng. Fgure 1 shows a typcal array-based FPGA archtecture. An array-based FPGA conssts of a two-dmensonal array of logc modules, vertcal and horzontal routng channels, and swtch modules. The logc modules contan combnatonal and sequental crcuts to realze logc functons. The routng channels and the swtch modules comprse the routng resources of an FPGA. The Ths work was partally supported by the Natonal cence Foundaton under grant CCR Permsson to make dgtal or hard copes of all or part of ths work for personal or classroom use s granted wthout fee provded that copes are not made or dstrbuted for proft or commercal advantage and that copes bear ths notce and the full ctaton on the frst page. To copy otherwse, to republsh, to post on servers or to redstrbute to lsts, requres pror specfc permsson and/or a fee. ICCAD 03, November 11-13, 2003, an Jose, Calforna, UA. Copyrght 2003 ACM /03/ $ vertcal channel L L L L L L L L L swtch module horzontal channel LUT logc module FF nput pn Fgure 1: Typcal FPGA archtecture output pn routng channels usually have varous lengths of wre segments to mprove crcut performance and mantan reasonable routablty at the same tme. Routng of an FPGA s performed by programmng the swtches to connect the wre segments. Due to ther hgh RC delays and large area, the routablty of swtch modules are usually lmted. It s wdely known that the feasblty of FPGA desgn s most constraned by routng resources, and routng delays domnate the performance of FPGAs. The routng problem of the array-based FPGAs has been extensvely studed by researchers[4, 6, 9, 12, 13, 14, 16, 18]. Most FPGA routers route one net at a tme, and they suffer from netorderng problem n whch routng results may vary sgnfcantly dependng on the orderng of the nets to route. The PathFnder algorthm[14] allevates ths problem by welldesgned rp-up and reroute scheme. The VPR router[16], based on a careful mplementaton of the PathFnder algorthm, s a very successful placement and routng tool. In ths paper, we present an effectve routablty drven detaled routng algorthm, whch also consders routng delay. Our algorthm frst consders the problem of routng all the nets connected to one common logc module through logcally equvalent nput pns. We assume the LUT-based logc modules for our target archtecture. Our algorthm explots the fact that the nput pns of a LUT are logcally equvalent, and t routes all the nets connected to one LUT smultaneously. Our algorthm s based on mn-cost flow computatons, and t guarantees to fnd a congeston-free wre type assgnment soluton f one exsts. Furthermore, t can fnd a soluton wth mnmum total delay at the same tme. Although network flow frameworks have been used for varous

2 c d a L 1 L 2 L 3 L 4 b e g h net1 net2 Fgure 2: A routng graph and the routng trees for two nets. Black nodes represent nput pn nodes, whte nodes correspond to output pn nodes, and the gray nodes correspond to the wre segments. Edge pars between the nodes are represented by the bdrectonal edges for smplcty. routng algorthms[3, 7, 11, 15], most of those algorthms need to solve the multcommodty flow problems whch cannot guarantee nteger flow solutons. Although [15] proposed an algorthm based on mn-cost flow algorthm, t can only handle the nets connected to a common node. To allevate the possble orderng problem n LUT selecton, and to further mprove the routng results, we adopt an teratve refnement scheme based on Lagrangan relaxaton. In the Lagrangan relaxaton framework, the routng problem s transformed nto a sequence of subproblems called the Lagrangan subproblems. Each subproblem corresponds to the routng problem for all the nets connected to a LUT, and t s solved by mn-cost flow computaton. At each teraton of our algorthm, volatons n congeston constrants are reflected n the value of correspondng Lagrangan multplers, and the multplers gude the router. The rest of the paper s organzed as follows. The FPGA detaled routng problem s defned n secton 2. In secton 3, we present the flow network graph constructon scheme and our network flow based algorthm for routng nets together wth the Lagrangan relaxaton framework for teratve refnement. Expermental results are shown n secton 4, and we conclude the paper n secton PROBLEM FORMULATION Routng of an FPGA s performed by programmng the swtches to connect the wre segments. Unlke the nterconnectontracksncustomics,awresegmentnanfpga cannot be shared by dfferent nets. Together wth performance constrants, ths congeston constrants make FPGA routng a very challengng problem. The problem of routng FPGAs s assgnng nets to routng resources to route all nets successfully. The routng archtecture of an FPGA can be modeled wth a routng graph G(V,E). A set of nodes f V n ths drected graph represents the nput pns and output pns of logc modules, and the wre segments. The set of edges E corresponds to feasble connectons between the routng resources represented by nodes. We can attrbute a set of capacty R and a set of cost C to each node and edge n G. A capacty of a node (or an edge) denotes the avalable number of the pn or wre segment (swtch), and a cost of a node (an edge) represents the routng delay through the correspondng routng resource. For detaled routng, capactes for all the routng resources can be set to 1. A route of a net corresponds to a subtree n G. The root of a routng tree s the source of the net, and all the leaf nodes are the snks of the net. Because no resource can be shared by dfferent nets, the routng trees for the nets are vertex dsont. Fgure 2 shows an example of a routng graph and routng trees. Nodes and edges are supermposed on the correspondng routng resources. The problem addressed n ths paper s stated below: FPGA detaled routng problem: Gven a routng resource graph G for an FPGA archtecture, fnd vertex dsont routng trees n G for all the nets. To allevate the net orderng problem, we route several nets connected to a common logc module smultaneously rather than routng nets one by one. As shown n Fgure 1, we assume a wdely used model of a logc module, whch conssts of several look-up tables (LUTs) and flp-flops. In ths paper, we assume that a logc module has one LUT n t for the smplcty of presentaton unless stated otherwse. Because all the nputs of a LUT are logcally equvalent, they are permutable when they are assgned to the routes for the nets connected to the LUT. In our routng algorthm, we route all the nets connected to a LUT smultaneously. For multple-pn nets, we route a porton of net (net segment) branched from a partal routng tree prevously constructed for the net. In the example shown n Fgure 2, both of net1 and net2 are connected to a logc module L 2. Net1 s a multple-pn net. uppose the routng tree for net1 s already constructed partally (from L 1 to L 4 usng wre segments a and g) when the logc module L 4 s processed. Then, only the porton of the tree branchng from ths partally constructed tree needs to be routed when the module L 2 s handled. Before statng the overall routng problem, we defne a smaller problem as follows: The Routng for One LUT (ROL) Problem: Gven a routng resource graph G(V,E) andalut,fndroutesfor all the net segments connected to the LUT such that each edge and node s used at most once. Because we wll use mn-cost flow computaton to solve ROL problem, we can also mnmze the total cost of the routes for the nets. By solvng the ROL problem for each LUT, we can solve the overall routng problem for an FPGA. As ROL problem for each LUT s solved, branches of routngs trees for the nets are gradually constructed, and after solvng ROL for all the LUTs, we can get the routng trees forallthenetsnanfpga.intheexampleoffgure2, although only a porton of net1 s routed when L 4 s processed, by the tme when routng for L 2 s fnshed, routng trees for both of net1 and net2 are fully constructed. The FPGA detaled routng problem can be formulated as: 389

3 Mnmze subect to P,k cx k P k x k 1 x X V,and where x s a decson varable for each node (or edge) defned as 1, f the routng of net k uses node (or edge) x k = 0, otherwse c s the cost of node (or edge), x s the vector of x k,and X s the set of all possble routes of each net. 3. ALGORITHM DECRIPTION In ths secton, we descrbe the algorthms to solve the problems ntroduced n the prevous secton. By performng the mn-cost max flow computatons on the flow network whch s constructed from G, our algorthm for the ROL problem, ROL NF, can solve the ROL problem n polynomal tme. Because each routng resource can be accessed by several nets, there can be dependency between the flows computed for each LUT. To avod ths orderng problem of LUTs processed by ROL NF, we adopted an teratve refnement scheme based on Lagrangan relaxaton. Lagrangan relaxaton s a general technque for solvng optmzaton problems wth dffcult constrants. In Lagrangan relaxaton, constrants are relaxed and added to the obectve functon after beng multpled by coeffcents called Lagrangan multplers. In our scheme, the congeston constrants are relaxed, and the Lagrangan multplers used to relax the congeston constrants are added to the cost for each node to gude the router to fnd less congested routes for the nets. 3.1 Mn-cost flow algorthm to route nets for one LUT To solve the ROL problem for a LUT, we construct the flow network from the routng graph. We wll apply a mncost flow algorthm on the constructed flow network. Let L = {l 1,l 2,..., l m} be a set of all LUTs n an FPGA. Gven a routng graph G(V,E) wth capacty R and cost C and a LUT l k, we construct the flow network G f (V f,e f )asfollows: 1. V f = V {s, s 1,s 2,..., s n,t}, wheres s a source node, and s s a subsource node, and t s a snk node of G f (V f,e f ). n s the number of nets connected to l k. 2. E f = E E s E s E t, where E s = {(s, s ) = 1, 2,..., n}, E s = {(s,v) =1, 2,..., n, v T }, E t = {(p,t) p p}. T denotes a partally constructed routng tree for net, and p s a set of nodes correspond to the nput pns of l k. 3. Edge Capacty: r f (e) =1 e E f 4. Node Capacty: r f (v) =1 v V {s 1,s 2,..., s n}, nodes and node t are ncapactated. (r(), c( k (r(), c( k (a) (b) (r(), c( ' " (c) Fgure 3: Network transformatons: (a) Orgnal network. Note that the edge between node and node (e 1) s an undrected edge. (b) Transformaton to drected edges. (c) Node splttng. Node s splt to and. A capacty and a cost are assgned to the edge (, ). All the ncomng edges to node are connected to, and an outgong edge s replaced by an edge gong out of node. (Node splttng for node and node k are omtted.) 5. Edge Cost: c(e), f e E c f (e) = 0, otherwse 6. Node Cost: c(v), f v V c f (v) = 0, f v s, s 1,s2,..., s3,t The constructed flow network for a ROL problem s llustrated n Fgure 4. Note that the subsource nodes and the edge set E s are adaptvely updated for each l k dependng on the number of nets connected to l k and the partal routng tree of each net constructed n the process of solvng ROL problems for other LUTs. By connectng a subsource node to all the nodes belongng to a partal routng tree for a net, we can fnd the best branchng pont for the tener tree. To make our problem conform to the classcal network flow framework, we transformed G f (V f,e f ) to a drected graph n whch only edges have capactes and costs. Note that any undrected edges, whch can be formed due to bdrectonal wre segments, n G f (V f,e f ) can be transformed to a par of drected edges wth the cost and the capacty of the orgnal undrected edge [2]. By node splttng transformaton, any node wth nonzero cost and capacty s transformed nto the two nodes and. Ths transformaton replaces each of the orgnal edges (, ) and(, k) nto(, )and(,k), respectvely. It also adds an edge (, )wththecostand the capacty of node. Fgure 3 shows an example of the network transformatons. k 390

4 s 2 s s 1 s t s Fgure 4: A flow corresponds to ROL for 4 net segments connected to l 7. It can be shown that any flow n G f s a routng soluton for a subset of the gven nets to route. Each flow from s to t through subsources corresponds to a route for a net segment connected to l k. A node occuped by a flow corresponds to a wre segment used for the route, and the flow along an edge denotes that the correspondng swtch s used for the route. If a flow f exsts and f = n, thenwecan fnd a feasble soluton for all the net segments connected to the LUT, and the cost of the flow s the cost of a soluton to the ROL problem. nce we assgned 1 to all the edges and the number of edges connected to s s n, and t s the same as the number of edges connected to t, f n, where f s the maxmum flow n G f. If f <n,theres no feasble soluton to the ROL problem, and the mn-cost maxmum flow assgns routng resources to the routes for as many net segments connected to the LUT as possble wth mnmum total delay costs. The followng theorem shows that the ROL problem can be exactly solved by a network flow computaton on G f. Theorem 1. A mn-cost maxmum flow f n G f corresponds to a soluton to the ROL problem wth mnmum total delay cost. If the sze of f s n, the number of net segments connected to a LUT, then the ROL problem for the LUT s feasble so that all the net segments connected to the LUT can be routed. From the computed flow n G f, a soluton to the ROL problem can be derved by a depth-frst search from each nput pn node of the LUT to each subsource node n G f.because each subsource node s s assocated to a net segment and t s connected to the nodes belongng to the partal routng tree assocated wth that net, the node connected to the subsource node among the nodes n partal routng tree becomes a branchng pont for the branch from the routng tree to the LUT. Fgure 4 shows a flow f correspondng to a ROL soluton for 4 net segments connected to a LUT. In ths example, the net from l 1 s a multple-pn net, and a porton of ths net s routed whle l 14 s processed. Hence, the subsource s 2 s connected to all the nodes along the partally connected routng tree. Because only a flow of sze one can flow through s 2, only one node s selected as a branch- Fgure 5: Routes correspond to the flow computed n Fgure 4 Algorthm ROL NF Input: G(V, E), R, C, l k Output: routes for all net segments to l k begn 1. Construct the flow network G f (V f,e f ) 2. Assgn costs and capactes 3. Run mn-cost max-flow algorthm on G f (V,E) 4. Derve the correspondng routes from the computed flow end Fgure 6: Algorthm ROL NF ng pont. The routes correspond to the flow soluton of Fgure 4 s shown n Fgure 5. Fgure 6 summarzes our ROL NF algorthm. There are several polynomal-tme optmal algorthms avalable for fndng a mn-cost maxmum flow n a network[2]. Dervng a soluton to the ROL problem from a flow can be done n O(E) tme. Thus, the ROL problem can be solved effcently as stated n the followng theorem, f we adopt the double scalng algorthm[1]. Theorem 2. The ROL NF algorthm exactly solves the ROL problem n O(VEloglogR maxlog(vc max tme, where R max s the maxmum value of the capactes and C max s the maxmum value of the costs. 3.2 Iteratve refnement usng Lagrangan relaxaton In ths secton we solve the FPGA detaled routng problem. We apply the ROL NF algorthm successvely on all the LUTs n an FPGA. To avod orderng problem of selectng LUTs, we adopt an teratve refnement scheme based on Lagrangan relaxaton. We relax the congeston constrants n the FPGA detaled routng problem formulated n the prevous secton. Each of the constrants s multpled by the correspondng Lagrangan multpler, and added to the obectve functon. Let L λ (x) = X X c x k + X λ X ( x k 1) k 391

5 crcut #of #oftracks crtcal path delay (ns) total wre length LUTs vpr FlowRoute vpr FlowRoute mprove vpr FlowRoute mprove 9symml % % term % % apex % % example % % alu % % too-lrg % % vda % % alu % % s % % Table 1: Comparsons between VPR and FlowRoute n number of used routng tracks, delay, and total wrelength. Ths relaxed obectve functon s called the Lagrangan functon, and the Lagrangan subproblem assocated wth a fxed set of Lagrangan multplers λ s L λ : Mnmze L λ (x) For any gven λ, wenotethat L λ (x) = X X c x k + X λ X ( x k 1) k = X ( X c x k + X ) λ x k X = X X (c + λ )x k X λ Because P λ s a constant term, we can solve L λ for a gven λ by solvng ( ) X X L λ = mn (c + λ )x k k We solve ths reduced Lagrangan subproblem L λ by solvng the ROL problems for all LUTs n L after assgnng (c + λ ) to each node (edge) as a cost. After solvng the ROL problem, we reset the capacty of the edges to allow the relaxaton of the congeston constrants. To dscourage usng routng resources used n routng for nets to other LUTs, we defne the c term as follows, c = d q where d s a delay cost of node (edge), andq s the penalty term proportonal to the number of nets usng node (edge) currently. It s known that the mnmum value of the Lagrangan subproblem for any gven vector λ s a lower bound on the optmal obectve functon value of the orgnal optmzaton problem. Hence, the tghtest lower bound to the optmal obectve functon value s obtaned by solvng L =max λ 0 L λ whch s known as the Lagrangan dual problem. To solve the Lagrangan dual problem, an teratve approach s used. At each teraton, we solve L λ by solvng L λ for a gven λ, and then update the Lagrangan multplers for the next teraton usng the soluton of the current teraton. The λ Algorthm FlowRoute Input: G f, R, C, L Output: Routng trees for all nets n an FPGA begn 1. Intalze λ 2. for each l n L do 3. Rpupallthenetsconnectedtol k 4. Call ROL NF 5. Update costs and reset capactes 6. Update λ 7. Repeat tep 2-6 untl no shared resource exsts end Fgure 7: Algorthm FlowRoute Lagrangan multplers for ( + 1)th teraton are updated by the subgradent method [2, 5] as follows: ( ) λ +1 =max 0,λ + θ(x x k 1) k where θ P s a step sze wth the property that lm θ 0, and lm θ.weusedθ = a/( + b) as a step sze, where a and b are constants. By multplyng the amount of volatons of the congeston constrants, overly subscrbed routng resources can be penalzed over teratons. Fgure 7 summarzes our algorthm for the FPGA detaled routng problem, FlowRoute. 4. EXPERIMENTAL REULT We have mplemented our algorthms n C programmng language on a UN parc Ultra 5 (360MHz) wth 128M memory. The experments are performed on 9 crcuts from MCNC benchmark [17]. The placed netlsts were generated usng the placer n VPR [16]. We assumed a symmetrcalarray-based FPGA, where each logc block contans four 4- nput lookup tables and four flp-flops. We set F s =3and F c = W,whereW s the number of wre segments of each channel. F s denotes the number of connectons for each wrng segment enterng the swtch box. F c denotes the number of tracks to whch each logc block pn can connect. For the purpose of comparson, we used dentcal ntrnsc delay values and tmng models of VPR. We compared the mnmum number of tracks per channel to acheve feasble routngs for all nets, crtcal path delay, 392

6 and the total wre length from FlowRoute wth those from VPR router. Because FlowRoute s bascally a congestondrven detaled router, we compared our results from the ones obtaned by runnng VPR router n congeston-drven mode. Results are shown n Table 1. FlowRoute used smaller number of tracks per channel for 3 crcuts. Although FlowRoute s a congeston drven router, because t s based on mn-cost flow computaton, t shows mprovement n crtcal path delay up to 28.9 %(average 14.1 %). Because the obectve functon of the problem of ths paper s the total sum of delays of routng resources, we also compared total wre length. The wre lengths n the table are represented as nteger multple of one logc module length. The total wre length used to route all nets are reduced up to 13.3 % (average 8.3 %). 5. CONCLUION In ths paper, we proposed a congeston-drven detaled router for FPGAs. In our algorthm, we route all the net segments connected to a LUT smultaneously rather than routng one net at a tme. By routng several net segments smultaneously usng mn-cost flow computaton, our algorthm can allevate the net orderng problem. To avod orderng problem n selectng LUTs, we adopted an teratve refnement scheme based on Lagrangan relaxaton. Each of Lagrangan subproblems s solved by successve applcaton of mn-cost flow based routng algorthm on all the net segments connected to each LUT. We could fnd feasble routngs for the benchmark crcuts wth less or equal number of routng tracks per channel compared to VPR router. Furthermore, the total delays of the nets are also reduced, whch can contrbute to reducng crtcal path delay of the crcut. We compared our algorthm wth VPR router and the expermental results shows that our algorthm s very effectve. 6. REFERENCE [1] R.K.Ahua,A.V.Goldberg,J.B.Orln,and R. E. Taran, Fndng mnmum-cost flows by double scalng, Mathematcal Programmng 53, pp , [2] R. K. Ahua, T. L. Magnant and J. B. Orln, Network Flows: Theory, Algorthms, and Applcatons. Prentce Hall, [3] C. Albrecht, Provably good global routng by a new approxmaton algorthm for multcommodty flow, Proceedngs of ACM IPD-00, pp , 2000 [4] M. Alexander, G. Robns, New performance-drven FPGA routng algorthms, Proc. ACM/IEEE Desgn Automaton Conference, pp , [5] M.. Bazaraa, H. D. heral, and C. M. hetty, Nonlnear Programmng: Theory and Algorthms, 2nd ed. New York: Wley, [6]. Brown, M. Khellah, G. Lemeux, egmented Routng for peed-performance and Routablty n Feld-Programmable Gate Arrays, n Journal of VLI Desgn, [7] R. C. Carden, C. K. Cheng, A global router usng an effcent approxmate multcommodty multtermnal flow algorthm, ACM/IEEE DAC-91, pp , [8] Yao-Wen Chang, D. F. Wong, Ka Zhu, and C. K. Wong, On a New Tmng-Drven Tree Problem, n Proc. Intl. Conf. on Computer-Aded Desgn, 1994, pp [9] Yao-Wen Chang, D. F. Wong, C. K. Wong, FPGA Global Routng Based on a New Congeston Metrc, n Proc. Intl. Conf. on Crcut Desgn, 1995, pp [10] J.. wartz, V. Betz, J. Rose, A Fast Routablty-Drven Router for FPGAs, Proc. ACM/IGDA Internatonal ymposum on Feld ProgrammableGateArrays, 1998, pp [11] J. Huang, X. L. Hong, C. K. Cheng, and E.. Kuh, An effcent tmng-drven global routng algorthm, ACM/IEEE DAC-93, pp , [12] Y.-. Lee, C.-H. Wu, A performance and routablty drven router for FPGAs consderng path delay, n Proc. Desgn Automaton Conference, 1995, pp [13] G. G. F. Lemeux,. D. Brown, D. Vranesc, On Two-tep Routng For FPGAs, n Proc. Internatonal ymposum on Physcal Desgn, 1997, pp [14] L. McMurche, C. Eberlng, PathFnder: A Negotaton-Based Performance-Drven Router for FPGAs, n Proc. ACM/IGDA Internatonal ymposum on Feld Programmable Gate Arrays, 1995, pp [15] G. Mexner, U. Lauther, A new global router based on a flow model and lnear assgnment, Proc. ICCAD-90, pp.44-47, [16] V. Betz, J. Rose, VPR: A New Packng, Placement and Routng Tool for FPGA Research, n Proc. the 7th Annual Workshop on Feld Programmable Logc and Applcatons, 1999, pp [17]. Yang, Logc ynthess and Optmzaton Benchmarks, Verson 3.0, Tech. Report, Mcroelectroncs Center of North Carolna, [18] K. Zhu, Y.-W. Chang, D. F. Wong, Tmng-Drven Routng for ymmetrcal-array-based FPGAs, n Proc. Intl. Conf. on Computer Desgn, 1998, pp