Fisheye Lens Distortion Correction on Multicore and Hardware Accelerator Platforms

Transcription

1 Fiheye Len Diorion Correcion on Mulicore and Hardware Acceleraor Plaform Konani Dalouka 1 Chrio D. Anonopoulo 1 Nikolao Sek M. Bella 1 Chai 1 Deparmen of Compuer and Communicaion Engineering Univeriy of Thealy Volo, Greece Moorola Inc. Schaumburg, IL, USA

2 Inroducion Wide-angle lene a.k.a. fiheye lene are radiionally ued o enlarge he field of view in phoography A. Convenional recilinear len B. Full-frame fiheye len 98 degree horizonal by 147 degree verical C. Full circular fiheye len 180 degree horizonal and verical April 0, 010 IPDPS 010

3 Inroducion Main Applicaion Meeorology Aronomy Robo Navigaion Video Surveillance Video Conferencing Digial Camera The incoming ray are mapped ono a pherical urface Such mapping inroduce barrel diorion April 0, 010 IPDPS 010

4 Moivaion Explore he mapping of he algorihm inheren parallelim on hree conemporary plaform: x86 Chip Muliproceor Core Quad Cell B.E. proceor Virex-4 FPGA Preen a deailed characerizaion of he performance uing boh high- and low-level meric April 0, 010 IPDPS 010 4

5 Ouline Inroducion Wide-angle Lene Diorion Correcion Algorihm Decripion of Targe Plaform Algorihm Opimizaion Performance Evaluaion Concluion April 0, 010 IPDPS 010 5

6 Wide-angle Lene Diorion Correcion Tranformaion of he diored wide-angle image back o he cenral perpecive pace. April 0, 010 IPDPS 010 6

7 Projecion Model of Wide-angle Lene Cenral Perpecive Projecion Wide-angle Projecion April 0, 010 IPDPS 010 7

8 April 0, 010 IPDPS Algorihmic Flow A Invere Mapping: Map each image poin i, j o he correponding poin x, y in he wide-angle pace j i r r r r r r r r r Z Y X c c c d x x h Xc Yc Zc Yc Xc a R x 1 an d y y h Yc Xc Zc Yc Xc a R y 1 an

9 Algorihmic Flow A Need o approximae he value of fracional poiion in he fiheye pace Complex memory acce paern April 0, 010 IPDPS 010 9

10 Algorihmic Flow B Bicubic Inerpolaion: ue a 4x4 window of pixel o approximae inermediae poin April 0, 010 IPDPS

11 April 0, 010 IPDPS Algorihmic Flow B Bicubic inerpolaion i broken ino horizonal and verical 1D inerpolaion C i are he pixel value 4 5 * * * * U U U U U C U C U C U C x g 4 5 * * * * , V V V V V x g V x g V x g V x g y x G

12 Complee Algorihm For each pixel i, j in he cenral perpecive pace { Apply invere mapping o find fracional coordinae x, y in he wide-angle pace Ue bicubic inerpolaion o approximae he pixel value a x,y } Apply a D low pa filer and downcale oupu image o VGA reoluion 640x480 April 0, 010 IPDPS 010 1

13 Ouline Inroducion Wide-angle Lene Diorion Correcion Algorihm Decripion of Targe Plaform Algorihm Opimizaion Performance Evaluaion Concluion April 0, 010 IPDPS 010 1

14 Inel Core Quad A mainream homogeneou mulicore yem.5 GHz operaing frequency 1. GHz FSB Organized a wo independen dual core proceor block MB L cache for each block 64KB L1 cache for each proceor Suppor he SSE 4.1 vecor inrucion e April 0, 010 IPDPS

15 Cell Broadband Engine A heerogeneou mulicore proceor Inegrae a -way SMT PPC and 8 SPE. GHz operaing frequency Each SPE conain: A 18-bi wide SIMD execuion engine 56KB privae Local Sore On-chip nework EIB wih 07. GBp peak perf. Peak Performance: 04.8 GFlop for ingle-preciion 14.6 GFlop for double-preciion April 0, 010 IPDPS

16 Virex-4 LX80 FPGA Array of uncommied logic block Flexibiliy in ailoring he archiecure o mach he applicaion High power efficiency Virex-4 LX80: 80,640 logic cell 6.5 MHz operaing frequency Main drawback: Programmed primarily wih HDL Low clock frequency Correcion module generaed uing he Proeu archiecural ynhei ool April 0, 010 IPDPS

17 Proeu Produce hardware acceleraor ha follow he reaming paradigm Produce everal load/ore uni and he daapah a well The applicaion i expreed uing an aembly-like reaming DFG Source code i modulo-cheduled wih II = Generae 100K line of ynheizable Verilog from 800 line of code April 0, 010 IPDPS

18 Ouline Inroducion Wide-angle Lene Diorion Correcion Algorihm Decripion of Targe Plaform Algorihm Opimizaion Performance Evaluaion Concluion April 0, 010 IPDPS

19 High-Level Opimizaion Block Tiling Pariion he oupu image in block and correc a block of pixel a a ime Alleviae he problem of prefeching Faciliae efficien daa pariioning x86 and Cell and 1/x x aanx ak-level pipelining FPGA Invere Mapping Coordinae Y pixel Inpu pixel DMA Cb/Cr pixel Bicubic Inerpolaion Y,CbCr Verical low pa filer Y,CbCr Horizonal low pa filer Oupu pixel April 0, 010 IPDPS

20 x86 and Cell: Low-Level Opimizaion SIMD Opimizaion Explici loop unrolling Eliminae pipeline all from daa dependencie r r 1 r r r r r April 0, 010 IPDPS r 4

21 Low-Level Opimizaion x86 and Cell: Invere-mapping amorizaion Cell-pecific: Manual inrucion cheduling FPGA Modulo cheduling wih II = 400 DFG operaion in all pipeline age April 0, 010 IPDPS 010 1

22 Ouline Inroducion Wide-angle Lene Diorion Correcion Algorihm Decripion of Targe Plaform Algorihm Opimizaion Performance Evaluaion Concluion April 0, 010 IPDPS 010

23 Proceing Speed Frame/Sec Performance and Scalabiliy Analyi fp.8 fp 7.86 fp fp 9.94 fp.70 fp Invere Mapping Amorizaion HL+LL opimizaion HL opimizaion 8.01 fp 15.8 fp.8 fp Only PPE 1 SPE SPE 4 SPE 8 SPE 1T T 4T Virex-4 LX80 Cell Core Quad FPGA April 0, 010 IPDPS 010

24 Only PPE HL, 1 SPE HL, SPE HL, 4 SPE HL, 8 SPE HL+LL, 1 SPE HL+LL, SPE HL+LL, 4 SPE HL+LL, 8 SPE IMA, 1 SPE IMA, SPE IMA, 4 SPE IMA, 8 SPE HL, 1T HL, T HL, 4T HL+LL, 1T HL+LL, T HL+LL, 4T Virex-4 LX80 Module Runime Breakdown Performance and Scalabiliy Analyi Invere Mapping Bicubic Inerpolaion Low Pa Filer 100% 80% 60% 40% 0% 0% Cell Core Quad FPGA April 0, 010 IPDPS 010 4

25 MBye/ec Memory Performance hread 4 hread hread 1 hread Average Off-Chip Bandwidh Cell Core Quad Cell Core Quad Virex-4 LX 80 Cell HL opimizaion HL + LL opimizaion IMA April 0, 010 IPDPS 010 5

26 Billion Cycle cummulaive Sall Cycle,5 1,5 HL opimizaion HL + LL opimizaion IMA Sall Cycle 1 0,5 0 Toal Branch Mie Reource Relaed LD/ST Toal Branch Mie LS Buy Core Quad Cell April 0, 010 IPDPS 010 6

27 Developmen Co A ignifican facor ha mu be conidered One apec in he comparion of programming model in he hree plaform Ue Line-of-Code LOC a he primary meric Iniial ingle-hreaded verion: 800 line Fully-opimized verion for x86: exra 500 LOC Fully-opimized verion for Cell: exra 1500 LOC FPGA Implemenaion: 800 aembly-like LOC Require muliple ime-conuming ynhei and Place & Roue ieraion April 0, 010 IPDPS 010 7

28 Ouline Inroducion Wide-angle Lene Diorion Correcion Algorihm Decripion of Targe Plaform Algorihm Opimizaion Performance Evaluaion Concluion April 0, 010 IPDPS 010 8

29 Concluion Preened he implemenaion of a real-ime image warping algorihm Analyzed and characerized he performance on all underlying archiecure Applied a erie of opimizaion and idenified heir effec Commercially available general purpoe muli-core no capable of handling real-ime diorion correcion Exoic archiecure uch a Cell or FPGA offer he neceary compuaional power Significanly higher developmen co Advanced ool, developmen model and uppor environmen can alleviae hi effor April 0, 010 IPDPS 010 9

30 Acknowledgemen We would like o hank Barcelona Supercompuing Cener for providing u wih acce o heir IBM QS0 blade Thi projec i parially uppored by he EC Marie Curie Inernaional Reinegraion Gran IRG 819 April 0, 010 IPDPS 010 0