Optimizing the Processing Performance of a Smart DMA Controller for LTE Terminals

Transcription

1 Opimizing he Processing Performance of a Smar DMA Conroller for LTE Terminals David Szczesny, Sebasian Hessel, Shadi Traboulsi, Aila Bilgic Insiue for Inegraed Sysems, Ruhr-Universiä Bochum D-78 Bochum, Germany {david.szczesny,sebasian.hessel,shadi.raboulsi,aila.bilgic}@is.rub.de Absrac In his paper we presen an exended and opimized version of a smar Direc Memory Access () conroller supporing differen on-he-fly proocol sack acceleraion conceps for Long Term Evoluion (LTE) mobile erminals. In addiion o he downlink processing, we analyse differen on-he-fly hardware acceleraion modes for he uplink proocol sack processing in layer (L). Moreover, he sysem performance is furher improved by adoping parallelizaion mehods. The efficiency of on-he-fly hardware acceleraion is proved by comparing he ranspor block processing imes o hose achieved wih a convenional hardware acceleraor. Therefore, a cycle approximae virual prooype of a sae-of-he-ar mobile phone plaform based on an ARM76 processor is simulaed a LTE-Advanced daa raes of up o Gbi/s. In uplink direcion, we are able o reduce he complexiy in he conroller and simulaneously improve he processing performance in he mobile plaform. This is realized by inelligen hardware/sofware pariioning and an opimized descripor forma. Furhermore, a significan opimizaion (up o %) of he sysem performance in a mobile device is achieved by adoping parallelized on-he-fly hardware acceleraion modes. We show how he conroller clearly ouperforms he radiional approach by reaching speedups of up o % and 66 % for he ranspor block processing imes in uplink and downlink direcions, respecively. I. INTRODUCTION In GPP s Long Term Evoluion (LTE) and in he nex upcoming mobile communicaion sandard LTE-Advanced, he peak daa raes are increased up o Mbi/s and even Gbi/s, respecively. This general rend in wireless echnologies is mainly driven by new services and feaures like video sreaming or online gaming. Simulaneously growing algorihm complexiy and decreasing laencies are challenging facors for mobile devices where compuaional resources and baery lifeime are sricly limied. Even hough a lo of work has already been done regarding he physical layer [], inensive invesigaions of higher proocol sack layers like he layer (L) are sill required o suppor hese high ransfer raes in mobile erminals. Wih efficien hardware/sofware pariioning conceps, ha adop dedicaed hardware acceleraors for he ime criical asks, he processing performance and he power consumpion of an embedded sysem can be improved [], []. Therefore, we presened already a promising approach for he LTE downlink proocol sack processing in []. I is based on a smar Direc Memory Access () conroller which significanly ouperforms convenional hardware acceleraors by applying on-he-fly hardware acceleraion for he header decoding and decrypion. In his work, however, we invesigae differen on-he-fly hardware acceleraion conceps for he uplink proocol sack processing. Moreover, by simulaing LTE-Advanced ransmission condiions of up o Gbi/s, we show how he sysem performance of mobile erminals can be furher increased wih parallelizaion of he operaions. A virual prooyping approach is used for simulaion and measuremens of a mobile phone plaform [] [8]. Wih is high simulaion speeds and sill saisfacory accuracy, i offers he necessary amoun of absracion for performance analyses on sysem level. This paper is organized as follows: In secion II he model of he mobile phone plaform and he sofware sack are described. A deailed insigh ino he conroller and he parallelizaion echniques is given in secion III. The comparison of differen hardware acceleraion conceps for he proocol sack processing is presened in secion IV. In secion V he simulaion seup and he resuls are presened leading o he conclusion in secion VI. II. SYSTEM ARCHITECTURE The inegraion and evaluaion of differen hardware acceleraion conceps for he LTE proocol sack is carried ou in his work wih a virual prooype of a mobile phone. Is sysem archiecure is depiced in Fig. and consiss of a cycle approximae model of a hardware plaform which is simulaed ogeher wih he execued sofware sack in he CoMET virual prooyping environmen provided by Synopsys [9]. A. Hardware Plaform The core of he hardware plaform is an ARM76 embedded processor [] represening a common choice for sae-of-he-ar mobile devices []. I provides 6-bi and -bi AMBA AXI bus inerfaces [] connecing o he insrucion and daa buses and a peripheral bus, respecively. Differen memory ypes are uilized in he hardware plaform, a small on-chip memory wih fas access imes and a large off-chip memory wih higher laencies []. Because of he high amoun of daa which needs o be ransferred in LTE beween he memory and he physical inerface, he proocol sack is execued from he off-chip memory. In order o enable a realisic simulaion of LTE ransmissions for uplink (UL) and downlink (DL) direcions in he closed virual prooyping

2 Fig.. Sysem archiecure of he ARM76 based virual prooype of a mobile phone showing he hardware plaform and he sofware sack environmen, he physical layer and base saion funcionaliy are modeled by he configurable enodeb/l peripheral. Thereby, ransmied or received daa is generaed or processed a differen daa raes and channel condiions on ranspor block level []. Moreover, he hardware plaform conains a general purpose inerrup conroller aached o all sysem inerrup lines, a imer which esablishes a ime base for he scheduler in he real-ime operaing sysem and wo user inerfaces: a UART conneced o an emulaed console for exual ineracion and a display driven by an LCD conroller for graphical oupus. The componens in focus of his work are he hardware acceleraors for he L proocol sack processing. On he one hand we use a sand-alone de-/ciphering uni () supporing he encrypion algorihms specified by he GPP [] for LTE sysems. I represens a convenional hardware acceleraion approach wih an inernal daa buffer and an inerrup signaling he processing compleion [6]. On he oher hand, an on-he-fly hardware acceleraion concep is realized wih he smar DMA () conroller. The de-/ciphering funcionaliy is herefore inegraed in he DMA conroller and he DMA engine is exended by conrol and compuaional unis for header decoding in downlink and descripor processing in uplink direcions. B. Sofware Sack In order o mee real-ime requiremens in proocol sack implemenaions, he underlying operaing sysem should feaure fas inerrup handling and low ask swiching laencies. Therefore, he sofware sack is based on he open source real-ime operaing sysem FreeRTOS in he curren version 6.. [7]. Is kernel suppors asks and co-rouines whereas queues, semaphores and muexes allow for iner ask communicaion and synchronizaion. In our seup, he kernel is configured for preempive mode enabling ask inerrupion. This is mandaory for he proocol sack execuion where high prioriy asks are acivaed for insance by incoming ranspor blocks. The LTE L proocol sack model implemens he mos complex and compuaional inensive funcionaliy of he daa plane [8]. Furhermore, he downlink and uplink subcomponens are subdivided each in only hree differen asks corresponding o he sublayers Medium Access Conrol (), Radio Link Conrol () and Packe Daa Convergence Proocol () specified by he GPP [9]. A lower number of asks reduces he oal ask swiching overhead in he real-ime kernel. Video daa is generaed by a video applicaion and is send via he proocol sack o he emulaed base saion in uplink direcion. Insead, received ranspor blocks conaining video daa are processed in downlink direcion and forwarded o he video applicaion which uilizes he LCD conroller o play he video sream. In a realisic scenario, he proocol sack execuion can be negaively affeced by oher applicaions running in parallel, for example by clearing he caches in he processor. We emulae such an behavior by execuing a dhrysone benchmark permanenly in parallel o all oher asks in he sysem. III. SMART DMA (SDMA) CONTROLLER A convenional DMA engine is combined in he conroller wih processing unis for he LTE L proocol sack. This enables on-he-fly hardware acceleraion applied direcly during ranspor block ransfers beween he physical layer inerface and he memory. In he following he exended engine and parallelizaion sraegies for on-he-fly hardware acceleraion are described in deail. A. Engine The key componen of he conroller is he exended daa move engine depiced in Fig.. In he normal mode of operaion wih deacivaed and bypassed hardware acceleraors for a DMA channel, buffered read and wrie reques are issued on he bus inerfaces whereas he daa available in he read buffer is moved direcly o he wrie inerface. This echnique is used o perform processor independen copy operaions beween memory regions specified by source and desinaion addresses. Thus, a reducion of he CPU load and faser copy operaions by employing burs ransfers especially for big daa sizes are achieved. Addiionally, he conroller can be configured for hardware acceleraion accomplished during daa ransfers (on-he-fly) of LTE ranspor blocks from or o he physical layer inerface in DL and UL direcions, respecively. On-he-fly acceleraed processing in UL direcion sars wih reading descripors for proocol daa unis (PDUs) and PDUs, which are conained in a ranspor block, and soring hem in he inernal descripor buffer. The conroller is capable of reading he descripors from a coninuous memory region and processing descripors organized in a linked lis as well. In order o perform on-he-fly ciphering of he packes locaed in he ranspor block, he descripor daa is evaluaed by he corresponding uplink processing uni which generaes conrol informaion for he iniializaion and

3 Daa Move Engine Channel Daa Header Decoding Header Decoding Header Decoding Daa Conrol Daa Uplink Processing De-/Ciphering Read Conrol Hardware Acceleraor Conrol Bus Inerface Fig.. Exended daa move engine in he conroller wih uplink and downlink hardware acceleraors and conrol unis acivaion of he de-/ciphering core. Every PDU has a unique sequence number and an associaed hyper frame number required for individual iniializaion of he encrypion algorihms. Furhermore, ciphering is no necessarily applied on enire packes which requires addiional informaion in he form of an address offse referenced o he packe sar address in he memory. A mach beween he curren address offse calculaed by he buffer conrol uni and obained from he UL descripor processing uni riggers a signal which acivaes he on-he-fly de-/ciphering uni. The encrypion algorihms are hen applied on all he daa moved from he read o he wrie inerface. In case of an empy read buffer he de-/ciphering uni is suspended and reacivaed when daa becomes available. In conras o he UL mode, he informaion required for on-he-fly hardware acceleraion in DL direcion needs o be exraced direcly from he ranspor block daa copied from he physical layer inerface o he memory for furher sofware processing by he proocol sack. Therefore, he header decoding unis for he differen L sublayers are acivaed saring wih he header decoder. The exraced informaion is sored in he descripor buffer and riggers in combinaion wih he informaion from he buffer conrol uni an enable signal for he header decoder which in urn acivaes he following header decoder in he same way. An incomplee header in he read buffer which is idenified by he amoun of remaining daa in he read buffer and he conrol informaion from he corresponding header decoding uni requires o hal he header processing and wai for he reacivaion riggered by he nex read burs. Afer successful compleion of he header decoding, he de-/ciphering uni is iniialized and performs on-he-fly deciphering for every no segmened PDU locaed in he ranspor block. Finally, he decoded header informaion from he descripor buffer is copied afer compleion of he ranspor block ransfer o preconfigured memory regions for each sublayer and furher access by he proocol sack. B. Parallelizaion On archiecural level, performance opimizaions are carried ou basically by minimizing he criical pah and hus increasing he frequency. Furhermore, a higher daa hroughpu can be achieved by pipelining and/or hardware parallelizaion. These opimizaion echniques only have direc impac on he iming of separae processing unis like hose inside of he conroller. In fac, on sysem level his is modeled wih parameers ha are configured before simulaion. However, sysem level simulaions are mandaory for invesigaions of more absrac performance opimizaion approaches for peripherals whose processing imes are influenced by he ineracion wih oher componens in he hardware plaform. For insance, he iming for on-he-fly hardware acceleraion wih he conroller depends among ohers on he read and wrie laencies from/o memory regions and on he curren bus uilizaion. The performance of on-he-fly acceleraed ranspor block processing in boh ransmission direcions can be increased by implemening separae bus maser read and wrie inerfaces and running hem in parallel. Thereby, according o our seup a speedup can be achieved only by using differen Read HwA Processing Fig.. Theoreical view on he iming characerisics during on-he-fly hardware acceleraion wih he conroller: sequenial mode wih one bus maser inerface parallel mode wih wo bus maser inerfaces

4 Processing Direcion Header Header Header Payload Header Header Payload Fig.. Timing characerisics of he descripor wrie operaions during on-he-fly hardware acceleraion wih he conroller in downlink direcion: sequenial mode where he descripors are wrien afer he ranspor block processing parallel mode wih an addiional bus maser inerface and descripor wrie operaions during ranspor block processing busses conneced o he physical layer inerface and memories. Oherwise he concurren read and wrie requess on he same bus would block each oher which in urn represens he mode wih one bus maser inerface. A heoreical comparison of he iming characerisics in he sequenial mode wih one bus maser inerface and he parallel mode by uilizing wo bus maser inerfaces is illusraed in Fig.. We assume he same imings for he read and wrie burss and he processing in he hardware acceleraors. In he sequenial mode, a wrie burs reques is issued on he bus afer compleion of he read burs and he following processing in he hardware acceleraors. The processing ime is reduced in he parallel mode because of is capabiliy o issue he wrie and he nex read burss simulaneously. The iming required by he conroller for on-he-fly hardware acceleraion in DL direcion can be furher reduced by parallelizing he descripor wrie operaions (c.f. Fig. ). Therefore, an addiional bus maser inerface is necessary. In order o show he iming characerisics in sequenial and parallel modes, an exemplary ranspor block, which comprises wo PDUs wih an arbirary number of PDUs, is used. I sars wih a header, followed by he PDUs. Every PDU consiss of an header and he payload which is represened by an arbirary number of PDUs consising of a header and a payload as well. When applying he sequenial mode, he decoded header informaion in he form of descripor daa is wrien o he specified memory regions afer he compleion of he ranspor block processing. In he parallel mode, descripor wrie operaions are riggered direcly afer he corresponding header decoder finishes is compuaions. Because all PDUs conained in a PDU are combined in one descripor, he decoded header parameers are wrien o he memory afer he processing compleion of an enire PDU. IV. HARDWARE ACCELERATION CONCEPTS Differen hardware acceleraion conceps for he LTE L proocol sack processing are evaluaed in his work wih regard o heir performance measured on sysem level. The approaches are presened separaely for he UL and he DL ransmission direcions. A. Uplink Transpor blocks which are ransmied in UL direcion over a wireless link are processed in he LTE L saring in he sublayer. Thereby, he payload of every PDU needs o be encryped by applying he ciphering algorihms before he packes can be forwarded o he subcomponen. All logical channel daa from he sublayer is combined in he sublayer o a ranspor block which is hen copied o he physical layer inerface. When he convenional hardware acceleraor is used, he payload of every PDU is moved by a DMA copy operaion beween he memory and he sand-alone de-/ciphering uni which encryps he daa (c.f. Fig. ). In he on-he-fly hardware acceleraion mode wih he conroller, he PDU payload is direcly encryped during he ranspor block ransfer from he memory o he physical layer inerface. Hence, he ranspor block daa needs only o be copied once in conras o he convenional approach. In order o perform on-he-fly hardware acceleraion, necessary proocol sack informaion in he form of descripors can be read and evaluaed by he conroller in wo differen ways. On he one hand, addiional effor in he sofware sack is avoided by using he proocol sack descripor forma. The hen processes descripors organized in a linked lis provided by he and he sublayers. The drawbacks in he conroller are a more sophisicaed read mechanism for he linked liss and an overhead due o unused descripor daa. The proocol sack mainains a lo of differen parameers in a packe descripor which are no all required by he conroller for on-he-fly hardware acceleraion. In he second mode, an specific and opimized descripor wih removed redundancy is generaed by he proocol sack in a coninuous memory region. This addiional complexiy in he sofware sack is compensaed in he conroller wih a simplified read mechanism and faser descripor read operaions. B. Downlink The comparison beween he convenional and he on-he-fly hardware acceleraion approaches in downlink direcion is given in Fig. 6. Received LTE daa is copied in he form

5 Sofware Processing Hardware Processing Sofware Processing Hardware Processing c) Generaion Transpor Block Daa Daa Transpor Block Daa Daa Fig.. Hardware acceleraion conceps for he LTE L uplink: convenional wih a sand-alone hardware acceleraor on-he-fly wih conroller by using he proocol sack descripor forma c) on-he-fly wih conroller by using an opimized descripor forma Fig. 6. Hardware acceleraion conceps for he LTE L downlink: convenional wih a sand-alone hardware acceleraor on-he-fly wih conroller of ranspor blocks from he physical layer inerface o he memory for processing by higher proocol sack layers. Before all PDUs locaed in he ranspor block can be exraced and deciphered in he sublayer, he, and headers are sequenially decoded and evaluaed. Deciphering wih he convenional hardware acceleraor is accomplished on level where encryped daa is copied from he memory o he sand-alone de-/ciphering uni. Afer he compleion signaled by an inerrup, he decryped daa is ransferred back o he memory. In conras, on-he-fly hardware acceleraion including deciphering akes place direcly during copying he ranspor block daa from he physical layer inerface o he memory. Furhermore, necessary header informaion exraced by he header decoding unis in he conroller is wrien in he proocol sack descripor forma o he specified memory regions for access by he, and sublayers. Consequenly, he processing complexiy and execuion imes in he proocol sack are furher reduced by omiing he header decoding funcionaliy in sofware. V. RESULTS All parameers conrolling he sysem behavior of he mobile phone plaform are se in a global configuraion file in he virual prooyping environmen before simulaion and measuremen. We use clock frequencies of MHz and Mhz on he ARM76 processor and he bus sysem, respecively. According o [], his is a reasonable seing for LTE mobile phones. Moreover, he core is configured wih daa and insrucion cache sizes of kb. Invesigaions have shown, ha an increase of he cache sizes leads only o marginal performance improvemens []. The sand-alone and he inegraed de-/ciphering uni in he conroller use boh an equal iming configuraion of ns per bye for encrypion and decrypion. This is he maximum performance value derived from hardware implemenaions presened in []. Addiionally, he header decoding unis in he conroller work wih a iming of one cycle per bye. This assumpion is jusified by he fac ha he exracion of header informaion from dedicaed bi fields does no require inensive calculaions. The processing imes in he proocol sack are measured for differen ranspor block sizes generaed by he enodeb/l peripheral (DL) and by he proocol sack (UL). Wih he ransmission ime inerval of ms in LTE, he variaion beween kbi and Mbi corresponds o daa raes of Mbi/s and Gbi/s, respecively. All processing imes presened in his work are derived by calculaing he average value from measuremens. The average processing imes per ranspor block of he LTE L UL for differen hardware acceleraion conceps are depiced in Fig. 7. The convenional hardware acceleraion approach () is compared o differen UL on-he-fly hardware acceleraion modes in he conroller by using he proocol sack descripor forma ( UL) and an opimized descripor forma ( UL). Addiionally, he conroller operaes firs in a sequenial and second in a parallel mode wih wo bus maser inerfaces. As expeced, he processing imes are srongly increasing wih he daa raes. I becomes clear ha all on-he-fly hardware acceleraion conceps are significanly ouperforming he convenional

6 9 6,799,87696, ,8,69,,976 7, ,7979 6,889 6,7,899 6,7,69 6, ,698 7,89797,99 9,8876, , 6,87 6,669 6,8968 9, ,687 6,7888 7,988 6,77 6,999 6,7 9,8796 7,788 9, ,78 7,79, ,969,766,7777,8688,9979 6, ,9 6,686,879,896 6,868 9, , ,97,669,789 6, ,9979 6,76 6, ,8 6,68 6,677 6,7668 6,7766 6,996 8,9986,86687,997,97 8 6,7 6,8979, 7, ,796 7,9,6 6,669 6, ,687 9,8887 6,999 6, ,8796 9,787 76,78 6, G Speedup 9,9796,799 6,76,98877,9,69 7,868, ,686 7,796,899,76 7, , ,79, ,9979 6, ,68 6,7668 6,996,79,969,7777,9979 6,8979,879 6,796 6,868,669 6, ,8887 6, ,787 6, AVG Speedup,9796 6,76,9 7,868 7,796,76 8, conv. 8 Processing HwA Times ArmClock@ MHz Processing conv. Times HwA ArmClock@ MHz, Process UL UL DL conv. UL,parallel HwA, UL 8, 6 UL UL DL,parallel UL UL 7 DL UL,parallel UL,parallel,, DL,parallel UL 6 DL,parallel UL UL UL,parallel, DL,parallel,,,, Daa Rae in Mbi/s Daa Rae in Mbi/s Daa Rae in Mbi/s Daa Rae in Mbi/s Average Processing Time in ms Average Processing Time in ms Processing Times ArmClock@ MHz Fig. 7. Average processing imes per ranspor block of he LTE L UL proocol sack model Speedup for differen ArmClock@Mhz hardware acceleraion modes Speedup ArmClock@Mhz UL UL,parallel UL UL UL,parallel UL,parallel UL UL,parallel Daa Rae in Mbi/s Daa Rae in Mbi/s Average Average Processing Processing Time in Time ms in ms Speedup in % s Processing Process Times ArmClock@ MHz Fig. 9. Average processing imes per ranspor block of he LTE L DL proocol sack model for differen hardware acceleraion modes 6 6 Speedup Speed ArmClock@Mhz Speedup Speed ArmClock@Mhz UL UL UL,parallel UL,parallel DL DL DL,parallel DL,parallel DL,parallel DL,parallel Daa Rae in 6 Mbi/s Daa Rae in Mbi/s Fig. 8. Relaive speedup of he LTE L UL processing for differen hardware amode acceleraion UL,parallel modes in he UL,parallel conroller DL,parallel in comparison DL,parallel o a convenional i/shwamode hardware acceleraion UL,parallel concep UL,parallel DL,parallel DL,parallel Mbi/s 7,8967 8, ,998,997 7,8967 8, ,998,997 hardware acceleraor for all ransmission condiions. A more deailed diagram showing he relaive speedups achieved wih on-he-fly hardware acceleraion in UL direcion compared o he convenional approach is given in Fig. 8. The speedup is decreasing wih higher daa raes for all configuraions and ranges a mos beween 7 % and % ( UL, parallel). The reason is ha he descripor processing complexiy grows faser wih increased daa raes han he processing of he ranspor block daa resuling in a reduced performance gain. Compared o he UL hardware acceleraion concep, he UL approach is up o % faser in he sequenial as well as in he parallel mode. Even higher speedups are achieved by on-he-fly hardware acceleraion in DL direcion compared o he convenional approach (c.f. Fig. 9 and Fig. ). In addiion o he sequenial mode, he acceleraed processing imes are measured for he parallel mode wih wo bus maser inerfaces (parallel) and he full parallelizaion wih an exra bus maser inerface and concurrenly running descripor wrie operaions (parallel). The header informaion is direcly decoded in he conroller in conras o he UL mode where firs descripors generaed by he proocol sack need o be read and evaluaed. Hence, a higher maximum performance gain of abou 66 % ( DL, parallel) is reached for DL on-he-fly hardware acceleraion whereas he speedup is increasing wih growing daa raes. Fig.. Relaive speedup of he LTE L DL processing for differen hardware acceleraion modes in he conroller in comparison o a convenional hardware acceleraion concep In order o analyze he effeciveness of he parallelizaion echniques in comparison o he sequenial modes in he conroller, he relaive performance improvemen of he processing 6,7688 imes during 9,6777 on-he-fly 9,69697 hardware,6896 acceleraion,896,6798 9,6787,79 is depiced,9767 in Fig..,68779 By implemening 9,967986an addiional,99 bus,76,99 9,98, maser inerface in he conroller for parallel read and 6,66,77877,898,99 wrie, 7 he, processing,8678 ime can be,7969 reduced by,768 up o 9 % 8,6667,8889,8,96 and up o % for he UL and DL modes, respecively. A 9,889,7796,8,869 higher daa,8 raes, wih,8878 more effor for,97698 he descripor,86996 read and processing,99 where parallelizaion,77 has no 9,8677 effec in,687 UL direcion, he speedup is degraded o approximaely %. In conras, he 8 6 Diagrammiel Daa Rae in Mbi/s UL,parallel UL,parallel DL,parallel DL,parallel Fig.. Relaive speedup of he processing imes achieved by parallelizaion conceps for on-he-fly hardware acceleraion in uplink and downlink direcions

7 DL speedup is almos consan and can be furher improved ( %) by applying he parallel descripor wrie mode. VI. CONCLUSION In his paper we presen differen on-he-fly hardware acceleraion conceps for uplink (UL) and downlink (DL) LTE proocol sack processing based on a smar DMA () conroller for mobile erminals. Moreover, by applying parallelizaion echniques, we show how he efficiency of he conroller is improved. We invesigae he performance on sysem level by comparing he processing imes o hose achieved wih a convenional hardware acceleraor. Therefore, a cycle approximae virual prooype of a mobile phone consising of an emulaed hardware plaform and he sofware sack is simulaed wih LTE-Advanced daa raes of up o Gbi/s in boh ransmission direcions. Bes performance is offered in UL direcion wih he conroller in he opimized descripor mode. More compuaional effor in he proocol sack is compensaed wih less complexiy and hus faser processing in he hardware acceleraor. Consequenly, his is he preferred mode for on-he-fly hardware acceleraion in UL direcion. Furhermore, by incremening he number of bus inerfaces and parallelizing he ransfers we reduce he processing imes by up o %. Considering a full uilizaion of he conroller also by oher applicaions in he mobile erminal issuing convenional DMA ransfers, he whole sysem performance is equally improved. On-he-fly hardware acceleraion has a clear benefi compared o he convenional hardware acceleraion approach wih maximum speedups of up o % and 66 % in UL and DL direcions, respecively. Simulaneously, he adopion of he conroller significanly reduces he number of daa ransfers leading o a reduced uilizaion of he bus archiecure. Since he overall power consumpion in embedded sysems considerably depends on he bus communicaion [], we assume ha a noiceable decrease can be reached wih our on-he-fly hardware acceleraion approach. We show ha he conroller wih is high performance and relaive low complexiy represens an efficien hardware acceleraor for LTE erminals. ACKNOWLEDGMENT The auhors acknowledge he excellen cooperaion wih all projec parners wihin he EASY-C projec and he suppor by he German Federal Minisry of Science and Educaion (BMBF). Furher informaion is available on he projec websie: hp:// [] M. Ouellee, D. Connors, Analysis of Hardware Acceleraion in Reconfigurable Embedded Sysems, in 9h IEEE Inernaional Parallel and Disribued Processing Symposium (IPDPS ), Denver, Colorado, USA, pp. 68a-68a, April [] D. Szczesny, S. Hessel, F. Bruns and A. Bilgic, On-he-fly Hardware Acceleraion for Proocol Sack Processing in Nex Generaion Mobile Devices, in 7h Inernaional Conference on Hardware/Sofware Codesign and Sysem Synhesis (CODES+ISSS 9), Grenoble, France, pp. -6, Ocober 9 [] J. Cockx, Efficien Modeling of Preempion in a Virual Prooype, in h Inernaional Workshop on Rapid Sysem Prooyping (RSP ), Paris, France, pp. -9, June [6] S. Schliecker, J.-C. Braam, S. Sein and M. Schnieringer, Whie Paper: Sofware Driven Embedded Sysems Design [7] T. Eckar and M. Schnieringer, Developmen and Verificaion of Embedded Firmware using Virual Sysem Prooypes, in Inernaional Symposium on Sysem-on-Chip (SoC 6), Tampere, Finland, pp. -, November 6 [8] M. Brandenburg, A. Schollhorn, S. Heinen, J. Eckmüller and T. Eckar, From Algorihm o Firs.G Call in Record Time - A Novel Sysem Design Approach Based on Virual Prooyping and is Consequences for Inerdisciplinary Sysem Design Teams, in Design, Auomaion & Tes Conference (DATE 7), Nice, France, pp. -, April 7 [9] Synopsys, Inc., hp:// [] ARM76JZF-S Processor Technical Reference Manual, ARM Limied, Li.-Nr.: ARM DDI F, 8 [] S. Hessel, F. Bruns, A. Bilgic, A. Lackorzynski, H. Härig and J. Hausner, Acceleraion of he L/Fiasco Microkernel Using Scrachpad Memory, in Inernaional Workshop on Virualizaion in Mobile Compuing (MobiVir 8), Breckenridge,pp. 6-, USA, June 8. [] AMBA AXI Proocol, ARM Limied,Li.-Nr.: ARM IHI B,, hp:// [] P. R. Panda, N. D. Du, and A. Nicolau, On-chip vs. off-chip memory: he daa pariioning problem in embedded processor-based sysems ACM Transacions on Design Auomaion of Elecronic Sysems (TO- DAES), Volume, Issue, July [] D. Szczesny, A. Showk, S. Hessel, U. Hildebrand, V. Frascolla and A. Bilgic, Performance Analysis of LTE Proocol Processing on an ARM based Mobile Plaform, acceped for h Inernaional Symposium on Sysem-on-Chip (SoC 9), Tampere, Finland, Ocober 9 [] GPP Sysem Archiecure Evoluion (SAE): Securiy Archiecure, GPP Sd. TS., Rev. 8.., Dec. 8. [6] Olli Silven and Kari Jyrkkä, Observaions on Power-Efficiency Trends in Mobile Communicaion Devices, in EURASIP Journal on Embedded Sysems, Volume 7, ISSN:687-9, January 7. [7] FreeRTOS, hp:// [8] D. Szczesny, A. Showk, S. Hessel, U. Hildebrand, V. Frascolla and A. Bilgic, Join Uplink and Downlink Performance Profiling of LTE Proocol Processing on a Mobile Plaform, o appear in Inernaional Journal of Embedded and Real-Time Communicaion Sysems (IJERTCS), [9] The rd Generaion Parnership Projec (GPP), hp:// [] van Berkel, C.H., Muli-core for mobile phones, in Design, Auomaion & Tes in Europe Conference (DATE 9),Nice,France, pp.6-6, April 9 [] S. Hessel, D. Szczesny, N. Lohmann, J.Hausner and A. Bilgic, Implemenaion and Benchmarking of Hardware Acceleraors for Ciphering in LTE Terminals, submied in IEEE Global Communicaions Conference (GLOBECOM 9), Honolulu, Hawaii, USA, November 9. [] C. Talarico, J.W. Rozenbli, V. Malhora and A. Srier, A New Framework for Power Esimaion of Embedded Sysems, in Compuer Volume 8, pp. 7-78, February REFERENCES [] J. Berkmann, C. Carbonelli, F. Dierich, C. Drewes and Wen Xu, On G LTE Terminal Implemenaion - Sandard, Algorihms, Complexiies and Challenges, in Inernaional Wireless Communicaions and Mobile Compuing Conference 8 (IWCMC 8), Cree Island, Greece, pp , Augus 8 [] Greg Si, Roman Lysecky and Frank Vahid, Dynamic Hardware/Sofware Pariioning: A FirsApproach, in Proceedings of he h Design Auomaion Conference (DAC ), Anaheim, California, USA, pp. -, June