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1 Course:CS493- Computer Architecture Lab PROGRAMME: COMPUTERSCIENCE&ENGINEERING DEGREE:B. TECH COURSE: Computer Architecture Lab SEMESTER: 4 CREDITS: 2 COURSECODE: CS493 COURSE TYPE: Practical COURSE AREA/DOMAIN: Programming, Computer Architecture CONTACT HOURS: 3 (weekly) CORRESPONDINGL ABCOURSE CODE (IFANY): LAB NAME: Computer Architecture, XLINX Lab Course pre-requisites CODE COURSE NAME DESCRIPTION SEM CS201 Basic Computation & Principles of Computer Programming Programming skills II CS302 Data structures and algorithms Concepts of different data structures III CS303 Computer Organisation The components of a computer system III CS393 Computer Organisation Lab Designing various circuits with ICs III CS301 Analog and Digital Electronics Concepts of various gates and ICs III CS391 Analog and Digital Electronics Lab Designing various circuits with ICs III Course Objectives 1. Simulate digital circuit design using XLINX tool Course Outcomes 1. Practical experience on Xlinx Programme Outcomes addressed in this course a. An ability to apply knowledge of mathematics, science, and engineering b. An ability to use Xlinx tool Department of CSE Page 1
2 Syllabus All laboratory assignments are based on Hardware Description Language (VHDL or Verilog) Simulation. [Pre-requisite: The hardware based design has been done in the Analog & Digital Electronics laboratory and Computer Organisation laboratory] 1. HDL introduction 2. Basic digital logic base programming with HDL 3. 8-bit Addition, Multiplication, Division 4. 8-bit Register design 5. Memory unit design and perform memory operatons bit simple ALU design 7. 8-bit simple CPU design 8. Interfacing of CPU and Memory Gaps in the syllabus to meet industry/profession requirements PROPOSED PO ACTIONS MAPPING 1 Parallel Computing Extra Class a. Topics beyond syllabus/advanced topics DESCRIPTION HOURS 1 Parallel Computing, SISD, SIMD. 3 2 Burning programs in FPGA 6 Web Source References URL 1 Delivery/Instructional Methodologies DESCRIPTION 1 Chalk and Talk Department of CSE Page 2
3 2 Study Material, PPT 3 Desktop 4 Power Point Presentation Assessment Methodologies DESCRIPTION TYPE 1 Student Assignment. Direct 2 Tests Direct 3 University Examination Direct 4 Student Feedback Indirect Course Plan Assignment Week 1 1. Write a program to add two 8 bit number (A+B=RESULT with a carry and without a carry). 2. Write a program to subtract one 8 bit number from another (A-B=RESULT with a borrow and without a borrow). 3. Write a program to find out AND, OR, NOT, XOR, NAND, NOR, XNOR of two 8 bit number. Week 2 1. Write a program to find out addition of two 16 bit numbers. 2. Write a program to find out subtraction of two 16 bit numbers. Department of CSE Page 3
4 3. Calculate 2 s complement of the contents of two successive memories 8050 and 8051 which contain C9 and 86 respectively and then store them in location 9070 and For each of the following experiment a. Create VHDL code and Test Bench Waveform b. View and realize the RTL Schematic diagram c. View and realize the technology schematic diagram. d. Simulate the result using Xilinx ISE simulator e. View the truth table and K-map. Week 3 1. Implement the logic gates (AND, OR, XOR, NOT, NAND, NOR, XNOR) in VHDL using Data Flow 2. Implement the same using Behavioral architecture. Week 4 1. Design and implement the Half Adder circuit in VHDL using Data Flow and Behavioral 2. Design and implement Full Adder circuit in VHDL using Data Flow and Behavioral Week 5 Do the following using Data Flow Architecture 1. Design and implement a 2:1 MUX. 2. Design and implement a 4:1 MUX. Do the following using Behavioral Architecture 3. Design and implement a 2:1 MUX. 4. Design and implement a 4:1 MUX. Week 6 Department of CSE Page 4
5 1. Design and implement a Decoder (2X4) and Encoder (4X2) using Behavioral 2. Do the same using Data Flow 3. Design and implement 8 bit multiplication/division circuit using Data Flow Week 7 Do the following using Structural Architecture 1. Design and implement a 4:1 MUX using two 2:1 MUX. 2. Design and implement a 4:1 MUX using two 2:1 MUX. 3. Design and implement a full adder using two half adder. Week 8 1. Design and implement T, D and SR Flip Flop in VHDL using Behavioral architecture. Week 9 1. Design and implement a shift registers(4 bits) using Data Flow architecture. 2. Do the same using Structural architecture Week Design and implement different counters(4 bits) using Data Flow architecture 2. Do the same using Structural architecture Week Design and implement an ALU (8 bit) using Data Flow architecture. Department of CSE Page 5
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