Predicting Die-level Process Variations from Wafer Test Data for Analog Devices: A Feasibility Study

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1 Predctng De-level Process Varatons from Wafer Test Data for Analog Devces: A Feasblty Study S. Devarakondl, J. McCol, A.Nahar, J.M.Carull Jr., S. Bhattacharya and A.Chatterjeel Georga nsttute of Techno}ogy, Atlanta, Texas nstruments, Dallas shyam@ece.gatech.edu, chat@ece.gatech.edu Abstract- A methodology to predct the process e-test parameters correspondng to each de (even n regons of the de where e-test structures are not avalable) from de test measurements for analog/rf systems s developed. The methodology provdes dagnoss of process varatons wth hgher spatal resoluton n volume manufacturng over other technques due to the avalablty of manufacturng test data at every de ste on the wafer as opposed to measurements of e test parameters at only specfc wafer locatons. Manufacturng test data for each de s mapped to spatally nterpolated e-test data usng regresson analyss tools. The resultng mappng functon can be used to predct the mplct e-test parameter values for each de from ts manufacturng test measurements. n addton, the proposed methodology provdes gudance regardng whch e-test parameters need to be controlled more accurately n comparson to other parameters for hgh devce yeld (.e. the crtcal e-test parameters). Data collected from 4 dfferent lots and 08 wafers for an analog devce currently n producton was used to demonstrate the proposed concept and feasblty of the proposed methodology for dentfyng the crtcal e-test parameters s presented. Keywords- De-level process varatons, Analog/RF, Spatal nterpolaton, Regresson, E-test parameters, Yeld. NTRODUCTON Wth shorter tme-to-market cycles, yeld enttlement s a crtcal parameter for commercal success of current semconductor devces. n the case of analog/rf crcuts mplemented n advanced nanometer nodes, attanng hgh yeld s a challenge. Ths s because the mpact of process varatons on these crcuts s hghly mult-dmensonal n comparson to ther dgtal counterparts, and no generc tools exst for mplementng DFM and DFY methodologes []. Current state-of-the-art has two lnes of defense that determne the overall yeld of the devce. These lnes of defense are the fab process lmts and test specfcatons lmt. Whle testng the devce, varous specfcatons of devces are checked aganst ther respectve lmts to determne f the devce has passed or faled. At the fabrcaton level, a number of statstcal process control methods are used to montor ndvdual process e-test parameters (also called e-test parameters). Tradtonally, the fab montors a large gamut of e-test parameters based on the process technology that s beng used. These parameters are montored through undmensonal control charts where each e-test parameter s expected to be wthn an upper control lmt (UCL) and a lower control lmt (LCL). Whle test and fab checkponts exst, each of these operates ndependently. The problem wth the exstng technque s that t does not take nto account the senstvty of a partcular process e-test parameter to that of a test specfcaton. There s no method to dentfy the parameters that are crtcal for the yeld of a crcut (especally for a fabrcaton engneer) wthout performng ntensve crcut-level smulatons. Further, t has been shown n pror lterature [] [3] that not all parameters affect the devce and the dmensonalty of the process/e-test parameters can be reduced. As technology nodes scale (especally below 45 nm), dependng on the desgn and mplementaton of the crcut, there s a greater need to control dfferent process parameters n a selectve manner. n the past, numerous technques were developed for the purpose of dagnoss and process control montorng. Parametrc test measurements for zero-yeld wafers are used to obtan process parameters [4]. Dagnoss of process ntegraton errors has been studed usng data mnng [5] as well as neural-network technques [6]. Pelgrom models have been used tradtonally, to determne the process varatons n a group of transstors [7].Whle these are commonly used n desgn PDK, they are not accurate enough for larger dmensons. n [8], the authors dscuss condtons for performng fault dagnoss n analog crcuts usng behavoral models and senstvty analyss. A methodology for dagnosng crtcal process/crcut parameter values from dagnostc test/performance measurements (generated from specfc measurements at crtcal nodes of the crcuts) usng reverse soluton of forward regresson models (mappng process/crcut parameters to the test measurements) was developed n [9]. n [], authors dscuss a technque for predcton of Spce-level parameters and DUT specfcatons on a per-chp bass from specally crafted test stmulus response. The authors dscuss an effcent algorthm for the development of the test stmulus, and use the predcted specfcaton and Spce-level parameters to perform a causeeffect analyss. Whle ths technque s effectve, test development on present day complex analogrf SoCs would be tme consumng and computatonal expensve. As a result, n ths paper, a methodology s proposed where the regresson s developed usng back-end data rather than n smulaton envronment. n [0], a technque called nearest neghborhood resdual s mplemented on DDQ tests to help better dentfy outlers. Numerous other technques for defects and outlers have been dscussed n lterature. However, the focus of ths paper s not to deal wth outlers, but to develop a framework by whch a hgh resoluton map of crtcal process parameters that mpact the crcut, can be dentfed. Ths nformaton can be used to detect process shfts and correct for them before the /3/$ EEE

2 .. devces starts to fal. Thus t enables dentfy the hypersurface (unque to each crcut) n whch the parameters that mpact the crcut, need to le for the devce to be classfed as pass. t s mportant to note that each analog/rf devce wll have a dfferent set of process e-test parameters that affect the crcut (dependng on ts desgn and mplementaton). To the author's knowledge, such a methodology that helps determnes the process e-test parameters, specfc to a gven crcut, from ts test data has never been showcased n producton platform.. CURRENT PROCESS CONTROL METHODOLOGY Current methodology of process control montorng nvolves measurng process e-test parameters at ether or 9 locatons on each ndvdual wafer n a fab. These e-test parameters are measured usng test structures placed n scrbe lnes (n between the des) n specfc sub-regons of a wafer called photo shots (also called as shots or retcles of the wafer). A hypothetcal shot-map that marks the dfferent shots/stes across the wafer where measurements are made s shown n Fgure. The e-test parameters are measured usng specalzed test structures at a certan lmted number of test shots on each wafer. Each shot s square/rectangular regon composed of des, and test structures that are placed n the scrbe lnes n between the des. As each wafer gves only 9 or measurements, a sgnfcant amount of data needs to be collected across large ntervals of tme (wafers and lots) to account for any determnstc process e-test parameter varaton. Faster feedback can be obtaned usng ncreased number of test structures but at the cost of greater test tme and slcon area. Each test structure measures a partcular e test parameter and the wafer s classfed as a good wafer as long as each e-test parameter les wthn certan lmts. Often there exst hundreds of parameters, and the fab does not have any knowledge of the relatve mportance of the parameters and the lmts wth whch the parameters need to be controlled for a gven crcut. /f"" '" / 5 6 \ \ '\ 8 7 " :h M / E-test structures!.t ' r r De locatons < Scrbe lnes Fgure : Hypothetcal shot-map of the wafer.. ApPROACH/METHODOLOGY n the absence of a catastrophc defect, the varaton of an output response of the DUT depends on ts process parameter vanatlon space (quantfed by e-test parameters measurements). Usng ths knowledge, t follows that from the test measurement data one should be able to obtan nformaton about the process e-test parameters that nfluence the output response of the DUT. Ths s accomplshed usng a regresson model that relates the output measurements {M} to each of the process e-test parameter n {P}. The number of senstve process e-test parameters that can be determned depend on the number of ndependent measurements that span the output measurements space {M}. n producton envronment, dependng on the nature of the devce, a combnaton of probe-level (called Multprobe) and fnal tests that are measured under dfferent test condtons should suffcently consttute the measurement space such that all the process e-test parameters that mpact the crcut can be determned (see Fgure ). The regresson model relatng the e-test parameter and the test measurements can be ntally developed usng the characterzaton or desgn of experment (DOE) wafers where a number of process e-test parameters are vared beyond the normal expected varatons. deally, the process e-test parameters that sgnfcantly nfluence the crcut specfcatons can be determned usng experments such as central composte desgn (CCD) [] n the smulaton envronment. However, ths analyss would be possble at the cost of addtonal computatonal resources and tme. For parameters that are not vared durng the ntal devce characterzaton phase, the regresson mappngs need to be performed usng the ntal wafers produced (we use the latter technque n ths work). deally, there are tens of e-test parameter measurements made on an ndvdual wafer (see Fgure ). Hence, to capture the spatal varaton trends n the presence of nose as well as mssng measurements would requre many measurements over lots. Ths would lead to greater amount of tme to mplement the feedback framework. Alternatvely, there exsts sgnfcant process varaton nformaton on each wafer n the shots where the measurements have not been made. Ths spatal process varaton on each wafer can be obtaned by nterpolatng the exstng e-test parameter measurements to other locatons on the wafer (non-numbered shots n the wafer map shown n Fgure ). Once a hgher resoluton wafer map of the process e-test parameter s obtaned usng the a few wafers of the frst lot, regresson models relatng the test data of the devces and the nterpolated process e-test parameters can be developed (see Fgure ). Please note that spatal nterpolaton of an e-test parameter does not ndcate ts sgnfcance or ts nsgnfcance to the devce. Any parameter that has spatal correlaton can be nterpolated. Hence, t s mportant to develop the regresson model relatng these parameters and the test data for each crcut E-test parameter data Spatal nterpolaton Fab! - Test data (Multprobe and fnal test) Regresson models F(test) = e-test parameter + Regresson functon analyss Fgure : Overvew ofthe proposed methodology. Test floor

3 3 Once the regresson model s developed, usng the test data from dfferent locatons of a wafer, for subsequent wafers, the process e-test parameters at the correspondng locatons can be detennned. The ablty to determne the e-test parameters from test measurements (potentally from every de that has no hard fault) helps n quckly dentfyng any drft occurrng n process parameters. At ths pont, feedback can be provded to the fab to tune the correspondng process parameter before future yeld loss occurs. f the test measurement space s not large enough, then not all of the process e-test parameters that are crtcal for the yeld of the crcut can be determned. However, the technque would stll provde nformaton about sgnfcant process varaton trends n some of the crtcal parameters. t s essental to note that no addtonal step n the current producton cycle s requred to obtan the dagnoss nformaton. The exstng test data from devce and e-test parameter data from scrbe lnes are used to develop the methodology. V. SPATAL NTERPOLATON n ths work, the Vrtual Probe technque developed n [] s used for spatal nterpolaton. The technque apples the prncple of compressed sensng to semconductor e-test parameters to perform wafer-level spatal nterpolaton. n ths technque, t s shown that f an e-test parameter has a hgh amount of spatal correlaton n the X-Y dmenson (Eucldean), then the e-test parameter n the spatal frequency doman (.e. Fourer or Cosne transfonn of the spatal varaton) has a sparse structure wth large number of coeffcents beng small or close to zero. The assumpton of hgh amount of spatal correlaton s true n practce for most process e-test parameters. The e-test parameter, whch needs to be spatally nterpolated, can be expressed as a two dmensonal functon n X-V doman namely [(x,y), where x E [,.... M], y E [,.... N] (see Fgure ) are the coordnates, and [(x, y) s the functon that defmes the varaton of the e-test parameter along the respectve coordnates. f the dscrete cosne transfonn (DCT) of the two dmensonal functon can be stated as F(p, q), where :::; p :::; M, :::; q :::; N, then the correspondng nverse dscrete cosne transfonn (DCT) functon s shown n Equaton. M.. N ( ) rr(x-l) p rr(y-l) q N ' f(x,y) = L p =l L...q =l a p {3 q F p,q cos ----:z;:;-- cos :::; x:::; M, :::; y :::; N, Equaton n Equaton, ap' {3q are the scalng coeffcents. Now consderng that the e-test parameter s beng measured n L locatons (L beng or 9),.e. the values of [(x,y) at these locatons are known. The goal s to use these measurements to fmd [(x, y) at other locatons usng Equaton l. t has been shown n [] that the DCT coeffcents (F(p, q) n Equaton ) are sparse due to the exstence of hgh amount of spatal correlaton across the wafer. By consderng the jont probablty dstrbuton functon (PDF) of all the coeffcents, t has been shown that the DCT coeffcents can be estmated usng Ll-norm regularzaton. The above Ll-nonn regularzaton can be solved usng the least absolute shrnkage and selecton operator (LASSO) algorthm [3]. Once the estmate for the DCT coeffcents s obtaned, usng Equaton, the nterpolated values of the functon [(x, y) can be obtaned. The accuracy of nterpolaton that can be obtaned usng the technque was found to depend on spatal samplng frequency and the amount of spatal correlaton n the process e-test parameter. The reader s asked to refer to the followng references for more detaled explanaton of the technque [][4][5]. V. REGRESSON ANALYSS Whle spatal nterpolaton technque provdes greater number of data ponts for process e-test parameters, to dentfy and predct the set of crtcal e-test parameters that nfluence the crcut, the relatonshp between the test measurements and e-test parameters need to be developed. To determne the e test parameters nvolves the development of the regresson model functons p = [(m) (see Fgure ). n ths step, a methodology called Multvarate Adaptve Regresson Splnes (MARS) s used for regresson functon development [6]. The MARS s a nonparametrc adaptve regresson algorthm that selects a set of bass functons (lnear or hgher order) usng the nput varables and coeffcents for the bass functons to develop a regresson functon. The algorthm uses the concept of recursve parttonng based on the data varatons to develop the model. t nvolves a forward step where the algorthm add bass functons to the model and a backward trmmng phase where bass functons that contrbute mnmum to the least squares ft of the model are removed. The backward phase s performed usng the generalzed cross-valdaton error (GCVE) crteron that balances between over-fttng of data as well as resdual error. A. Sp atal nterpolaton V. DEVCE RESULTS The devce consdered s a SOC mplemented n a 80 nm process that s currently n producton. t has both analog and dgtal components that nclude DC-DC converters, amplfers, ADCs and DACs among other modules. The smulaton envronment used for nterpolaton and regresson analyss s Matlab. Ths secton provdes the expermental valdaton of the spatal nterpolaton technque mplemented. A set of 8 wafers were mplemented wth test structures at all the 70 shots rather than the conventonal or 9 stes/shots/retcle per wafer. Each e-test parameter s measured once n a shot. The choce of (called category A parameters) or nne (called category B parameters) locatons depends on the parameter sgnfcance (nput from the desgner & process engneer based on experence). To use the nterpolaton technque dscussed n Secton, t s necessary to ensure that process e-test parameters have a substantal amount of spatally correlaton across the wafer. Ths s verfed ntally by performng a DCT of all the measured values of parameter at varous ponts n the wafer and ensurng that a large number of DCT coeffcents of the are close to zero ndcatng the exstence of hgh spatal correlaton. Then the conventonal and 9 ste measurements made on every wafer are then used to perform nterpolaton n the remanng stes. The orgnal and nterpolated wafer map of the scaled values of the Nwell sheet resstance parameter s shown n Fgure 3. The relatve error s calculated usng the fonnula shown n Equaton.

4 4 Relatve error {(ex,y) - fex,y))/ fex,y)} = * 00, Equaton where ex,y) s the nterpolated value and fex,y) s the measured value. Table. provdes the relatve error between the measured and nterpolated parameters across all measurements both usng and 9 measurement locatons. The mean of the absolute value of relatve error and the standard devaton of the relatve error at varous locatons and wafers are tabulated n Table. Out of 6 e-test parameters that were used for nterpolaton, 07 parameters could be nterpolated wth less than 5 % relatve error. Whle the basc method of Vrtual Probe has been mplemented here, more advanced versons of ths methodology that take multple wafers of a same lot nto account have been publshed [4][5]. Ths technque dscussed n [4] could ad n provdng nterpolaton results wth greater resoluton. Orgnal (measured at all shots/stes) 0 : 4 nterpolated (usng measurements) n n B Fgure 3: Orgnal and nterpolated scaled e-test wafer maps for Nwell sheet resstance. B. Data Condtonng & Regresson Analyss For the purpose of regresson analyss, data from 79,604 des from 08 wafers across four lots was obtaned. On each wafer, 97 process e-test parameters were measured at stes (category A) and 68 process e-test parameters were measured at nne stes (category B). For each process e-test parameter, measurements were collected across wafers and screened to remove outlers. Ths outler detecton s an mportant step as these outlers sgnfcantly affect the spatal nterpolaton step as well as the regresson functon coeffcents. A nonparametrc nter-quartle range (lqr) technque was used to remove outler observatons. The above data-condtonng step helps n removng spurous data caused due to measurement error and varous other related error sources. n ths study, to valdate the proposed concept, the probelevel test data measured before packagng of the des were used n the regresson analyss. To avod defects, only des that passed all the tests are consdered n the experment. As the resoluton of the process e-test parameter were obtaned at the shotlste/retcle-evel (see Fgure 3), to perform the regresson analyss, the probe-level test measurements of all the pass des n a sngle shot were collected and the medan of all these measurements was calculated. The reason for usng medan of the measurements s ts relatve nsenstvty to outler or extreme measurements. Out of the 347 probe-level test measurements, a number of measurements such as the full scale ADC readng, do not show any dstrbuton over the samples. Only 50% of these measurements showed contnuous dstrbuton and were used 0.6 n developng the regresson analyss. For ths devce, the number process e-test parameters n category A are 97. Smlarly, n category B, there are 68 process e-test parameters measured. For each of the process e-test parameters, regresson functons were developed usng all the contnuous test measurements. For tranng the regresson functons for the e-test parameters, 400 observatons were selected randomly from all the wafers n the frst two lots as well as from wafers of Lot three. A combnaton of the actual and nterpolated e-test parameters were used for tranng. For evaluaton, 0 observatons collected from the three wafers of Lot three not ncluded n the tranng and from all the wafers n Lot four were used. Table. Error n nterpolaton usng or 9 measurements. Parameter Mean absolute percentage error (%) Relatve error standard devaton (%) 9 9 Nwell Sheet resstance Capactance unt PMOS VT PMOS Off current PMOS Drve current Fgure 4 shows the scaled predcton plots for the varous process e-test parameters. As can be seen from the graphs, usng ths technque we can effcently predct the process e test parameters to whch the crcut s senstve. Table shows the error values for some of the process e-test parameters that could be predcted from both category A and B. Along wth the mean of relatve error, the normalzed root mean square (NRMS = RMS Error/ range(parameter)) s calculated. The goodness-of-ft metrc (lnear Pearson correlaton metrc) between the actual and the predcted values s also provded. 4 parameters n category A and 35 parameters n category B were predcted wth ther NRMS values rangng from nne to 0%. Poly sheet resstance (Ohms/sq) Poly hgh sheet resstance (Ohms/sq) 5.0, '6'4.3,-----,! > > 'C 4.90 'C! o o 4.0 :c 4.80 l. 4. 7R ' 4=-=.8;:- O ----:- 4.= '5 =-=.07' = 5."':: 0:--" : 3.';; "'-4.;---4"'.;----,J4.3 '6'-35.8!-36,0 PMOS VT lnear regon (Volts) Parallel plate capactance (ff/um) _45,---- l.. o /) ; a!-36.4 l 35 * o u "t+- : l. 3 f Fgure 4: Scaled predcton plots for process e-test parameters. 45

5 5 The mnmum goodness-of-ft metrc was (for the PMOS VT parameter; the parameter wth worst predcton error). The predcted parameters, whch mpact the crcut, can be controlled n a multdmensonal manner as compared to other parameters for ensurng hgh yeld of the devce. Table. Predcton error n crtcal e-test parameters Parameter NRMSE Relatve Goodnes (%) error (%) s-of-ft PMOS drve current Parallel plate capactance Poly sheet resstance parameters that can be predcted can be ncreased further by usng the post-packagng [mal test data for predcton. Lot 3-wafer 3 (actual) - Lot 3-wafer 3(predcted) V sf-- l- f- '- f- 6- f- l- - f-- 6. H-J----, \6. f- h / /' :- 6 _ S 5.S 0 lot 4-wafer 04 (actual) Poly sheet resstance VA Resstance Fgure 5: Scaled predcton wafer maps of PMOS drve current for dfferent wafers. NMOS drve current Lot 3 wafer 3(predcted all stes)?-r7'" Lot 3-wafer 3(predcted)-every de Metal 6 resstance Poly hgh sheet resstance PMOS VT Depleton MOS DVT The PMOS drve current predcton across dfferent wafers/lots s shown n Fgure 5. The mean absolute relatve error for wafer 3 s 0.54 % and the mean absolute relatve error for wafer 4 s.3%. The wafer predcton at all the 70 shots/stes (3x resoluton ncreases as compared to measurements) as well as for the all the pass devces n the wafer are shown n Fgure 6. Even though the regresson functon s developed at the shot-level, as an experment, the measurements of every ndvdual de can potentally be used to predct ther respectve parameters wthn a certan degree of acceptable error. As can be seen from Fgure 6, there exsts some whte spots n the wafer map correspondng to the faled devces. The accuracy of ths predcton can be made better f an nterpolaton algorthm that s capable of nterpolatng to the resoluton of a de s used and the regresson model s then developed usng the test measurements of every de rather than the medan of the des n the shot. Further advanced outler detecton mechansms appled to the measurement doman before developng the regresson functon wll mprove the predcton accuracy. As process montorng usng the proposed technque s performed usng test data of every de (close to l300 values n a wafer as opposed to the current e-test structure measurements), any process shfts can be quckly dentfed (close to 65x resoluton ncrease) and process shft nformaton can be fed back to the fab, before any future yeld loss occurs. The number of crtcal e-test Fgure 6: Scaled predcton wafer maps of PMOS drve current at every ste (left) and for every de (rght). An analyss of the regresson functons was performed to valdate the developed regresson model. The regresson functon for each ndvdual process e-test parameter s gven by the equaton below p = fmp(m) = Lf;(m;) + LAu(m;mu) +... Equaton 3 where the functon s regrouped to provde the relatve contrbuton of each measurement towards the process e-test parameter predcton. n Equaton 3,!(m;) s the contrbuton of the measurement to the process e-test parameter p. Ths analyss can be consdered as a varance contrbuton of each test measurement to the e-test parameter or equvalently as provdng a coeffcent to each test measurement. Such an analyss s performed for the process e-test parameters Poly sheet resstance and Parallel plate capactance and shown n Fgure 7 and Fgure 8 respectvely. As can be seen from Fgure 7, T8, T9, T0 contrbute sgnfcantly to the Poly sheet resstance parameter, these measurements are the 0 resstance and current measurements. Ths observaton concurs wth the desgn knowledge of the crcut. From Fgure 8, t can be nferred that no sngle test measurements contrbutes sgnfcantly to the parallel plate capactance.

6 6 Ths makes sense from a desgn perspectve as a multple number of test measurements get affected by capactance. = Regresson analyss of poly sheet resstance = 0 :9 ;< 30 j, e (0 E- 0 y, '5 0 ;=-';:..!;:: ';:: ;::Wr r N M w m O r N M w m o Test numbers Fgure 7: Analyss of regresson model. Regresson analyss of parallel plate capactance Test numbers Fgure 8: Analyss of regresson model for parallel plate capactance. V. BENEF[TS AND DSCUSSONS The contrbutons and potental benefts of ths work are: Provdes a methodology to determne the senstve e-test parameters usng the test data collected durng varous stages of testng of a devce (.e. de-level probe data and post -package fnal test data). Ths nformaton provdes a framework that can be used for makng quck decsons based on process varaton trends (potentally avalable from every de) so that potental future yeld loss can be prevented. The novelty of the presented yeld montorng technque n comparson to exstng ndustral process control technques s that t accounts for the senstvty of a partcular process e-test parameter to the crcut test measurement/specfcaton. Ths learnng of the relatonshp between test measurements and process e-test parameters can be helpful for performng dagnoss on customer return devces as well as n defnng varaton lmts for mportant process e test parameters based on lmts obtaned from pass devces when the devces are transferred from the exstng fab to other fabs. Fnally, the results of the presented analyss would help the desgn engneers and process-modelng engneers by provdng a means to compare process models (Spce models) wth varatons occurrng n producton envronment As mentoned earler, spatal nterpolaton technques elmnate the random component of process varaton. Ths random component s reflected only n the devce test measurement. As technology nodes scale, the random component of process varaton becomes sgnfcant. Hence, by predctng the e-test parameter usng measurement and comparng t wth the spatal nterpolated value may gve an ndcaton of extent of randomness n the parameter. Ths assumes that the nose n the measurement and the resdual error n the regresson model are mnmal. V. CONCLUSON A methodology for obtanng senstve process e-test parameters to enable a rapd feedback methodology for yeld montorng and dagnoss s presented. The technque s valdated usng data from four lots of a commercal SoC currently n producton and can be used to predct the e-test parameters at a de-level resoluton. The potental of the presented technque s mmense durng the producton yeld sustenance stage as well as product-rampng perod. REFERENCES [] Buhler. M. et al. "DATE 006 Specal Sesson: DFM/DFY Desgn for Manufacturablty and Yeld - nfluence of process varatons n dgtal, analog and mxed-sgnal crcut desgn," Proceedngs of Desgn, Automaton and Test n Europe, 006. Volume, 6-0 March 006. [] Cheh-Yuan Chao; Mlor, L.S.;, "Performance modelng usng addtve regresson splnes," Semconductor Manufacturng, EEE Transactons on, vol.8, no.3, pp.39-5, Aug 995. [3] Devarakond, S.K.; Sen, S.; Bhattacharya, S.; Chatterjee, A;, "Concurrent Devce/Specfcaton Cause-Effect Montorng for Yeld Dagnoss Usng Alternate Dagnostc Sgnatures," Desgn & Test of Computers, EEE, vo.9, no.l, pp.48-58, Feb. 0 [4] Andrew Hamlton,et.al. "An Expert System for Process Dagnoss," Proc. EEE [ntl. Conf. On Mcroelectroncs Test Structures. [5] F. D Palma, et a., "Process Dagnoss va Electrcal-Wafer-Sortng Maps Classfcaton," EEE [CDM, 005, 4 pp. [6] F.Chen and S.F. Lu, "A neural network approach to recognze defect spatal pattern n semconductor fabrcaton," EEE Trans. on Semconductor Manufacturng, 000, vol. 3, pp [7] Pelgrom, MJ.M.; Dunmajer, AC.J.; Welbers, AP.G.;, "Matchng propertes of MOS transstors," Sold-State Crcuts, EEE Journal of, vo.4, no.5, pp , Oct 989 [8] Lu, E.; Kao, W.; Felt, E.; Sangovann-Vncentell, A.;, "analog testablty analyss and fault dagnoss usng behavoral modelng," Custom ntegrated Crcuts Conference, 994., Proceedngs of the EEE 994, vol., no., pp.43-46, -4 May 994 [9] S. Cherubal, A Chatterjee, "Parametrc fault dagnoss for analog systems usng functonal mappng," DATE, 999, pp [0] Daasch, W.R.; McNames, J.; Madge, R.; Cota, K.;, "Neghborhood selecton for DDQ outler screenng at wafer sort," Desgn & Test of Computers, EEE, vol. 9, no.5, pp. 74-8, Sep-Oct 00. [] Ramakrshnan, H.; Shedabale, S.; Russell, G.; Yakovlev, A;, "Analysng the effect of process varaton to reduce parametrc yeld loss,". CCDT 008. EEE nternatonal Conference on, June 008 [] Wangyang Zhang; Xn L; Lu, F.; Acar, E.; Rutenbar, R.A; Blanton, R.D.;, "Vrtual Probe: A Statstcal Framework for Low-Cost Slcon Characterzaton of Nanoscale ntegrated Crcuts," Computer-Aded Desgn of ntegrated Crcuts and Systems, EEE Transactons on, vol.30, no., pp.84-87, Dec. 0. [3] R.Tbshran, "Regresson Shrnkage and Selecton va the Lasso," Journal of the Royal Statstcal Socety. Seres B (Methodologcal), Vol. 58, No. (996), pp [4] Wangyang Zhang, Karthk Balakrshnan, Xn L, Duane Bonng, and Rob Rutenbar. 0. 'Toward effcent spatal varaton decomposton va sparse regresson". n Proceedngs of the 0 EEEA CM nternatonal Conference on Computer-Aded Desgn (CCAD '). [5] Wangyang Zhang; et a., "Mult-Wafer Vrtual Probe: Mnmum-cost varaton characterzaton by explorng wafer-to-wafer correlaton," Computer-Aded Desgn (CCAO), 00 EEE/ACM nternatonal Conference on, vol., no., pp.47-54, 7- Nov. 00. [6]. H. Fredman, "Multvarate Adaptve Regresson Splnes", The Annals of Statstcs, vol. 9, 99, pp. -4.

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