Thermal Analysis on Face-to-Face(F2F)-bonded 3D ICs

Transcription

1 1/16 Thermal Analysis on Face-to-Face(F2F)-bonded 3D ICs Kyungwook Chang, Sung-Kyu Lim School of Electrical and Computer Engineering Georgia Institute of Technology

2 Introduction Challenges in 2D Device Scaling 2/16 130nm nm nm nm 2014 challenges channel length scaling increasing contact resistivity lithography limitation increasing wire resistance higher manufacturing cost How about placing cells in 3D space?

3 Introduction Three-dimensional (3D) ICs 3/16 Wafers are stacked vertically Benefits from short vertical connections Three flavors of 3D ICs MIV F2F-bond TSV-based 3D IC[1] easier and reliable vertical connection F2F-bonded 3D IC[1] Monolithic 3D IC[1] higher vertical integration density [1] S. Panth et al., "Design and CAD Methodologies for Low Power Gate-level Monolithic 3D ICs," IEEE International Symposium on Low Power Electronics and Design, 2014

4 Introduction Challenges in 3D ICs 4/16 Tools No EDA tools supporting 3D cell placement Requires tricks to place cells in 3D space Heat dissipation Higher temperature due to increased power density Requires thermal-aware packaging and 3D cell placement

5 3D IC Implementation Flow Cascade-2D Flow 5/16 How to place cells in 3D space? Mimic vertical connections with sets of anchor cells and dummy wires Implement two tiers simultaneously in a single emulated 2D design (cascade-2d design) top tier M3_T M2_T M1_T Slide Cut bottom tier MIV M6_B M5_B M4_B M3_B M2_B M1_B Monolithic 3D IC cascade-2d design in 2D EDA tools [2] K. Chang et al., "Cascade2D: A Design-Aware Partitioning Approach to Monolithic 3D IC with 2D Commercial Tools," IEEE International Conference on Computer-Aided Design, 2016

6 3D IC Implementation Flow Cascade-2D Flow Details 6/16 1. Design-aware partitioning (cell z-location) Perform block-level partitioning, maximizing timing paths crossing tiers 2. Vertical connection planning (vertical connection location) Determine vertical connection location, minimizing wire-length btw blocks 3. Cascade-2D design implementation (cell x-y location & routing) Implement the emulated 2D version of an M3D IC bottom partition Anchor cells and dummy wires act as a wormhole emulating vertical connections top partition dummy wire 0ns M8 M6 0ns 0ns M1 bottom tier area anchor cell cutline top tier area anchor cell

7 3D IC Implementation Flow Iso-performance Power Comparison 7/16 Design: Arm Cortex -A7 core Technology: Foundry 28nm, 14/16nm, and predictive 7nm technology 3D IC flavor: Monolithic 3D IC (M3D) 28nm 2D 28nm M3D

8 3D IC Implementation Flow Source of Power Savings 8/16 3D IC offers both wire-length and standard cell area savings

9 Thermal Analysis Flow Thermal Analysis Methodology 9/16 layer map (FEOL+BEOL) active of top wafer design + cell layouts conductivity map ANSYS Fluent active of bottom wafer thermal profile cell placement + power volume power

10 Thermal Analysis Flow Assumed Thermal Stack Configuration 10/16 thickness (um) material heat sink 1,000 Cu heat spreader 100 Cu TIM 25 Grease substrate 45 Si underfill 25 SiO 2 C4 25 Cu PCB 1,200 PCB

11 Thermal Analysis on F2F-bonded 3D ICs Temperature Comparison: 2D vs. F2F-bonded 3D IC 11/16 F2F-bonded IC (top) ºC 2D 103 ºC Min: ºC, Max: ºC F2F-bonded IC (bottom) 93.6 ºC 84.2 ºC Min: 65.3 ºC, Max: 72 ºC +40 ºC 74.7 ºC Min: ºC, Max: ºC 65.3 ºC

12 Thermal Analysis on F2F-bonded 3D ICs Impact of Frequency on Temperature 12/16 steeper increase max performance w/o thermal issue

13 Thermal Analysis on F2F-bonded 3D ICs Thermal Issue of F2F-bonded 3D ICs 13/16 M6_T heat sink FEOL M5_T M1_T M2_T M3_T BEOL M4_T PCB 2D IC M6_T heat sink FEOL M3_T M4_T M5_T M6_B M5_B M1_T M2_T BEOL trapped heat M4_B BEOL M3_B M2_B M1_B FEOL PCB F2F-bonded 3D IC

14 Thermal Analysis on F2F-bonded 3D ICs Impact of Packaging on Temperature 2D IC w/o PCB 77.3 ºC 72.3 ºC F2F-bonded 3D IC bottom w/o PCB top w/o PCB 14/ ºC ºC Min: 71.1 ºC, Max: 77.3 ºC 67.3 ºC Min: ºC Max: ºC Min: ºC Max: ºC ºC w/ PCB 62.3 ºC bottom top w/ PCB w/ PCB -5.3 ºC 57.3 ºC ºC ºC ºC ºC Min: 65.3 ºC, Max: 72 ºC 52.3 ºC Min: ºC Max: ºC Min: ºC Max: ºC Packaging affects more in F2F-bonded 3D ICs 99.4 ºC

15 Future Works 15/16 Impact of packaging Find thermal-aware packaging for F2F-bonded 3D ICs How to reduce trapped heat in the middle? Thermal-aware cell partitioning Place power hungry cells on top tier Impact of power-delivery network Utilize TSVs for better conduction to PCB Commercial tool Use commercial EDA tools for accurate thermal analysis

16 Thank You 16/16

17 3D IC Implementation Flow Design-Aware Partitioning Stage (cell z loc.) 17/16 Partition functional blocks into two groups Microarchitecture organization à Floorplan timing-critical functional blocks on different tiers Information from 2D implementation Functional block area The number of timing paths crossing each pair of functional blocks Partition functional blocks into two groups Balance area Maximize the number of timing-path crossing two groups

18 3D IC Implementation Flow MIV Planning Stage (MIV loc.) 18/16 Minimize the distance between functional blocks with large number of timing paths top group implementation bottom group implementation MIV ports (on M6) A D F B E C location of MIVs MIV ports (on M6)

19 3D IC Implementation Flow Cascade-2D Stage (cell x-y loc. & routing) 19/16 Dummy wires Connect MIV port pairs in two partitions Anchor cells à Connect MIV ports to M1 in top partition, M6 in bottom partition Perform place & route with hard partition between tiers Anchor cells and dummy wires act as a wormhole emulating MIVs bottom partition top partition dummy wire 0ns M8 M6 0ns 0ns M1 bottom tier area anchor cell cutline top tier area anchor cell

20 F2F-bonded 3D IC Implementation Flow Cascade-2D Flow 20/16 No EDA tools supporting 3D cell placement Use tricks to place cells in 3D space with 2D tools Implement two wafers simultaneously in a single emulated 2D design (cascade-2d design) cut top wafer M1_T slide dummy wire flip M4_T M4_B bot wafer M1_B anchor cell anchor cell F2F-bonded IC cascade-2d design in 2D EDA tools

21 F2F-bonded 3D IC Implementation Flow Design-Aware Partitioning Stage (cell z loc.) 21/16 Partition functional blocks into two groups Microarchitecture organization à Floorplan timing-critical functional blocks on different tiers Information from 2D implementation Functional block area The number of timing paths crossing each pair of functional blocks Partition functional blocks into two groups Balance area Maximize the number of timing-path crossing two groups

22 F2F-bonded 3D IC Implementation Flow F2F-bonds Planning Stage (F2F-bond loc.) 22/16 Minimize the distance between functional blocks with large number of timing paths top group implementation bottom group implementation F2F-bond ports (on M6) A D F B E C location of F2F-bonds F2F-bond ports (on M6)

23 F2F-bonded 3D IC Implementation Flow Cascade-2D Stage (cell x-y loc. & routing) 23/16 Dummy wires Connect F2F-bond port pairs in two partitions Anchor cells à Connect F2F-bond ports to M6 of each partition Perform place & route with hard partition between tiers Anchor cells and dummy wires act as a wormhole emulating MIVs dummy wire bottom partition top partition 0ns 0ns 0ns bottom wafer area anchor cell cutline top wafer area anchor cell

24 F2F-bonded 3D IC Implementation Flow Experimental Setup 24/16 Design: Arm Cortex -A7 core Technology: CLN16FCLL ULVT Target Frequency: F2F-bonds size/pitch: 0.5um/1um top wafer design M1_T M2_T M3_T M4_T M5_T M6_T PAD_T F2F-bond PAD_B M6_B M5_B M4_B M3_B M2_B 2D IC F2F-bonds F2F-bonded 3D IC M1_B bottom wafer design

25 F2F-bonded 3D IC Implementation Flow Design / Power Metric Comparison 25/16 metrics 2D IC F2F-bonded 3D IC % target freq (GHz) footprint (um) 523x x cell count 199, , std. cell area (um 2 ) 69,009 68, density (%) wire-length (um) 3,025,229 2,885, pin cap (pf) wire cap (pf) total cap (pf) sw power (mw) int power (mw) lkg power (mw) tot power (mw)

26 F2F-bonded 3D IC Implementation Flow Reason for Low Power Saving 26/16 Slow memory Almost all critical paths start from memory blocks Standard cell area reduction happens only on those paths Memory floorplan Non-optimal F2F-bond placement congestion congestion bottom wafer top wafer

27 Thermal Analysis Flow Assumed Thermal Stack Configuration 27/16 width/height thickness (um) material K (W/m-K) heat sink wafer width/height * 2 1,000 Cu 401 heat spreader wafer width/height * Cu 401 TIM wafer width/height 25 Grease 5 substrate wafer width/height 45 Si 149 underfill wafer width/height 25 SiO C4 25um (pitch 50um) 25 Cu 401 PCB wafer width/height *2 1,200 PCB 4.5(V) / 60(L)