Power-Supply-Network Design in 3D Integrated Systems

Transcription

1 Power-Supply-Network Design in 3D Integrated Systems Michael B. Healy and Sung Kyu Lim School of Electrical and Computer Engineering, Georgia Institute of Technology 777 Atlantic Dr. NW, Atlanta, GA 3332 {mbhealy, Abstract Three-dimensional integration (3D IC) technology has been gaining significant interest from the VLSI community for several years. However, layout-level explorations of the impact of 3D technology have only recently been introduced. This work examines both static and dynamic power-supply noise in a layoutlevel 3D design prototype, and the impact of possible 3D-specific changes to the power-supply network design and topology. Our results show that distributing power-supply TSVs throughout the design with finer pitch than the C4 supply bumps lowers both IR-drop and dynamic noise in our 3D system. In fact, using a distributed TSV topology lowers dynamic noise by 13.3% compared to a 2D system with less total power dissipation. We also show several other 3D-specific supply network changes and their impact on both IR-drop and dynamic noise. I. INTRODUCTION Many players in both the VLSI industry and academia see 3D stacking as a coming major trend. 3D stacking has the potential to reduce power consumption from off-chip communication, reduce wirelength and delay, and lower the cost of process integration. However, there remain many challenges in the design of 3D ICs. Increases in volumetric power density combine with larger thermal resistance between the silicon layers and the heatsink could result in higher operating temperatures and reductions in reliability. Smaller footprints and larger package-level power consumption could cause power-delivery problems. In this work we provide a layout-level examination of the design of 3D power delivery networks, and demonstrate that the unique environment of 3D ICs can have a dramatic effect on both IR-drop and dynamic noise in these networks. We examine two types of power-supply noise in a layoutlevel prototype processor-on-memory stacked 3D system. IRdrop (sometimes referred to as ground-bounce) is the resistive voltage drop in power and ground distribution networks caused by the dynamic and leakage power of ICs. Dynamic noise in power-supply networks results from transient changes in device current demand interacting with inherent inductance in the power-delivery network. Continued device scaling has resulted in reduction in supply voltages and increases in total current, which reduces power-supply-noise margins. These factors are causing a larger and larger percentage of available routing resources to be dedicated to power supply distribution in high-performance designs, which can add significantly to congestion problems and reduce the amount of functionality that can be packed into a unit area. Many researchers have proposed optimization schemes for traditional IC power network design. Previous work on power delivery networks for 3D systems has largely assumed a straightforward extension of 2D power delivery network design. Huang et al. [1] presented a physical model of 3D power distribution networks. Jain et al. [2] extended the work of Gu et al. [3] by examining the use of multi-story power delivery in 3D ICs. Yu et al. [4] demonstrate an optimization scheme for supply-bump assignment and via insertion simultaneously considering both supply noise and temperature. Healy and Lim [5] examined scaling trends in many-tier 3D powerdelivery networks. All previous work assumes that supply bumps are aligned with TSVs in every case. The overall goal of this work is to provide a layout-level exploration of power delivery in 3D ICs and how it differs from traditional designs. Compared to prior efforts, we demonstrate the benefits of re-examining the unique capabilities of TSVs relative to package-level bumps. We also perform our analysis using layout-level designs and strive to provide realistic results. Accordingly, we validate our model results using commercial-grade sign-off IR-drop analysis software. The major contributions of this work are as follows: We present the first layout-level analysis of 3D power distribution networks that is validated using commercial tools. We demonstrate improve power-supply noise by spreading power and ground distribution TSVs away from the power and ground supply bumps in designs with nonuniform power dissipation. We examine other 3D-specific techniques for improving power-supply noise and demonstrate their effectiveness using our framework. II. 3D AND FLIP-CHIP POWER NETS High performance 3D systems will generally use flipchip style packaging to increase off-chip interconnect density and reduce parasitics. Flip-chip power distribution systems are commonly laid out as grids. High-level metal layers are reserved for laying out a coarse-grained grid with large wires that connects a regular array of power and ground C4 bumps. A fine-grained mesh provides local distribution and connects to lower-level-metal power rings or standard-cell row distribution wiring. Most commercial products today have C /11/$ IEEE th Int'l Symposium on Quality Electronic Design

2 Core Bulk Active Layer Core Bulk Active Layer Mem 1 TSV Mem 1 TSV Mem 2 Mem 2 P/G bump C4 C4 P/G TSVs Clustered Distributed Fig. 1. P/G wires (thick) Bumps, TSVs, and wires in a 3D P/G network Fig. 2. Two TSV topologies for power distribution. C4 bumps are shown in black and P/G TSVs in green. The combined resistance of all TSVs in each topology is equal. bump pitches around 1 to2μm, however, researchers have demonstrated micro-bumps with pitches below 1μm. For 3D systems, each tier will contain its own power distribution network. These networks will all be interconnected using TSVs. Figure 1 shows the general topology of a 3D power distribution network. The inter-layer resistance between adjacent tiers should be close to that of the C4 bumps to maintain reliable power and ground voltages. The resistance of individual C4 bumps is on the order of 5mΩ. Additionally, TSVs should be much smaller than the C4 bumps or large amounts (25% or more) of die area will become unusable. TSVs can be manufactured in many different sizes. Diameters of less than 1μm have been shown in the literature. Power and ground TSVs should be large to have low resistance, but signal TSVs should be small to increase interconnect density and reduce parasitic capacitance. Manufacturing multiple TSV sizes on a single die would increase cost and reduce yield. Therefore, it will likely be necessary to use a single TSV size for both power distribution and signal wiring. In this work it is assumed that only one TSV size is available, and the TSV size is optimized for signals. There are several potential combinations of TSV distribution that could be used to deliver power. Figure 2 shows two of the basic choices we investigate thoroughly in this paper. clustered topology: multiple small TSVs are clustered over the C4 pads for both power and ground distribution. distributed topology: multiple small TSVs are spread evenly throughout the die. The combined resistance of all the TSVs is assumed to be the same for both of the topologies. III. PROTOTYPE LAYOUT The prototype layout used in our simulations is based on a design targeted at demonstrating extreme memory bandwidth using 3D interconnects. Our design is a many-core processor composed of an array of simple cores connected with a nearest-neighbor communication mesh. Each core has eight banks of dedicated SRAM directly stacked above it in two separate tiers. The core tier contains a 1 1 array of cores. The 1-core prototype processor was designed using a 13-nm standard cell library from Global Foundries. For the physical design we used Cadence s SOC Encounter automated RF i-mem Fig. 4. The power map for one core of our processor. The maximum total power consumption per core is 65.5mW. place and route tool. The layouts for a single core and a single memory tile are shown in Figure 3. We also highlight the areas in the layout reserved for ground TSV connections. The distribution of connection points is irregular due to the constraints of the layout, especially the locations of the hard memory macros. For the distributed TSV topology, TSVs are located at all of the potential locations. In the clustered TSV topology, all of the TSVs are grouped into the center position, over the C4 bump. The power TSV locations are similarly distributed in an offset fashion, the main difference is that the power C4 bumps are at the corners of the core, while the ground C4 bump is in the center. Each location is capable of accepting a 6μm diameter via-first TSV, while the locations over the C4 bumps (the center and near the corners) are capable of accepting 25 or more of these TSVs. The single-core and single-tile layouts are both 56μm square. The core-to-core and tile-to-tile pitch is 59μm to accommodate the inter-core logic and communication, as well as the power distribution from the C4 bumps. The full 1- core and 1-tile layers are approximately 6mm square. The maximum total power dissipation for the system (one core tier + two memory tiers) is approximately 13.2W. Figure 4 shows the power map for a single core. The power dissipation of this design is not extreme, however the high volumetric power density could be a problem for traditional heatsinks. For this case micro-fluidic channels [6], [5] have been shown to be an effective method for cooling large-scale 3D chip stacks.

3 ground C4 possible ground TSV locations single core layout single memory tile Fig. 3. Layout of a single core and single memory tile from our 1-core processor. The possible ground distribution TSV locations are highlighted in red. The ground C4 bump in the center of the core is indicated. The power C4 bumps are near the corners of the core. A. Methodology IV. 3D IR-DROP ANALYSIS Layout-level IR-drop values are computed by performing power consumption simulations, either statistical or simulation-driven, to obtain gate- and module-level power consumption values. The consumption values are then divided by the nominal supply voltage, in our case 1.5V, to obtain gate- and module-level current consumption values. Next, parasitic extraction is performed on the layout to obtain a SPICE netlist that models the power distribution network. Our experiments were performed using Cadence s QRC transistorlevel extraction tool. The current consumption values are then connected to the nodes representing the corresponding transistors belonging to the appropriate gates and modules. For traditional 2D ICs the netlist is then simulated using a power network simulator, in our case Cadence s UltraSim. Figure 5 shows the analysis flow 2D netlists. In 3D designs the previously described steps are performed once for each type of tier (core, memory, etc.). The tier-type SPICE models are replicated for each instance of that tier-type and then connected using a resistive TSV model. Simulation of power distribution networks is a generally difficult problem for traditional ICs. These networks can contain tens of millions of nodes. 3D stacking exacerbates the problem even further. Given the extreme regularity of the prototype design that is examined in this work, we mitigate some of the extreme memory and execution-time requirements of power network simulation by only simulating a 5 5 array of cores instead of the full 1 1 array. We stress that our design is extremely regular and so this reduction should only impact the accuracy of our analysis in a minor way. Simulations indicate that this introduces approximately 3% error in our results. annotated GDSII SPICE netlist Calibre LVS Cadence QRC layout translate transistors to current sources tier-level netlist Cadence VoltageStorm power consumption Fig. 5. The analysis flow used to obtain the tier-level netlist for IR-drop analysis. This flow is performed multiple times for each tier type, then the netlists are connected together with a TSV model for 3D analysis. B. Validation We compare the results for a 2D layout to Cadence s VoltageStorm sign-off power noise analysis tool to validate the IR-drop analysis flow described above. The results of our analysis flow are within 4% of the values reported by VoltageStorm. We were also able to create a method for tricking VoltageStorm into performing 3D analysis for twotier stacks. First we create an ICT file, a process technology description file, that contains a description of all of the metal layers in two tiers. The metal and dielectric layers are renamed so that the tier number is embedded in the name. For example, METAL1 becomes METAL1 1 and METAL1 2. Then, a techfile is created using Cadence s TechGen based on the new ICT file. Next, we modify the LEF files provided by the foundry that describe the technology, standard cells, and

4 Iload Imax... 5 ps 15 ps 3 ps Fig. 7. The current waveform used for each transistor for dynamic noise analysis. A random delay is added to the start of the waveform for each gate s transistors. Fig. 6. A depiction of the ICT file that contains metal layers for two tiers of a 3D stack. The ICT file is used to compile a techfile used for parasitic extraction by VoltageStorm for our 3D IR-drop verification flow. TABLE I EFFECTIVE INDUCTANCE VALUES IN ph FOR POWER DISTRIBUTION TSVS. THE TSV DIMENSIONS ARE IN μm. TSV Dimensions Clustered Distributed μm.829 ph.14 ph μm 1.6 ph.27 ph μm 2.5 ph.41 ph μm 3.6 ph.58 ph macros. The DEF and instance power files for the designs of each tier are also modified in the same way. Each file is essentially duplicated so that there is one version for the first tier and one version for the second tier. The modifications amount to renaming the objects and metal layers in the same way that the ICT file is modified. To include detailed analysis of the macro blocks, we also modify their GDSII files. We first convert the GDSII to GDT, an ascii-version of the binary GDSII data. Then we map all of the GDSII layer numbers for the metal layers into a non-overlapping number space. The modified GDT is then converted back to GDSII. The XTC extraction tool is then given a GDSII layer map file that maps the appropriate layer numbers to the correct tier s metal layers for each macro. Using the above method we were able to match the 3D IRdrop results from VoltageStorm within 4%. Figure 6 shows a depiction from Cadence s ViewICT tool of the modified ICT file containing metal layers in two dies. Note that the second die does not have a substrate layer. This is a limitation of the tool, due to the fact that it was not designed with 3D designs in mind. However, for power/ground network analysis the substrate can largely be ignored. For these experiments we created a face-to-back style 3D design, however, this technique is general enough to apply to face-to-face 3D designs as well. V. 3D DYNAMIC NOISE ANALYSIS Layout-level dynamic noise values are computed using the power consumption values and parasitic extracted networks obtained for IR-drop analysis with added decoupling capacitors. We create triangular current demand waveforms [7] (Figure 7) for each transistor such that the average power consumption matches the value obtained for IR-drop analysis. The triangular waveforms for each gate are delayed by a random amount such that the majority of them start near the beginning of the cycle. The random delays are distributed in a Gaussian fashion about zero and then the absolute value of the delay is used for the real current waveform. Our dynamic noise numbers are obtained by performing transient simulation of a repeating pattern of current demand with a cycle time of 3ps. The peak of the voltage swing is recorded as the noise value after the swings have stabilized. Ultrasim s power network simulation engine does not handle large-scale transient simulation well, so we used a custom SPICE simulator based on Modified Nodal Analysis [8], which returns results within 2% of HSPICE. For our simulations we use a step size of 1ps. TSV inductance may also be an important contributor to dynamic noise. We modeled several sizes and arrangements of TSVs using Synopsys inductance extractor Raphael. The results of our TSV inductance simulations are shown in Table I. The distributed TSV topology results in effective inductance values about two orders of magnitude smaller than the clustered TSV topology. The default TSV size used in most of our simulations is 6 6 2μm. VI. RESULTS First, we compare our 3D prototype system with a 2D system containing a single layer with 1 cores. The IR-drop and dynamic noise results are shown in Figure 8. The graph shows that the 3D system with the clustered TSV topology results in higher maximum IR-drop and dynamic noise in the core layer. This is expected due to the additional TSV parasitics between the package-level power-supply bumps and the extra power consumed by the memory layers. However, the 3D system using the distributed TSV topology results in 13.3% lower IR-drop and dynamic noise than the 2D system, even though the 3D system dissipates more power. The improvements in power-supply noise seen when using the distributed TSV topology are enabled by the sharing of noise slack between the memory layers and the core layers. This can be seen in Figure 8 by comparing the relative noise levels of the memory layers between the clustered and distributed TSV topologies. The distributed TSV topology trades-off lower maximum system-level supply noise with higher supplynoise levels in the memory layers. Next, we show the results of modifying the size of the TSVs used to deliver power in our prototype 3D system. This analysis is accomplished by modifying the resistances and

5 25 Noise Value (mv) Core Mem 1 Mem Core Only Clustered Distributed Core Only Clustered Distributed 2D 3D 3D 2D 3D 3D IR-Drop Dynamic Noise Fig. 8. A comparison of the IR-drop and dynamic noise results for a 2D system with only the core tier and 3D systems with the clustered and distributed TSV topologies. The black line at 15mV represents the 1% noise margin. 25 Dynamic Noise (mv) Clustered Distributed Default TSV Size 3x3 6x6 1x1 15x15 TSV Size (um) Fig. 9. The dynamic noise in the three-layer system with both the clustered and distributed TSV topologies. Results for several different TSV sizes are shown. 25 Noise Value (mv) Clustered Distributed Default Default 2 Bumps 8 Bumps 2 Bumps 8 Bumps IR-Drop Dynamic Number of Bumps/Core Fig. 1. The impact on IR-drop and dynamic noise of increasing the number of bumps from two per core to eight per core Dynamic Noise (mv) Clustered Distributed Power Dissipation Ratio Fig. 11. The effect on dynamic noise of modifying the power dissipation ratio between the core and memory tiers. The total power consumption remains the same. The inflection point at.6 indicates the point where all three tiers dissipate the same amount of power. inductances representing the TSVs connecting neighboring tiers. Figure 9 shows the impact on dynamic noise of using four different sizes of TSVs. For this three-layer 3D system, the impact on power-supply noise of using different TSV sizes is relatively negligible. The impact is more significant for the distributed topology than for the clustered topology. However, TSV size will have a more significant impact on the actual layout itself, as well as the timing of the 3D signal nets. The trends for IR-drop are similar to those for dynamic noise. Figure 1 shows IR-drop and dynamic noise results for changing the number of bumps per core from the default (two bumps per core) to eight bumps per core. The results show that decreasing the C4 pitch has a significant impact on the noise results. The benefits of the distributed topology drop with more bumps per core because the number of TSVs is not increasing in this comparison. The trends are similar between IR-drop and dynamic noise. The different power dissipation levels of the various tiers in the 3D stack affect the improvements caused by using the distributed TSV topology versus the clustered TSV topology. To examine this in more detail we modified the power consumption of each tier such that the total power consumption of the stack remained constant. The supply-noise results are then plotted against the ratio of power dissipation between the core and memory tiers. The supply-noise results for this set of simulations is shown in Figure 11. Additionally, the actual percentage improvement in supply-noise is shown in Figure 12. The graphs show that when the power dissipation ratio between the memory and core tiers results in even power dissipation among all tiers the benefit of the distributed TSV topology is the lowest. As the ratio diverges from this value the improvement of the distributed topolgy increases up to 2%. Finally, Figure 13 shows the impact on dynamic noise of adding decap tiers to the three-layer stack. Adding a single decap tier improves the dynamic noise below the 15mV noise margin for the distributed TSV topology. Adding four decap tiers to the clustered topology (more than doubling the number of tiers stacked together) does not reduce the supply-noise below the 1% noise margin. These results indicate once more that the distributed TSV topology generally results in improved supply-noise performance. In fact, the addition of decap tiers is the only modification to the power-supply network that reduces the dynamic noise below the 1% noise margin. VII. CONCLUSIONS In this work we have explored 3D power delivery network design and shown that IR-drop and dynamic noise can be improved in these systems by exploiting the particular attributes of power supply TSVs that are unique compared to those of C4 supply bumps. Previous works have assumed a straightforward extension of traditional power supply network design in which

6 % Improvement Power Dissipation Ratio Fig. 12. The dynamic noise improvement of the distributed TSV topology over the clustered TSV topology. The total power consumption remains the same. The inflection point at.6 indicates the point where all three tiers dissipate the same amount of power. 25 Dynamic Noise (mv) Clustered Distributed REFERENCES [1] Gang Huang, M. Bakir, A. Naeemi, H. Chen, and J.D. Meindl. Power delivery for 3D chip stacks: Physical modeling and design implication. In Proceedings IEEE Conference on Electrical Performance of Electronic Packaging, pages 25 28, 27. [2] Pulkit Jain, Tae-Hyoung Kim, John Keane, and Chris H. Kim. A multistory power delivery technique for 3D integrated circuits. In Proceedings International Symposium on Low Power Electronics and Design, pages 57 62, New York, NY, USA, 28. ACM. [3] Jie Gu and Chris H. Kim. Multi-story power delivery for supply noise reduction and low voltage operation. In Proceedings International Symposium on Low Power Electronics and Design, pages , New York, NY, USA, 25. ACM. [4] Hao Yu, Joanna Ho, and Lei He. Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity. ACM Transactions on Design Automation of Electronics Systems, 14(3):1 31, 29. [5] Michael B. Healy and Sung Kyu Lim. A study of stacking limit and scaling in 3D ICs: An interconnect perspective. In Proceedings IEEE Electronic Components and Technology Conference, pages , May 29. [6] D. Sekar, C. King, B. Dang, T. Spencer, H. Thacker, P. Joseph, M. Bakir, and J. Meindl. A 3D-IC technology with integrated microchannel cooling. In Proceedings IEEE International Interconnect Technology Conference, pages 13 15, 28. [7] Q. K. Zhou. Power Distribution Network Design for VLSI. Wiley-IEEE, 24. [8] Chung-Wen Ho, Albert E. Ruehli, and Pierce A Brennan. The modified nodal approach to network analysis. IEEE Transactions on Circuits and Systems, (6):54 59, June Number of Decap Tiers Added Fig. 13. stack. The impact on dynamic noise of adding decap tiers to the three-layer the TSVs are treated as an extension of the C4 bumps. We advocate a design style in which power network TSVs are distributed throughout the entire surface of the layout. This increases the level of coupling between the power distribution networks of the various tiers in the 3D stack. This technique also allows the utilization of supply-noise slack in the lowerpower tiers to reduce overall system-level supply noise. To support our claims, we designed a 1-core 3D processor across three stacked tiers at the layout level. Our 3D IR-drop analysis method was verified against commercialgrade sign-off IR-drop analysis software from a major EDA vendor at both the 2D and two-tier 3D level. Detailed static and dynamic power-supply-noise simulations demonstrate that the distributed TSV topology generally provides much lower supply noise. The distributed TSV topology lowers dynamic noise for a three-tier system compared to a non-3d system by 13.3%, even though the total power consumption is higher in the three-tier system. The addition of one tier containing only decoupling capacitors also reduces dynamic noise by 31% when using the distributed topology. VIII. ACKNOWLEDGMENTS This material is based upon work supported by the National Science Foundation under Grant No. CCF-917, the SRC Interconnect Focus Center (IFC), and Intel Corporation.