Thermal Modeling and Active Cooling
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1 Thermal Modeling and Active Cooling for 3D MPSoCs Prof. David Atienza, Embedded Systems Laboratory (ESL), EE Institute, Faculty of Engineering MPSoC 09, 2-7 August 2009 (Savannah, Georgia, USA)
2 Thermal-Reliability Issues in 3D Chips Latest chips increase power density Non-uniform hot-spots in 2D chips In 3D chips, heat affects several layers! (even more cool components) [Sun, 1.8 GHz Sparc v9 Microproc] Courtesy: [Sun, [IBM and Irvine Sens.] Niagara Broadband Processor] 2
3 Run-Time Heat Spreading in 3D Chips 5-tier 3D stack: 10 heat sources and sensors Layer Inject between 4W 1.5W width (um) length (um) Layer nd Tier width (um) h (um) width th Tier Layer length (um) wid dth (um) Layer length (um) length (um) 3 rd Tier Large and non-uniform th Tier heat propagation! (up to 130º C on top tier) 394
4 NanoTera CMOSAIC Project: Design of 3D MPSoCs with Advanced Cooling 3D systems require novel electro-thermal co-design Academic partners: EPFL and ETHZ Industrial: IBM Zürich 4
5 NanoTera CMOSAIC Project: Design of 3D MPSoCs with Advanced Cooling 3D systems require novel electro-thermal co-design Academic partners: EPFL and ETHZ Industrial: IBM Zürich 3D stacked MPSoC chips: microchannels etched on back side to circulate liquid coolant HW adjustment at run-time of coolant flux SW task execution control System Level Ati Active Cooling Manager (heat flow prediction) 5
6 Compact RC-Based Tier Thermal Model Gate-level thermal model q bj 6 b f 1 fj T f b 0 j q Network of q b_top q b_back Si/metal layer cells q b_left q b_front q q b_right q b_bottom 2D tier modeled as heat flux moving between adjacent cells I-1 I I+1 (q bi ) I (q bi ) I+1 face i Convective boundary conditions between layers in tier q b_top = h top A(T a -T top ) q b_bottom = h bottom A(T a -T bottom ) [Atienza et al., TODAES 2007] 6
7 Complete 3D Chip Thermal Modeling Multi-level execution for thermal convergence in 3D Local (2D-tier) and then global (3D) propagation N iteration ns Evaluate local temperature for the cell Feedback temperature Update with neighbour temperature difusion Tier-lev vel conve ergence Go to next material layer 7
8 3D Thermal Model with Liquid Cooling 3D stack modeled as iterative process Each tier and liquid cooling flow Flexible set of layers in 3D stack, extendible 3D stack (up to 9 tiers) Pre-defined layers: Silicon, metal (10 layers), glue, overmold, interposer, bump 5-Tier validation stack manufactured at EPFL: Liquid Micro-Heater PCB Micro-Channels [Ayala et al., NanoNet 09] 8
9 3D Thermal Model with Liquid Cooling: Correlation with 5-Tier 3D Stack e (mv) Sensor Voltag D Chip, EPFL, Layer 3 characterization ti Blue Curve: 3D current -heat model for D8 Pink curve: Heater current measured in D8 Dev8 D7HD8S Heater Current (ma), applied to Dev 7 Sensor Voltage ( mv) D Chip, EPFL, multi-tier tier characterization Bue/Pink Curve: D7 (tier 1) and D8 (tier 4) Red Curve: 3D current-heat model for D8 Dev6 Dev7 Div6_Iheat Heater Current (ma), applied to Dev 7 9
10 3D Thermal Model with Liquid Cooling: Correlation with 5-Tier 3D Stack e (mv) Sensor Voltag D Chip, EPFL, Layer 3 characterization ti Blue Curve: 3D current -heat model for D8 Pink curve: Heater current measured in D8 Dev8 D7HD8S Heater Current (ma), applied to Dev 7 Variations of less than 1.5% between 3D stack measurements and new 3D thermal model mv) Sensor Voltage ( D Chip, EPFL, multi-tier tier characterization Bue/Pink Curve: D7 (tier 1) and D8 (tier 4) Red Curve: 3D current-heat model for D8 Dev6 Dev7 Div6_Iheat Heater Current (ma), applied to Dev 7 10
11 Run-Time HW/SW Thermal Modeling Framework for 2D/3D Chips Exploitation HW/SW (Atienza et al.,todaes 2007, THERMINIC 09) Zero-delay MPSoC architecture simulation Multi-Proc. OS + DVFS + Task Migration I/O CPU CPU Sw app 1... Sw app N SRAM SRAM SRAM I/O CPU CPU Energy of 2D components MPSoC Behavior Emulation on FPGA Detailed thermal analysis of 2D MPSoC layout standard Ethernet connection & dedicated HW monitor Software Thermal Model cu cu cucu cu si si si si si si si si si Temp. (T) of 2D components Host PC
12 Run-Time HW/SW Thermal Modeling Framework for 2D/3D Chips Exploitation HW/SW (Atienza et al.,todaes 2007, THERMINIC 09) Zero-delay MPSoC architecture simulation Multi-Proc. OS + DVFS + Task Migration I/O CPU CPU Sw app 1... Sw app N SRAM SRAM SRAM I/O CPU CPU Energy of 3D components MPSoC Behavior Emulation on FPGA Detailed thermal analysis of 3D MPSoC layout standard Ethernet connection & dedicated HW monitor Temp. (T) of of 2D 3D components N th Tier 3D Stack Thermal 1 st Tier Model Host PC
13 Thermal Management for 3D Chips: 3D-Floorplans 8-/16-Core Sun Niagara 3D Layouts (2 and 4 tiers) Web and server processing applications Separ-2 Mixed-2 Separ-4 Mixed-4 (EXP1) (EXP2) (EXP3) (EXP4) FEATURE Die thickness (1 stack) SIZE 0.15mm Area/core 10mm 2 Area/L2 cache 19mm 2 Convection capacitance Convection resistance 140 J/K 0.1 K/W Interlayer material 0.02mm thickness Interlayer material 0.25m resistivity K/W [A. Coskun et al., DATE 09] 13
14 Thermal Management for 3D Chips: Adapt3D Results 3D thermal manager with fixed and variable flow rates Proactive task sched., liquid cooling, floorplan-aware DVFS Promising figures for thermal control in 3D-MPSoCs [A. Coskun et al., DATE 09,VLSI-SoC 09] 14
15 Key References and Bibliography Thermal modeling and FPGA-based emulation HW-SW Emulation Framework for Temperature-Aware Design in MPSoCs, David Atienza, et al. ACM Trans. on Design Automation for Embedded Systems (TODAES ), Vol. 12, Nr. 3, pp. 1 26, August Emulation-Based Transient Thermal Modeling of 2D/3D Systems-on-Chip with Active Cooling, David Atienza, Proc. of the 15 th IEEE International Workshop on Thermal Investigations of ICs and Systems (THERMINIC 09), Belgium, October, Thermal management for 3D MPSoCs Dynamic Thermal Management in 3D Multicore Architectures, Ayse K. Coskun, et al., Proc. of Design, Automation and Test in Europe (DATE 09), France, April Modeling and Dynamic Management of 3D Multicore Systems with Liquid Cooling, Ayse K. Coskun, et al., Proc. of 17 th Annual IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 09), Brazil, October Through Silicon Via-Based Grid for Thermal Control in 3D Chips, Jose L. Ayala, et al., Proc. of the 4 th International ICST Conference on Nano-Networks (Nano-Net 09), Switzerland, October 2009.
16 QUESTIONS?
3D MPSoCs with Active Cooling
System-Level Thermal Management of 3D MPSoCs with Active Cooling Prof. David Atienza, Embedded Systems Laboratory (ESL), Ecole Polytechnique Fédérale de Lausanne (EPFL) MPSoC 11, July 4 th 8 th 2011 (Beaune,
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-1- ARTIST Summer School in Europe 2010 Autrans (near Grenoble), France September 5-10, 2010 Thermal-Aware Design of 2D/3D Multi-Processor System-on on-chip Architectures Invited ds Speaker: David idai
This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research and
This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research and education use, including for instruction at the authors institution
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