Introduction. Serial Peripheral Interface (SPI) SPI Basics. Capabilities of SPI

Transcription

1 Introduction Serial Peripheral Interface SPI_single_slave.svg/35px-SPI_single_slave.svg.png Serial Peripheral Interface (SPI)! What is it?! Basic Serial Peripheral Interface (SPI)! Capabilities ผศ.ดร. ส ร นทร ก ตต ธรก ล และ อ.สรย ทธ กลมกล อม ภาคว ชาว ศวกรรมคอมพ วเตอร คณะว ศวกรรมศาสตร สถาบ นเทคโนโลย พระจอมเกล าเจ าค ณทหารลาดกระบ ง! Protocol! Pro / Cons and Competitor! Uses! Conclusion 2 SPI Basics Capabilities of SPI! A communication protocol using 4 wires! Also known as a 4 wire bus! Used to communicate across small distances! Multiple Slaves, Single Master! Synchronized! Always Full Duplex! Communicating in two directions at the same time! Multiple Mbps transmission speed! Transfers data in 4 to 6 bit characters! Multiple slaves! Daisy-chaining possible 3 4

2 Protocol! Wires:! Master Out Slave In (MOSI)! Master In Slave Out (MISO)! System Clock (SCLK)! Slave Select N! Master Set Slave Select low! Master Generates Clock Wires in Detail! MOSI Carries data out of Master to Slave! MISO Carries data from Slave to Master! Both signals happen for every transmission! SS_BAR Unique line to select a slave! SCLK Master produced clock to synchronize data transfer! Shift registers shift in and out data 5 6 Master'with'Independent'Slaves' Master-Slaves/Daisy Chain' Less$wiring$ Slow$data$xFer$ Broadcast$is$also$possible.$ Master and multiple independent slaves 7 8

3 Shifting Protocol Data'xFer' Master shifts out data to Slave, and shift in data from Slave 9 Clock Phase (Advanced) ' SPI-mode CPOL CPHA Sampling 2 3 $ Leading$(Rising)$Edge$ Trailing$(Falling)$Edge$ Leading$(Falling)$Edge$ Trailing$(Rising)$Edge$ Clock'&'' Sampling'! Two phases and two polarities of clock => Four modes! Master and selected slave must be in the same mode! Master must change polarity and phase to communicate with slaves of different numbers 2

4 SPI'Data'Transfer'Modes'' " CPOL$and$CPHA.$$ " Modes$$and$3$are$the$most$common.$ " With$SPI$modes$$and$3,$data$is$always$latched$ in$on$the$rising$edge$of$sck$and$always$output$ on$the$falling$edge$of$sck.$ Example SPI devices 25LC2A - 2K SPI Bus Serial EEPROM TC Thermal Sensor with SPI Interface MCP32-2.7V 2-Bit A/D Converter with SPI Serial Interface MCP Bit DAC with Internal VREF and SPI Interface MCP4 - Single/Dual Digital Potentiometer with SPI Interface MCP6S92 - Single-Ended, Rail-to-Rail I/O, Low-Gain PGA MCP23S8-8-Bit I/O Expander with Serial Interface Example:'SPIADAC' MAX536'Diagram' MAXIM$MAX536$ 6Rbit$+/R$$LSB$Accuracy$ 2.7V$to$5.5V$supply$voltage$range$$ 5MHz$3Rwire$SPI$interface$$ 5 6

5 MAX536'Timing'Diagram' Example - reading data from the MCP32 (2 bit ADC)'' 7 8 Initialization' /*Initialise+SSP+in+SPI+mode+*/+ void+init_ssp(void)+ {+ + ++IODIR++=+IODIR PIN_SSP_SS; +//Enable+SSEL+pin+as+GPIO+ ++PINSEL+++ =+xa8;++++ +//Enable+SSP+pins+with+SSEL+as+GPIO+ ++//PINSEL+ =+xaa;+++ +//Enable+SSP+pins+with+SSEL+as+SS+ + ++/*+Set+DSS+data+to+8Ibit,+Frame+format+SPI,+CPOL+=+,+CPHA+=+,+and+SCR++ +(serial+clock+rate+(presscaler)+is+5+*/ SSPCR+=+xFF7;+ ++SSPCR+=+x2; ++++//Configure+as+SPI+Master /*+SSPCPSR+clock+prescale+register,+master+mode,+minimum+divisor++ +is+x2+max+254+*/+ ++SSPCPSR+=+5;+ 9 }+ Sender' /*Send+data+to+the+SSP+the+start+address+and+number+of+bytes+(size+of+ array)+must+be+given*/+ void+sspsenddata(unsigned+char+*data_add,unsigned+char+arr_size)+ {+ ++int+i;+ ++SSP_SS(); + + +//Select+slave+active+low+ ++for(i=;i<arr_size;i++)+ ++{+ ++++while+(+(sspsr+&+sspsr_bsy)+);+//+wait+until+the+busy+bit+is+ //+cleared SSPDR+=+*data_add;+ ++++while+((sspsr+&+sspsr_bsy)+);//wait+until+the+busy+bit+is+cleared+ ++++data_add++;+ +++}+ ++SSP_SS(); //deiselect+slave+ }+ 2

6 Receiver' /*Receive+data+to+the+SSP+the+start+address+of+where+the+data+should+ be+stored,+size+of+the+data+must+be+given+*/+ + void+sspreceivedata(unsigned+char+*data_add,unsigned+char+arr_size)+ {+ +++int+i;+ +++SSP_SS();+ +++for(i=;i<arr_size;i++)+ +++{+ +SSPDR+=+x; //dummy+write+ +while((sspsr+&+sspsr_bsy));+//wait+until+the+busy+bit+is+cleared+ +*data_add=+sspdr;++ + +while+((sspsr+&+sspsr_bsy)+);+//wait+until+the+busy+bit+is+ cleared data_add++;+ +++}+ +++SSP_SS();+ }+ 2 USBASPI'Board:'MAX342' 22 USBASPI:'MAX342' Conclusion! SPI 4 wire serial bus protocol! MOSI MISO SS SCLK wires! Full duplex! Multiple slaves, One master! Best for point-to-point streaming data! Easily Supported 23 24