A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application

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1 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application Aibin Yan, Kang Yang, Zhengfeng Huang, Jiliang Zhang, Jie Cui, Xiangsheng Fang, Maoxiang Yi, Xiaoqing Wen, Fellow, IEEE Abstract This paper presents a double-node upset (DNU) self-recoverable latch design for high performance and low power application. The latch is mainly constructed from eight mutually feeding back C-elements and any node pair of the latch is DNU self-recoverable. Using a high speed transmission path and a clock gating technique, the latch has high performance and low power dissipation. Simulation results demonstrate the DNU self-recoverability of the latch and also show that the delay-power-area product of the latch is improved approximately by 81.80% on average, compared with the latest DNU self-recoverable latch designs. Index Terms Circuit reliability, radiation hardening, soft error, double-node upset, single node upset H I. INTRODUCTION ARDWARE security is a major concern for integrated circuit designers and manufacturers [1]. Hardware security problems can be caused by maliciously implanted hardware Trojans or due to the exposure to the space radiation environment. The latter is generally identified as a reliability issue. Radiation effects can manifest as hard errors or soft errors due to the striking of high energy particles like neutrons, protons, alpha particles, and so on [2]. Soft errors are a type of transient errors, resulting from particle striking induced transient faults. In the nanoscale technology, soft errors are rapidly becoming more and more serious [3]. Manuscript received January 29, 2018; revised???; accepted???. Date of publication???; This work was supported in part by the National Natural Science Foundation of China under Grant , , , Anhui University Doctor Startup Fund (J ), Project Team of Anhui Institute of Economic Management (YJKT1417T01) and the Natural Science Foundation of Hunan Province, China (2018JJ3072) (Corresponding author: Jiliang Zhang) Aibin Yan, Kang Yang and Jie Cui are with the School of Computer Science and Technology, Anhui University, Hefei , China. ( abyan@mail.ustc.edu.cn, @qq.com, cuijie@mail.ustc.edu.cn). Zhengfeng Huang, Xiangsheng Fang, Maoxiang Yi are with the School of Electronic Science & Applied Physics, Hefei University of Technology, Hefei , China. ( huangzhengfeng@139.com, @qq.com). Jiliang Zhang is with the College of Computer Science and Electronic Engineering, Hunan University, Changsha , China, ( zhangjiliang@hnu.edu.cn). Xiaoqing Wen is with the Department of Creative Informatics, and the Graduate School of Computer Science and Systems Engineering, Kyushu Institute of Technology, Fukuoka , Japan ( wen@cse.kyutech.ac.jp). In the nanoscale technology, the charge required to change the state of a circuit node is significantly decreased since supply voltage and transistor capacitances are decreased. This implies that the logic state of a circuit node becomes more easily disturbed by glitches resulting from the radiation effect especially when the charges generated by the particle striking in silicon are collected by the source/drain diffusions of CMOS transistors [2]. Hence it is highly important to design soft error tolerant or even soft error self-recoverable integrated circuits [3]. For a sequential element such as a memory cell or a flip-flop, particle striking may result in the state change of a single node, thus leading to a soft error. This is called single node upset (SNU). So far many radiation hardened schemes for effectively tolerating SNUs have been proposed [3-14]. The schemes in [8-10] are about hardening memory cells, flip-flops or static random access memory cells, while others are about hardening latch designs. On the other hand, for the nanoscale technology, the aggressively scaled transistor size and very large scale integration may cause particle striking to induce single event charge collection to affect double adjacent nodes, resulting in double-node upset (DNU) [15-17]. In recent years, researchers have tried to propose many novel schemes to tolerate DNUs [15, 17-25], many of them [19-25] are about hardening latch designs. In order to tolerate a DNU, a feasible approach is to enlarge transistor sizes of a weak node pair; however, the node pair can still be upset especially when the energy of the radiation particle is large enough. Furthermore, layout techniques such as well isolation, node spacing increase [19] and guard rings can also tolerate a DNU; however, these techniques increase circuit design complexity. Therefore, many circuit designers employ radiation hardening by design (RHBD) techniques using spatial redundancy like multiple-modular redundancy or interlocked redundant hold nodes, and they have recently proposed many reliable latch designs for tolerating DNUs [20-25]. However, the recently proposed DNU hardened latch designs also suffer from some serious problems related to DNU self-recoverability or cost-effectiveness. Latch designs in [20-21] are DNU-tolerant but not DNU-self-recoverable since there is at least one node pair that cannot self-recover from a DNU. Latch designs in [22-25] are DNU-self-recoverable; however, they suffer from high costs in terms of transmission

2 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 2 A B O a) b) Fig.1. Schematics of two symbolic types of 2-input C-element. a) 2-input C-element. b) Clock gating based 2-input C-element. delay and power dissipation. This paper describes a DNU-self-recoverable latch design for high performance and low power application. Using eight mutually feeding back C-elements, redundant nodes make the latch DNU-self-recoverable. Using high speed transmission path and a clock gating (CG) technique, the latch has high performance and low power. Simulation results show the self-recoverability and cost effectiveness of the latch. The rest of the paper is organized as follows: Section II reviews typical hardened latch designs. Section III describes the circuit structure, behavior, and principle of the DNU self-recoverability and verification results of the proposed latch design. Section IV presents the comparison results for overheads. Finally, the conclusions are provided in Section V. II. PREVIOUS HARDENED LATCH DESIGNS This section reviews typical radiation hardened latch designs, such as the High performance Low cost Robust (HLR) and HLR-CG [6], self-recoverable, Frequency-aware and Cost-effective (RFC) [12], Double-Node Upset Tolerant (DONUT) [22], Non-Temporally Hardened LaTCH (NTHLTCH) [24], and Double-Node Upset Resilient Latch (DNURL) designs [25]. In these designs, C-elements (CEs) are widely used. Fig. 1 and Fig. 2 show the schematics of the CE and the above-mentioned latch designs, respectively. A B O A. HLR Latch As shown in Fig. 2-a), the HLR latch employs two independent feedback loops connecting to a CE so as to achieve SNU tolerance. The CE can mask any error in any feedback loop. However, the latch cannot tolerate a DNU since if the inputs of the CE are flipped, it would retain invalid data. B. HLR-CG Latch Using four mutually feeding back interlocked CEs as shown in Fig. 2-b), the HLR-CG latch can self-recover from any SNU. However, the latch cannot tolerate a DNU since if the outputs of any two CEs are flipped, it would retain invalid data. C. RFC Latch As shown in Fig. 2-c), the latch is mainly constructed from three mutually feeding back interlocked CEs so as to achieve SNU self-recoverability. However, the latch cannot tolerate a DNU and the reason is similar to that of the HLR-CG latch. D. DONUT Latch The DONUT latch comprises four united DICEs [8] as shown in Fig. 2-d) and it can self-recover from any DNU because of the existence of reliable feedback loops. However, the latch forms the feedback loops even in the transparent mode of operation, resulting in much power dissipation. E. NTHLTCH Latch As shown in Fig. 2-e), the latch mainly comprises nine CEs and more than three inverters to construct many feedback loops so as to ensure DNU self-recoverability. However, the latch is not cost-effective especially in terms of silicon area. F. DNURL Latch As shown in Fig. 2-f), the DNURL latch employs three delta cells, any of which is an RFC latch as shown in Fig. 2-c), to achieve DNU self-recoverability. To reduce overheads in terms of power dissipation and transmission delay, the latch employs clock gating and a high speed path. However, the latch is not cost-effective especially in terms of silicon area. a) b) c) DICE A DICE C DICE B DICE D d) e) f) Fig.2. Schematics of the reviewed latch designs. a) HLR. b) HLR-CG. c) RFC. d) DONUT. e) NTHLTCH. f) DNURL. b b b b SRC1 SRC2 b b SRC3

3 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 3 III. PROPOSED HARDENED LATCH DESIGN A. Circuit Structure and Behavior Fig. 3 shows the schematic of the proposed DNU self-recoverable latch design for High performance and Low power application (referred to as DNURHL). The latch design consists of four transmission gates TG1, TG2, TG3, TG4 and eight 2-input C-elements (CEs). Note that CE2, CE4, CE6 and CE8 are clock gating (CG) based ones. D,,, and are the input, the output, the system clock, and the negative system clock, respectively. Fig. 4 shows the layout of the design. When =1, the latch works in transparent mode; thus, nodes,, N6, and are driven by D through transmission gates and signals can be obtained from nodes,, and N7. It can be seen that,, N6, and are only driven by transmission gates since these CG based CEs cannot output values in the mode. As a result, current competition can be avoided on outputs of CG based CEs, resulting in reduced power dissipation. When =0, the latch works in hold mode; thus, nodes,, N6, and are stopped from being driven by D through transmission gates but instead driven by CG based CEs. As a result, the interlocked feedback loops in the latch are constructed to robustly retain data. It can be seen from Fig. 3 that the feedback rule for the CEs is as follows: In the ordered and circulated CE list <CE1, CE2, CE3, CE4, CE5, CE6, CE7, CE8>, the output of any CE is fed back to one input of the next CE and one input of the triply prior CE. In hold mode, there are totally 8 cases of SNU occurrences since every internal node may be affected by an SNU. In the case where is affected by the SNU and a glitch occurs, the glitch on would be fed back to one of the inputs of CE2 and one of the inputs of CE6, but the other nodes would not be affected since the glitch can be intercepted by CE2 and CE6. Since the inputs of CE1 are not affected by the SNU, can self-recover. Similarly, in above working flow, it can be seen that the latch can self-recover from SNUs for all nodes. As a result, the latch is SNU-self-recoverable. Now consider the case where a node pair is affected by a DNU. There are a total of C 8 2 =28 cases since any two of the internal nodes can be affected by a DNU. If the node distance between the output of one CE to the output of another adjacent CE is denoted by λ, the node distance between the output of one CE to the output of any other CEs can be obtained as and only as λ, 2λ, 3λ, and 4λ. This is because the CEs are symmetrical and circulated as shown in Fig. 3. Therefore, there are only 4 indicative node pairs, i.e., <, >, <, >, <, > and <, >. As for node pairs including the output of the latch, the four indicative node pairs are <N7, >, <N6, >, <, >, and <, >. Obviously, node distances for these node pairs are λ, 2λ, 3λ, and 4λ, respectively, while all other node pairs are just equivalent to the above indicative node pairs for the latch. In the case where <, > is affected by a DNU and glitches occur, according to the feedback rule for the CEs, the glitch on would be fed back to one input of CE2 and one input of CE6, the glitch on would be fed back to one input of N7 CE5 CE4 CE3 N6 CE6 TG2 TG3 N6 D N6 CE2 TG1 CE7 CE8 N7 CE1 Fig. 3. Proposed DNURHL latch design. TG4 Fig. 4. Layout of the proposed DNURHL latch design. CE3 and one input of CE7. Obviously, the one-input-affected but output-not-affected CEs can intercept a glitch, thus the output of CE6 and the output of CE7, i.e. N6 and N7 are correct. Since the correct N6 is fed back to one input of CE3, the output of CE3, i.e.,, is also correct. Besides, since and are correct, can self-recover, and subsequently can self-recover. As a result, the latch is DNU-self-recoverable for <, >. Similarly, <N7, > is also DNU-self-recoverable. Therefore, the latch is DNU-self-recoverable for <, > and <N7, >. In the case where <, > is affected by DNU and glitches occur, according to the feedback rule for the CEs, the glitch on would be fed back to one input of CE2 and one input of CE6, the glitch on would be fed back to one input of CE4 and one input of CE8. Obviously, the one-input-affected but output-not-affected CEs can intercept a glitch, thus the output of CE2, the output of CE4, the output of CE6 and the output of CE8 i.e.,, N6 and are correct. In other words, the inputs of both CE1 and CE3 are correct, thus and can self-recover from the DNU, i.e., the latch is DNU-self-recoverable for <, >. Similarly, <N6, > is also DNU-self-recoverable. Therefore, the latch is DNU-self-recoverable for <, > and <N6, >. Similarly, in the case where <, > or <, > is affected by DNU, the latch is DNU-self-recoverable. Besides, in the case where <, > or <, > is affected by a DNU, the latch is also DNU-self-recoverable. Therefore, the latch is DNU-self-recoverable for all these key node pairs. B. Simulation Results The proposed DNURHL latch was designed in the 22 nm CMOS technology and the detailed simulation conditions are as follows. First, the supply voltage was set to 0.8V and the transistor sizes for the design were as follows: a) the PMOS

4 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 4 Fig. 5. Simulation waveforms for DNURHL considering SNU on key single nodes, N6, N7 and. seen that all the key single nodes can self-recover from an SNU. This demonstrates that the latch is SNU-self-recoverable. Fig. 6 shows the simulation waveforms for DNURHL considering key node pairs <, >, <, >, <, >, and <, >. Note that and D signals are omitted since they are the same as that shown in Fig. 5. As shown in Fig. 6, at 0.3 ns, 0.7 ns, 2.3 ns, 2.7 ns, 4.3 ns, 4.7 ns, 6.3 ns, and 6.7 ns, an equivalent DNU (two simultaneous SNUs) was simulated on <, >, <, >, <, >, <, >, <, >, <, >, <, >, and <, >, respectively. It can be seen that these node pairs can effectively self-recover from a DNU. This demonstrates that all these key node pairs can self-recover from DNUs. Fig. 7 shows the simulation waveforms for DNURHL considering key node pairs <N7, >, <N6, >, <, >, and <, >. At 0.3 ns, 0.7 ns, 2.3 ns, 2.7 ns, 4.3 ns, 4.7 ns, 6.3 ns, and 6.7 ns, an equivalent DNU was simulated on <N7, >, <N6, >, <N7, >, <N6, >, <, >, <, >, <, >, and <, >, respectively. It can be seen that these node pairs can also self-recover from the DNU. This demonstrates that all these key node pairs can self-recover from DNUs. In summary, the above-described simulation results clearly demonstrate the ability of the proposed DNURHL latch to provide the SNU/DNU self-recoverability. Fig. 6. Simulation waveforms for DNURHL considering DNU on key node pairs <, >, <, >, <, > and <, >. Fig. 7. Simulation waveforms for DNURHL considering DNU on key node pairs <N7, >, <N6, >, <, > and <, >. transistors for the CG based CEs had W/L = 130/22 nm but the NMOS ones had W/L = 80/22 nm; b) the PMOS transistors for the normal CEs had W/L = 130/22 nm but the NMOS ones had W/L = 40/22 nm. Second, in error injections, a controllable double-exponential current source model was used and the time constant of the rise and fall of the current pulse was set to 0.1ps and 3ps, respectively. In order to validate the circuit operation under extreme SNUs and DNUs, the worst case injected charge was set to up to 75fC for a single node. From the simulation results for the error-free case, it was found that the operation of the latch was similar to that of a traditional D-latch, i.e., they had the same functions. As shown in Fig. 5, in order to verify the SNU self-recoverability of the proposed latch (DNURHL), SNU injections were conducted on key single nodes, N6, N7, and, respectively. It can be IV. LATCH COMPARISON AND EVALUATION To make a quantitative comparison, the proposed latch design and the reviewed latch designs mentioned in Section II were designed in the same technology using the same simulation conditions as mentioned in Section III.A including supply voltage, temperature, transistor sizes, and so on. Table I shows the detailed comparison results between the proposed latch and the reviewed latch designs. In Table I, the delay is D to transmission delay, i.e., the average of the rise and fall delays of D to. The reason why the D to delay was chosen is that changes along with D but not in transparent mode of operation. In Table I, the power is the average of dynamic and static power consumption, the area is silicon area extracted from layout comparisons, and the DPAP is the delay-power-area product calculated with Eq. (1). DPAP = Delay Power Area (1) It can be seen that from Table I that the top three SNU hardened latch designs have lower overheads in terms of delay, power, area, and DPAP; however, none of them can completely tolerate a DNU since there is at least one node pair that can be flipped, resulting in an invalid output for these designs. On the other hand, compared with the 4 th to 6 th DNU hardened latch designs, ours has low cost, especially in terms of power and DPAP. The reason why the DONUT latch dissipates more power is that, no matter what operation mode (transparent or hold) is, all the feedback loops are constructed for the latch. The reason why the other DNU hardened latch designs dissipate more power is that their silicon area is large. Note that the proposed latch design has the smallest transmission delay compared with the DNU hardened designs. The reason is that a high speed transmission path is used from D to as in designs

5 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 5 TABLE I COMPARISON RESULTS OF SNU AND/OR DNU HARDENED LATCH DESIGNS Latch Name HLR [6] HLR-CG [6] RFC [12] DONUT [22] NTHLTCH [24] Delay (ps) Power (μw) [6, 12, 25]. It can be seen that the delay of the designs [6, 12, 25] is comparable to that of ours. As for silicon area, ours is a little larger than that of the DONUT latch design since the DONUT uses even less transistors and layout. Compared with other DNU hardened designs, ours has the smallest silicon area and hence our DPAP is the smallest. Note that some data are extracted from our previously published work since the simulation conditions are the same. Table II shows the relative overheads in terms of delay (ΔDelay), power (ΔPower), area (ΔArea), and DPAP (ΔDPAP) among the DNU self-recoverable latch designs, and these results are calculated with Eq. (2). Δ = (Compared - Proposed) / Compared 100% (2) It can be concluded from Table II that ours saves much transmission delay when compared with the DONUT and NTHLTCH designs. In addition, ours also saves much power dissipation. Using the comprehensive metric of DPAP, it can be found that the proposed latch design can save about 81.80% DPAP on average compared with the DNU hardened designs. V. CONCLUSIONS As the process technology continues to scale, charge sharing induced DNUs are becoming more and more serious. Since most existing latch designs cannot self-recover from DNUs at low costs, we have proposed a novel low cost and DNU-self-recoverable latch design. Comprehensive simulation results have demonstrated that the proposed latch design is DNU-self-recoverable and cost-effective compared with the state-of-the-art DNU self-recoverable latch designs. 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