DIE-TO-DIE and within-die variations in process parameters

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1 1370 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 6, JUNE 2007 Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS Saibal Mukhopadhyay, Member, IEEE, Keejong Kim, Hamid Mahmoodi, Member, IEEE, and Kaushik Roy, Fellow, IEEE Abstract In nanoscaled technologies, increased inter-die and intra-die variations in process parameters can result in large number of parametric failures in an SRAM array, thereby, degrading yield. In this paper, we propose a self-repairing SRAM to reduce parametric failures in memory. In the proposed technique, on-chip monitoring of leakage current and/or delay of a ring oscillator is used to determine the inter-die process corner of an SRAM die. Depending on the inter-die Vt shift, the self-repair system selects the proper body bias to reduce parametric failures. Simulations using predictive 70-nm device show that the proposed self-repairing SRAM improves design yield by 5% 40%. A test-chip is designed and fabricated in IBM m CMOS technology to successfully demonstrate the operation of the self-repair system. Index Terms Design, failure, SRAM, variation, yield. I. INTRODUCTION DIE-TO-DIE and within-die variations in process parameters can result in functional failures (read, write, access, and hold failures) in SRAM cell (Fig. 1) [1], [2]. The functional failures due to parametric variations (hereafter, referred to as parametric failures) degrades memory yield (i.e., the number of non-faulty chips) [2]. Due to small geometry of the cell transistors, the principal reason for parametric failures is the random dopant fluctuation induced threshold voltage mismatch between neighboring transistors of a cell (i.e., random within-die or intra-die variations) [1], [2]. On the other hand, die-to-die variation in process parameters (say, Vt) can amplify the effect of intra-die variations, thereby, increasing the failure probability of a cell. In particular, low-vt dies has a higher probability of read and hold failures while high-vt dies suffer mostly from access and write failures [3]. Hence, a self-repairing technique in SRAM that reduces read/hold failures in low-vt dies and access/write failures in high-vt dies can considerably improve yield [3]. This can be achieved by using adaptive repairing technique such as application of adaptive body bias (ABB) [3] [6]. Application of reverse body bias Manuscript received December 12, 2005; revised December 18, This work was supported in part by Gigascale System Research Center, Semiconductor Research Corporation under Contract , Intel, and the IBM PhD Fellowship Program. Fabrication of the test-chip was supported by the MOSIS Educational Program. S. Mukhopadhyay is with IBM T. J. Watson Research Center, Yorktown Heights, NY ( mukhopad@us.ibm.com). K. Kim and K. Roy are with the Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN USA ( keejong@ecn.purdue.edu; kaushik@ecn.purdue.edu). H. Mahmoodi is with the School of Engineering, San Francisco State University, San Francisco, CA USA ( mahmoodi@sfsu.edu). Digital Object Identifier /JSSC Fig. 1. SRAM cell storing 0 at node R. (RBB) in low-vt dies increases their Vt, thereby reducing possible read/hold failures in SRAM cells. Similarly, application of forward body bias (FBB) in high-vt dies decreases their Vt, which reduces the number of SRAM cells failing due to access and write failures [3]. To apply self-repairing techniques to SRAM, it is necessary to detect the inter-die Vt corner of a die even under presence of large intra-die variation. In this paper, we propose a self-repairing SRAM that successfully detects the inter-die Vt corners by monitoring the leakage of a memory array or delay of a ring oscillator. Using delay and leakage monitoring, the proposed SRAM apply proper body bias to reduces the number of parametric failures in a die and improves memory yield. The proposed design is first designed and simulated using predictive 70-nm technology [7]. Simulation results show 5% 40% (depending on the inter-die and intra-die Vt variations) yield improvement for a 256-kB SRAM array. The proposed self-repairing SRAM is implemented in IBM m CMOS technology. Design and measurement of the test-chip successfully demonstrate the operation of the self-repair system. II. BACKGROUND: PARAMETRIC FAILURES AND ADAPTIVE REPAIR OF SRAM Random within-die variation in process parameters (principally, Vt variation due to random dopant fluctuations) results in different types of parametric failures in an SRAM cell. The parametric failures in SRAM are principally due to access (reduction /$ IEEE

2 MUKHOPADHYAY et al.: PROCESS VARIATION TOLERANT SELF-REPAIRING SRAM FOR YIELD ENHANCEMENT IN NANOSCALED CMOS 1371 Fig. 2. Effect of inter-die Vt shift and body bias on the failure probabilities. (a) Cell failure probability with inter-die Vt shift. (b) Memory failure probability with inter-die Vt shift. (c) Effect of body bias on cell failure. in the bit-differential produced while accessing the cell), read (data flipping while reading), write (unsuccessful write), and hold (data flipping at a lower supply voltage in standby mode) [2]. An SRAM cell can fail due to any of the above four mechanisms. A column of an SRAM array is defined to be faulty if any of the cells in that column is faulty. An entire SRAM array is said to be faulty (memory failure) if number of faulty column is more than the number of redundant column (assuming column redundancy). Proper sizing of the cell transistor can reduce the failure (due to within-die variation) probability of a cell at nominal inter-die corner [2]. However, the global inter-die variation in process parameter (such as Vt) can amplify the effect of local random variation. To understand this, we first applied a certain amount of Vt shift to all the transistors in an SRAM cell (represents an inter-die Vt shift). Next, we apply random intra-die Vt variation to each transistors in the cell and estimate different failure probabilities using the method proposed in [2]. At low inter-die Vt corner read (lower static noise margin) and hold (higher subthreshold leakage of pull-down transistor) failures are more probable at [2]. At high inter-die Vt corners, due to reduction in the current of the access transistors write and access failures are expected to high [Fig. 2(a), simulation in predictive 70-nm technology]. Hence, failure probability of a cell and an SRAM array strongly depends of the inter-die process variations. At nominal inter-die corner, low cell failure probability (region B), makes memory failure very unlikely as number of faulty columns is more likely to be less than that of redundant columns [Fig. 2(b)]. If negative (large read/hold failures in region A) and positive (large access/write failures in region C) inter-die Vt shifts increase beyond a certain level, memory failure probability becomes very high [Fig. 2(b)]. Hence, shifting of the dies from region A and C to region B (i.e., region B is widened) using adaptive repair technique improves yield [Fig. 2(b)]. Application of body bias can be used for adaptive repair of the dies [3]. For simplicity, we have assumed application of body bias only to NMOS devices of an SRAM cell. Forward body bias reduces Vt of the access transistors thereby reducing access and write failures for high-vt dies in region C. On the other hand, reverse body bias increases Vt of the devices thereby reducing read (higher static noise margin) and hold failures (lower subthreshold leakage) for low-vt dies in region A [Fig. 2(c)]. Hence, proper body bias can reduce the dominant types of failures in dies in region A and C and shift them to region B. Based on the above observation, we propose a self-repairing technique for SRAM by detecting the inter-die Vt corner of a die and apply proper body bias to reduce number of failures. In this approach, detection and correction of global die-to-die variation are used to reduce the effect of local variation, thereby improving the yield. III. LEAKAGE AND DELAY MONITORING FOR DETECTION OF INTER-DIE VT SHIFT To determine the correct body bias to apply to the SRAM chip for yield improvement, the inter-die process corner of a memory chip needs to be determined. The detection of the inter-die Vt corner (in the presence of large intra-die Vt variation due to RDF) of a die can be achieved by monitoring the leakage of a large SRAM array (instead of monitoring the leakage of a single transistor or cell) or delay of a long inverter chain (instead of a single one). Leakage distribution due to random within-die Vt variation of a cell from low inter-die Vt corner can overlap with that of a cell from high inter-die Vt corner [Fig. 3(a)]. However, since leakage of a large SRAM array is the sum of the leakage of all the cells, the leakage distribution of the arrays (due to within-die Vt variation) from different inter-die corners are well separated [Fig. 3(b)]. This essentially follows from the Central Limit Theorem [8]. Similarly, for an inverter chain of small length (say, three), the inter-die shift in the delay can be masked by the intra-die variation [Fig. 4(a)]. However, for a long inverter chain (say, 300) the delay distributions (due to intra-die variations) are well separated [Fig. 4(b)]. We used the following criteria to determine the minimum array size (say, ) required for effective separation (a similar criteria is used to determine minimum length of inverter chain:

3 1372 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 6, JUNE 2007 Fig. 3. Effect of random intra-die Vt variation at different inter-die Vt corners of SRAM. (a) Leakage distribution (due to intra-die variation) of an SRAM cell. (b) Leakage distribution (due to intra-die variation) of the 1-kB SRAM array. (c) Minimum memory size versus intra-die distribution. Fig. 4. Vt-binning with monitoring the delay of an inverter chain. (a) Three-stage inverter chain. (b) 300-stage inverter chain. (c) Minimum number of stages for effective separation. Fig. 3(c) and Fig. 4(c) show that memory array larger than 1 kb and inverter chain more than 300 stages long can provide good separation under reasonable variation. Hence, array leakage and/or delay of long inverter chain area reliable indicator of inter-die Vt corner even under large intra-die variation [3]. IV. SELF-REPAIRING SRAM Let us now discuss the implementation of the proposed self-repairing SRAM using leakage/delay monitors and adaptive body bias. In the proposed scheme, an on-chip process sensor detects the inter-die process corner of the chip and accordingly applies adaptive repair technique (in this case, proper body bias) to fix the parametric failures in that process corner. A. Self-Repairing SRAM Using Leakage Monitoring The schematic of a self-repairing SRAM array with leakage sensor is shown in Fig. 5(a). A current sensor circuit monitors the leakage of the entire SRAM array and generates an (1) output voltage (Vout) that is proportional to the leakage value [Fig. 5(b), simulation result for a simple current mirror circuit at predictive 70-nm technology]. The output of the leakage monitor is compared with the reference voltages corresponding to the different inter-die process corners. Based on the results of this comparison, the body bias selection circuit applies the right body bias to the SRAM array (Fig. 6). A PMOS switch bypasses the leakage monitor during normal mode of operation ( controlled by calibrate signal). The output voltage generated by the leakage monitor is sampled by a set of flip-flops (F/Fs) at the negative going edge of the calibrate signal (which also turns on the bypass PMOS). If an SRAM die is in the low inter-die Vt corner, the output of the leakage monitor (Vout) will be greater than both the reference voltages ( and ) and both comparators generate zero, resulting in application of a reverse body bias (RBB). Similarly, for a die in the high Vt corner, Vout will be less than both and and FBB will applied. For dies in the nominal Vt corner, zero body bias (ZBB) will be applied as. Statistical simulation of the proposed self-repairing is performed in HSPICE using predictive 70-nm technology. First, using Monte-Carlo simulation a large number (10 000) of inter-die Vt shifts are generated for the SRAM array [Fig. 7(a)]. The inter-die Vt distribution results in the inter-die distributions of the memory leakage [Fig. 7(b)], which results in different

4 MUKHOPADHYAY et al.: PROCESS VARIATION TOLERANT SELF-REPAIRING SRAM FOR YIELD ENHANCEMENT IN NANOSCALED CMOS 1373 Fig. 5. Self-repairing SRAM using ABB. (a) Block diagram of self-repairing scheme. (b) Inter-die Vt shift and current monitor output. Fig. 6. Body-bias generation circuit for self-repairing SRAM. (a) Body-bias selection logic. (b) Level converters. Vout voltage for dies in different inter-die corners [Fig. 7(c)]. Finally, based on the comparator (a simple comparator circuit from [10] is used in this simulation) results in each die, the correct body bias is generated [Fig. 7(d)]. In the proposed scheme, the selection of the reference voltages is based on the pre-calibration of the memory leakage at different inter-die process corner. Since, intra-die variation shifts the mean of the leakage distribution from its nominal value, pre-calibration needs to consider the amount of intra-die variation [Fig. 8(a)]. Moreover, spread in Vout due to random intra-die variation needs to be minimized. In our simulation we observed that the Vout distribution for dies at the different Vt boundaries are well separated [Fig. 8(b) for a 1-kB cache with Vt boundaries at 80 mv]. The separation increases with an increase in the Vt boundaries and/or the memory size. However, variation in Vout, coupled with non-zero offset of the comparators, results in a finite probability of misdetection of the inter-die corner of a die. For example, a die which is actually in region A (or C) can be detected as a nominal Vt die if due to within-die Vt variation Vout becomes less than (or more than ). Consequently, instead of applying a RBB (or FBB) the self-repair system will apply a ZBB and the die will not be repaired. Our simulation shows that the probability of this error is around 7% for a 1-kB SRAM array Fig. 7. Operation of the self-repair strategy. (a) Inter-die Vt distribution. (b) Inter-die leakage distribution. (c) Distribution of Vout. (d) Generation of ABB. (LVT: low Vt; NVT: nominal Vt; HVT: high Vt.) even for a large intra-die Vt variation. Increasing the memory size or the Vt window for region B reduces this probability [3]. On the other hand, dies in region B also can be misdetected

5 1374 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 6, JUNE 2007 Fig. 8. Effect of intra-die variation on Vout and the selection of reference voltage. (a) Selection of reference voltage with intra-die variation. (b) Variation of Vout due to intra-die variation at different inter-die process corner. Fig. 9. Delay monitor based self-repair circuit. (a) Circuit configuration. (b) Statistical operation. as in region A (or C) resulting in application of RBB (or FBB). This can shift the die to region A (or C) resulting in yield loss. To understand this let us consider the case where a die is in negative-vt part of ZBB window. As the die shifts towards the region A, its probability of getting misdetected as a low Vt die increases. However, for a nominal Vt die close to region A application of RBB is less likely to shift it to region C (since, region B window is reasonably large). It is easier for the dies closer to the zero Vt point (i.e., middle of the region B) to be shifted to LVT region due to incorrect application of FBB. However, the dies near the middle of region B less likely to be misdetected. Hence, the possibility of yield loss due to transfer of dies from region B to A or C is very low, which is also verified from simulations (assuming large intra-die variation and 50 mv comparator offset). It is evident that increasing array size and Vt boundaries will reduce this error further. B. Self-Repairing SRAM Using Delay Monitoring Fig. 9 shows the delay monitor (a 600-stage-long inverter chain) based self-repair circuit. Since the delay of a 600-stage ring oscillator is significantly higher than the clock period, we can use the clock and a counter-based detection technique. The counter is first initialized to zero state and at the rising edge of the calibrate signal (which needs to be synchronized with the rising edge of the clock) counting begins. The counter is disabled at the rising edge of the signal from the output of the final inverter. The total delay of the path is determined by the state of the counter. Finally, the final state of the counter is compared with pre-calibrated state values representing low-vt and high-vt corners (similar to and ) and proper body bias is applied. Monte Carlo simulation is performed using predictive 70-nm technology to verify the proposed technique. The inter-die Vt distribution gets converted to the distribution of the final state of the counter [Fig. 9(b)]. The digital comparator successfully compares the final counter state with reference states and proper body bias is generated. Since the delay is measured in the quanta of the clock cycle, the number of stages should be large enough to minimize the quantization error (the error can be further minimized using dual-edge triggered counters [11]).

6 MUKHOPADHYAY et al.: PROCESS VARIATION TOLERANT SELF-REPAIRING SRAM FOR YIELD ENHANCEMENT IN NANOSCALED CMOS 1375 Fig. 10. Parametric failures in self-repairing SRAM. (a) Reduction in number of failures in 256-kB memory array using self-repairing SRAM. (b) Yield enhancement using self-repairing SRAM. Fig. 11. Implementation of the proposed self-repairing SRAM. (a) Die photo of the self-repairing SRAM test-chip (technology: 0.13-m, dual-vt triple-well technology, die size: 16 mm, I/O pin: 84, number of transistors: 7 million). (b) Full-chip layout. (c) 16-kB SRAM block layout. (d) Tester circuit layout. The delay monitor based design eliminates the analog components (such as current mirror and comparators). The spread in the output state distribution and the shift in its mean value due to intra-die variation is very low in the delay monitor scheme. This not only minimizes the misprediction errors, but also eliminates the need to consider the amount of random variation during pre-calibration of reference states. Moreover, the delay monitor does not require the additional bypass PMOS. However, the primary drawback of the delay monitor is that linear dependence of delay on Vt reduces the difference between the output states for inverter chains shifted to different inter-die process corners (the difference in leakage is much higher due to exponential dependence of leakage to Vt). The complexity and area overhead of the delay monitor circuit (ring oscillator, counter, and the comparator logic) are also higher compared to the leakage monitor system. We would like to mention that the proposed ABB based yield enhancement technique can also be implemented using off-chip selection and application (using programmable fuses) of body bias voltages. C. Simulation Result for Yield Enhancement The proposed self-repairing SRAM is applied for 64-kB and 256-kB array designed using BPTM 70-nm technology and simulated in SPICE. The size of the transistors in the SRAM cell is first optimized to minimize the cell failure probability at Vt mv (at zero body bias). It is observed that the proposed scheme reduces number of failures in low-vt and high-vt inter-die corners, which widens the low memory failure region resulting in better yield (Fig. 10). The application of the self-repair technique results in 5% 40% improvement in yield over the SRAM array with no body bias (Fig. 10). The effectiveness of the technique improves with an increase in the intra-die and inter-die variations. V. DESIGN OF THE TEST-CHIP AND MEASUREMENT RESULTS The proposed self-repair SRAM is designed and fabricated in IBM m CMOS technology. Fig. 11 shows the die photo and layout of the fabricated chip. The dual-vt option available

7 1376 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 6, JUNE 2007 Fig. 12. Measurement results for a single isolated cell designed in 0.13-m CMOS technology. in the technology is used to emulate inter-die process variations. Two 64-kB SRAMs are implemented, one using low-vt (represents extreme negative Vt shift) and one with high-vt (represents extreme positive Vt shift) devices. In the test-chip, we implemented the leakage monitor based self-repairing system with on-chip body bias generators. Fig. 13. Failure measurement results for 64-kB low-vt and high-vt array fabricated in 0.13-m CMOS technology. (a) Read failures. (b) Hold failures. (c) Bitdifferential (access test). (d) Write failures. High-Vt array shows lower read and hold failures. Low-Vt array shows higher bit-differential (lower access failure, and lower write failures. A. Organization of the Test-Chip The complete design has two 64-kB array. Each of the arrays is divided in four blocks of 16 kb [Fig. 11(b)]. Each 16-kB block contains four blocks of 4-kB array (256 rows 128 columns) with column circuits (i.e., column decoder, read/write multiplexers, pre-charge circuit, and sense amplifiers) and row drivers (essentially a 256 bit shifter). Each 16-kB block also contains a tester circuit (explained in detail later) to test different types of failures [Fig. 11(b) and (c)]. The bypass PMOSes are designed so that they do not come in series with the pre-charge circuit (to reduce pre-charge delay overhead). It should be noted that the read delay is determined by the discharging current through the series connected access and pull-down NMOS devices. Hence, the bypass PMOS does not introduce additional delay penalty. The area overhead associated with the implementation of bypass PMOS transistors is approximately 5%. B. Failure Measurements Results Fig. 12 shows the measured results for read margin (the difference between read voltage and trip point), write margin (the maximum bit-line voltage with which a 0 can written to the node storing 1 ), read current, and hold voltage (the minimum cell voltage to which data can be held) from a single SRAM cell. It can be observed that FBB degrades read margin (higher read failure), and increases hold voltage (higher hold failure). On the other hand, RBB reduces read current (higher access failure) and write margin (higher write failure). It is interesting to note that with RBB, hold voltage increases marginally. However, since RBB reduces the leakage spread significantly, it will reduce the spread in the hold voltage, thereby reducing hold failures. Fig. 13 shows the measured values of a number of different types of failures from low-vt and the high-vt array. The on-chip Fig. 14. Failure measurement results for 64-kB array with adaptive body bias fabricated in 0.13-m CMOS technology. (a) RBB reduces read failures in low-vt array. (b) RBB reduces hold failures in low-vt array. (c) FBB increases bit-differential (lower access failures) in high-vt array. (d) FBB reduces write failures in high-vt array. failure measurement system described later is used for the measurement. First, we modified the measurement conditions to increase the number of failures to a statistical significant number. Next, using that condition we studied the effect of Vt shifts and body bias. A reduction in the cell supply voltage increases the read failure for both high-vt and low-vt array. However, read failure for the high-vt array is lower than the low-vt array [Fig. 13(a)].

8 MUKHOPADHYAY et al.: PROCESS VARIATION TOLERANT SELF-REPAIRING SRAM FOR YIELD ENHANCEMENT IN NANOSCALED CMOS 1377 Fig. 15. Proposed leakage sensor and its operation. (a) Conventional design using diode connected load. (b) Proposed leakage sensor. (c) BIAS generation circuit for the proposed leakage sensor. (d) Sensor output with temperature and Vt change. (e) Effect of intra-die variation on sensor output (simulation result in IBM 0.13-m technology). Fig. 13(b) shows that at different hold voltages, the hold-failures are more for low-vt array compared to the high-vt array. To measure access failure, we measured the bit-differential at the time of sense-amplifier firing. It can be observed that a cell from the high-vt array has lower bit-differential compared to the corresponding cell from the low-vt array [Fig. 13(c)]. This indicates that access failure will be more in the high-vt array. We performed a weak write test to measure write failures. Fig. 13(d) shows the write failure for the high-vt and low-vt array with different voltages for the low bit-line (i.e., weak write test ground). High-Vt array showed higher number of write failures. Hence, the measurement results show that different types of parametric failures are amplified at different inter-die Vt corner. Fig. 14 shows the measurement result which shows the effect of proposed self-repair technique on different cell failures. Based on the proposed scheme, RBB is applied to the low-vt array, which reduces the read and hold failures for that array. On the other hand, FBB is applied to the high-vt array, which results in higher bit-differential (lower access failure) and lower write failure for that array [Fig. 14(c) and (d)]. The failure measurement results validate the effectiveness of the proposed scheme in repairing SRAM array and improving design yield. Fig. 16. Measured current sensor output attached to the 64-kB LVT array. C. Design of the Self-Repair System The self-repair system consists of the leakage sensor, reference voltages, and body bias selection logic. Let us now discuss the implementation of these components.

9 1378 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 6, JUNE 2007 Fig. 17. Reference generator circuit. (a) Circuit schematic. (b) Effect of temperature and inter-die Vt shift (simulation result in 0.13-m CMOS). (c) Measured reference voltage change in supply voltage. 1) Current Sensor Circuit: The current sensing circuit is essentially a current mirror with an active NMOS load (Fig. 15, designed using large devices to reduce RDF effect). The current sensor is designed to have Vout 1.4 V for low-vt array (RBB signal is generated) and Vout 0 V for high-vt array (FBB signal is generated). The diode in the current mirror circuit is designed to be large and distributed in different parts of the array (four diodes are used for each of the 4-kB array with less than 0.01% area overhead) to reduce the effect of within-die random and spatial variability. The leakage sensor output (Vout) in the proposed scheme needs to have low sensitivity to 1) inter-die Vt shift in the sensor transistors, and 2) change in temperature (T). With a diode-connected NMOS load [Fig. 15(a)] positive inter-die Vt shift of the diode at the high-vt corner increases Vout. This reduces the difference in Vout between low and high-vt corners [ Conv. Design in Fig. 15(a)]. Also, due to exponential dependence of array leakage on T, Vout for a high-vt die at high T can be comparable to that of a low-vt die at low-t (Fig. 15). To solve this problem we used active NMOS load with variable bias [Fig. 15(b)]. The bias generator circuit is designed such that the bias increases with T and inter-die Vt shift of sensor transistors (with, and in Fig. 15(c), Vt ). This reduces the resistance of the NMOS load at higher T (lower sensitivity of Vout to T) and higher inter-die Vt (compensates the Vt increase of NMOS load). The transistors M1 M9 are designed to ensure a larger current through at the low-vt corner compared to the high-vt corner. This increases at a faster rate with T for low-vt cases to compensate the higher temperature sensitivity of the array leakage at the low-vt corner. Simulations in m technology show that the proposed sensor reduces the output sensitivity to temperature, inter-die and intra-die Vt variation of sensor transistors (Fig. 15). The leakage sensor is designed to have Vout 1.4 V for low-vt array and Vout 0 V for high-vt array 1.5 V. Measured value of Vout from the sensor monitoring the low-vt array leakage is close to 1.4 V (within 5% of the simulated value) (Fig. 16, array leakage is modified using source-bias). To represent equal inter-die Vt shift, the array and the sensor are Fig. 18. Measured sensor output and reference voltage for the low-vt array for different dies. designed with same types of devices (i.e., the sensor for low-vt array is designed with low-vt devices). As Calibrate switches from high to low during regular operation, the supply of the sensor is gated to minimize its static power dissipation. 2) Reference Generator Circuit: The on-chip reference voltages (0.5 V and 1 V) are designed to have a small positive temperature coefficient (similar to Vout, realized using NMOS and ) and low sensitivity to inter-die Vt shift (Fig. 17). Simulation of the proposed design in IBM m technology shows the small positive temperature coefficient of the reference voltage and its weak sensitivity to the inter-die Vt shift [simulation for the circuits designed using low-vt and high-vt devices, Fig. 17(b)]. Measured values of the reference voltage show low sensitivity to supply variation and low chip-to-chip variation [Fig. 17(c)]. 3) Body-Bias Generation and Application: Measurement results show that the proposed self-repair system can generate proper body bias generation signal based on the obtained sensor output and reference voltages. For example, measurement results from different chips show that the sensor output from low-vt array is higher than the reference voltages (Fig. 18). Hence, monitoring the low-vt array leakage and comparing it

10 MUKHOPADHYAY et al.: PROCESS VARIATION TOLERANT SELF-REPAIRING SRAM FOR YIELD ENHANCEMENT IN NANOSCALED CMOS 1379 Fig. 19. Measured body bias voltage for different chips. (a) Measured value of body bias at different supply voltage. (b) Measured value of body bias obtained from different dies. Fig. 20. Application of body bias. (a) Reverse bias with external bias. (b) Reverse bias with internal bias (longer transition time). with the reference voltages (we implemented a sense-amplifier [13] based comparator to minimize the offset voltage) will generate signal for application of reverse body bias. Let us now consider the design of the multiplexer logic shown in Fig. 6. Let us assume that the FBB generation signal is high (i.e., the die is in high-vt corner) and RBB generation signal (i.e., selection signal for the top pass-transistors) is low. It should be noted that if a negative RBB voltage is applied at the source of the pass transistors even if the gate of the NMOS is 0 V, Vgs of the NMOS is. Since the magnitude of RBB is expected to be larger than Vt of the NMOS, it will weakly turn on the NMOS. Therefore, even if only FBB generation signal is high, the pass transistor corresponding to RBB will also be weakly on. This will reduce the final body voltage from the applied FBB. To solve this problem, we use a simple level converter circuit which changes all logic 0 values from 0 V to the value of applied RBB (Fig. 6). This ensures the NMOS in pass transistor corresponding to RBB selection remains off if RBB selection signal is low. To show the feasibility of the complete on-chip system, we also implemented FBB and RBB generators. To reduce the substrate noise originating from the high activity column (including read/write circuits and sense-amplifiers) and row driver circuits, they were designed in isolated p-well (using the triple-well option) and the array was placed in substrate [6]. Since in the proposed design body bias is applied statically and the high-activity circuits are placed in triple-well, the fluctuation in the body current is low, which simplifies the on-chip design of the body bias generators. Also, the nature of the memory-failure probability curve shown in Fig. 2(b) suggests that a large body bias (upper bounded by maximum tolerable leakage values) can be used since the probability of shifting a die from region A to C (or vice versa) is low (as region B is reasonably wide) [3]. Moreover, the sharp transition of Vt curve at the region boundary also suggests that a small change in the Vt is required to shift a large number of dies from region A and C to region B [3]. From the above observations, we can conclude that the stability requirement of the applied body bias is less severe and only two levels (one positive and one negative) of body bias can give significant yield improvement (a continuous value of output bias is not required from the bias generators). The low stability requirement of the body voltage allowed us to design the bias generators using a reference circuit followed by an operational amplifier [6]. Measured FBB ( 0.5 V) and RBB ( 0.5 V) values from the designed on-chip bias generators show good stability against supply variation (Fig. 19). The measured body bias values from different dies are also close to each other (Fig. 19). Measurement body voltage transition waveforms in Fig. 20 (for RBB application; FBB application also shows similar waveform) shows successful application of proper body bias based

11 1380 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 6, JUNE 2007 Fig. 21. Built-in test circuit for failure measurement. (a) Schematic of the tester. (b) Schematic of the starter block. (c) Simulation waveform of the tester operations (in 0.13-m CMOS technology). on the comparator output using both off-chip and on-chip bias generators. It can be observed that the body voltage transition time is longer for the on-chip bias generator. The transition time for the on-chip generator can be reduced by increasing the drivability of the bias generator at the expense of higher power dissipation. D. Testing Scheme for Failure Measurement To measure the different types of failures in the proposed SRAM array, on-chip variable frequency oscillators and built-in test circuits are designed. The variable frequency on-chip oscillator is designed based on the circuit proposed in [14] and implemented for clock generation. To measure the different types of failures in the proposed SRAM array, built-in test circuits are designed as shown in Fig. 11(d) and 21(a). The heart of the proposed circuit is STARTER [Fig. 21(b)]. Depending on the input signals Reset, Feed, and Clock, this block either simultaneously turns on all the word-lines (which ensures a stable write to the cells) or turns on one word-line at a time (for normal operation). When all the word-lines are turned on simultaneously and enough time is given to ensure a proper write operation. This step essentially initializes all the cells in the array. In the next step, Reset is set to zero and the negative edge of Reset generates a Start pulse with a pulse width equal to that of the Clock (generated using an on-chip/off-chip clock). This pulse propagates through the row driver circuit (which is essentially a 256-bit shifter) to turn on one word-line at a time. This pulse also resets the counter and flag generation circuit [Fig. 21(a)]. At each clock cycle (i.e., when the word-line is on due to the start pulse) the cell in the selected row and column is read and output of the sense-amplifier is compared against the written data (Write-In) (using an XOR circuit). If the read data is different from the written data, the XOR circuit generates a pulse indicating a failure. This sets the output of the flag generation circuit to high and advances the state of the counter. After the start pulse exits from the shifter (i.e., a pulse appears at Srout) the counter is disabled and the counter state is latched. The data stored in the latch indicates the total number of failures while Flag indicates whether at least one failure exists. Fig. 21(c) shows the simulation waveform for the tester operation in IBM m technology. Fig. 22 shows measured waveforms of Reset, Start, Srout, Flag, and Tout during a read failure testing. The Start pulse is generated as soon as Reset goes to 0. Fig. 22(b) shows the Srout signal and generation of the Tout (output of the counter). In this particular case, change of Tout from 0 to 1 indicates that a failure has been registered in the counter. Initialization of the cells is performed at very low frequency to ensure proper write operation. The following read/write operations are performed at the desired speed. For read failure testing, two consecutive reads are performed (second read is performed at low speed to avoid access failure). To test for hold failure, after the initialization (i.e., the slow write), the supply voltage of the array is reduced to the desired hold voltage. After a sufficient time, the voltage is increased

12 MUKHOPADHYAY et al.: PROCESS VARIATION TOLERANT SELF-REPAIRING SRAM FOR YIELD ENHANCEMENT IN NANOSCALED CMOS 1381 ACKNOWLEDGMENT Thanks go to Dr. A. Datta, K. Kang, and D. Park, Purdue University, for helpful discussions and help with the design. REFERENCES Fig. 22. Measured waveforms of the SRAM with built-in tester. (a) Start and Reset. (b) Srout and Tout. back to the operational level and a slow (to avoid access failure) reading is performed to test for hold failures. To predict access failure the bit-differential is measured using a specialized test circuit. It consists of an additional sense-amplifier which is directly operated using the complement of the word-line signal. After the word-line is turned off, the sense amplifier becomes enabled and the voltage of the discharged bitline is compared against an external reference voltage. If the voltage of the discharged bit-line is less than, the OUT is high. On the contrary, if the voltage bit-line is higher than, then the OUT goes low. For a given clock frequency, by finding out the reference voltage at which the OUT is changing, we can measure the bit-differential at the time of sense-amplifier firing. VI. CONCLUSION In this paper, we proposed a self-repairing SRAM using on-chip current and delay monitoring technique. In the proposed SRAM array, array leakage and/or delay of an inverter chain are monitored and used to separate different SRAM dies in appropriate inter-die Vt corners. Adaptive body bias is applied to the dies in the different Vt corners, resulting in a significant reduction in failures. The self-repairing SRAM with leakage monitors was designed and implemented in m CMOS technology. Measurement of the test-chip successfully demonstrated the operation of the self-repair system. Since parametric failures in SRAMs are becoming an increasing problem, the proposed self-repairing SRAM can be very effective in achieving high yield in nanometer technologies. [1] A. Bhavnagarwala et al., The impact of intrinsic device fluctuations on CMOS SRAM cell stability, IEEE J. Solid-State Circuits, vol. 36, no. 4, pp , Apr [2] S. Mukhopadhyay et al., Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS, IEEE Trans. Comput.-Aided Des., vol. 24, no. 12, pp , Dec [3] S. Mukhopadhyay et al., Reliable and self-repairing SRAM in nanoscale technologies using leakage and delay monitoring, in Int. Test Conf. (ITC2005). [4] J. W. Tschanz et al., Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage, IEEE J. Solid-State Circuits, vol. 37, no. 11, pp , Nov [5] J. T. Kao et al., A 175-MV multiply-accumulate unit using an adaptive supply voltage and body bias architecture, IEEE J. Solid-State Circuits, vol. 37, no. 11, pp , Nov [6] K. Itoh, VLSI Memory Chip. New York: Springer, [7] BPTM 70 nm: Berkley Predictive Technology Model. [Online]. Available: [8] A. Papoulis, Probability, Random Variables and Stochastic Process. New York: McGraw-Hill, [9] R. Rao et al., Parametric yield estimation considering leakage variability, in Proc. DAC 2004, Jun. 2004, pp [10] ecircuitcenter. [Online]. Available: Models/V_Limit/ [11] H. Mahmoodi et al., Dual-edge triggered level converting flip-flops, in Proc. ISCAS 2004, vol. 2, pp. II-661 II-664. [12] C. H. Kim et al., On-die CMOS leakage current sensor for measuring process variation in sub-90 nm generations, in Symp. VLSI Circuits 2004, pp [13] B. Wicht et al., Yield and speed optimization of a latch type voltage sense amplifier, IEEE J. Solid-State Circuits, vol. 39, pp , Jul [14] H. R. Lee et al., A fully integrated 0.13-/spl mu/m CMOS 10 Gb Ethernet transceiver with XAUI interface, in IEEE ISSCC 2004 Dig. Tech. Papers. Saibal Mukhopadhyay (S 99 M 07) received the B.E. degree in electronics and telecommunication engineering from Jadavpur University, Calcutta, India, in 2000, and the Ph.D. degree in electrical and computer engineering from Purdue University, West Lafayette, IN, in He is currently a Research Staff Member at the IBM T. J. Watson Research Center, Yorktown Heights, NY. His research interests include analysis and design of low-power and robust circuits in nanometer technologies. Dr. Mukhopadhyay received the IBM PhD Fellowship award for He received the SRC Technical Excellence Award in 2005, the Best in Session award at 2005 SRC TECNCON, Best Paper Awards at 2003 IEEE Nano and 2004 International Conference on Computer Design. (logic and memory). Keejong Kim received the M.S. and Ph.D. degrees in electronic and electrical engineering from Pohang University of Science and Technology (POSTECH) in 1992 and 1997, respectively. He worked at LG-Philips LCD during in TFT-LCD and AMOLED driver circuit design for portable applications. Since 2004, he has been a Postdoctoral Research Engineer in the School of Electrical and Computer Engineering at Purdue University, West Lafayette, IN. His research interests include low-power and robust VLSI circuit design

13 1382 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 6, JUNE 2007 Hamid Mahmoodi (S 00 M 06) received the B.S. degree in electrical engineering from the Iran University of Science and Technology, Tehran, Iran, in 1998, and the M.S. degree in electrical and computer engineering from the University of Tehran, Iran, in He received the Ph.D. degree in electrical and computer engineering from Purdue University, West Lafayette, IN, in He is currently an Assistant Professor of electrical and computer engineering in the School of Engineering at San Francisco State University. His research interests include design of low-power, robust, and high-performance circuits and architectures for nanoscale technologies. He has more than 50 publications in journals and conferences and 5 patents pending. Dr. Mahmoodi was a recipient of the Best Paper Award of the 2004 International Conference on Computer Design and the 2006 IEEE Circuits and Systems Society VLSI Transactions Best Paper Award. Kaushik Roy (SM 95 F 01) received the B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign in He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the Electrical and Computer Engineering Faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently a Professor and holds the Roscoe H. George Chair of Electrical and Computer Engineering. He is Purdue University Faculty Scholar. He is the Chief Technical Advisor of Zenasis Inc. and Research Visionary Board Member of Motorola Labs (2002). His research interests include VLSI design/cad for nanoscale silicon and non-silicon technologies, low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. He has published more than 400 papers in refereed journals and conferences, holds 8 patents, and is co-author of two books on low power CMOS VLSI design. Dr. Roy received the National Science Foundation Career Development Award in 1995, the IBM faculty partnership award, the ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics and Design, and 2005 IEEE Circuits and Systems Society Outstanding Young Author Award (Chris Kim), 2006 IEEE TRANSACTIONS ON VLSI SYSTEMS Best Paper Award. He has been on the editorial board of IEEE DESIGN AND TEST, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, and IEEE TRANSACTIONS ON VLSI SYSTEMS. He was Guest Editor for the Special Issue on Low-Power VLSI in the IEEE DESIGN AND TEST (1994) and IEEE TRANSACTIONS ON VLSI SYSTEMS (June 2000), and IEE Proceedings Computers and Digital Techniques (July 2002).