Programmable Logic Devices (PLDs) >Programmable Array Logic (PALs) >Programmable Logic Arrays (PLAs) PAL/GAL 16V8 CPLD: Altera s MAX 3064 & MAX V
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1 Menu Look into my... Programmable Logic Devices (PLDs) >Programmable Array Logic (PALs) >Programmable Logic Arrays (PLAs) PAL/GAL 16V8 CPLD: Altera s MAX 3064 & MAX V Read Roth: Sections (Sections ) (Optional) Read Lam: Sections 6.4 See examples on web: Lam Ch 6 PLD figs, PAL/GAL info, m3000a.pdf, max5_handbook.pdf 1 See Lam Section 6.4 Programmable Logic Devices and Programmable Logic Arrays (PLA s) In conventional MSOP design, a function of 10 inputs and 8 outputs can be expressed as: >Z i = f (x 0, x 1,..., x 9 ), i = 0, 1,..., 7 X 0 X 1 X 2 X 3 X 4 X 5 X 6 X 7 X 8 X 9 Z 0 Z 1 Z 2 Z 3 Z 4 Z 5 Z 6 Z 7 X i s..... Z i 2 1
2 PLD Shorthand Notation LAM Fig PLA PLA Example Simplified Schematics LAM Fig
3 Simplified Schematics PLA LAM Fig Programmable Logic Devices and Programmable Logic Arrays (PLA s) Q: Any problems with MSOPs? A: Q: Any advantages? A: PLA s are not a new theory, but a systematic technique for realizing combinational logic in 1 package (IC). This allows us to take advantage of LSI (Large-Scaled Integration). 6 3
4 More PLA s Z 0 = A*/C + B Z 1 = A*/B + /A*B LAM Fig PLA Block Diagram N Inputs Inv / Non-Inv Buffers 2*N AND Array (K AND terms) K PLAs OR gates share AND gates, i.e., have access to all the AND gates OR Array M Outputs 8 4
5 PAL Block Diagram N Inputs Inv / Non-Inv Buffers 2*N AND Array (K M-1 terms) AND Array (K M-2 terms) AND Array (K 0 terms) K M-1 K M-2 K 0 OR OR OR Output M-1 Output M-2 Output 0 PALs do NOT share AND gates, i.e., each PAL OR gate has its own AND gates 9 PLA Options PLA s provide you with three options: > Manufacturer programmable (like masked ROM) > Field programmable (by blowing fuse links) PLAs (FPLA) > Electrically erasable (reusable or recyclable) PLAs (EEPLA) Advantages > Small board area, less cost/wires/solder, less stocking costs, reliability, flexibility, secrecy Disadvantages > For FPLA s, just 1 chance, initial cost (programmer required) 10 5
6 82S100 FPLA 16 inputs (I 0 I 15 ) 8 outputs (F 0 F 7 ) Tri-state enable, CE(L) controls all outputs Lam Fig S100 FPLA 16 inputs (I 0 I 15 ) 8 outputs (F 0 F 7 ) Tri-state enable, CE(L) controls all outputs Both activationlevs of all inputs are available Lam Fig 6.14 All ANDs are available to all ORs Tri-state enable 12 6
7 Programmable output If CE = 1, then can select the desired activation level activation-level of the output S i (H) X i = GND XOR[0, S i ] = S i Not driven inputs are high (X i ) X 0 = X and X 1 = /X Lam Fig 6.15 S i (L) X i = Vcc XOR[1, S i ] = /S i 13 Tri-state outputs If CE = 0, then output is tri-stated If CE = 1, then output is not tri-stated Lam Fig 6.15 S i (H) X i = GND XOR[0, S i ] = S i S i (L) X i = Vcc XOR[1, S i ] = /S i 14 7
8 PAL14H4 PALs do NOT share, i.e., they have their own ANDs 14 inputs 4 ANDs per OR 4 outputs (ORs) Lam Fig 6.16 Y = ABC + A /B + /A /B /C Z = A /B + /A B C + B /C 15 PAL Abbreviations The X in the AND all inputs connected, i.e., Z = A*/A*B*/B = 0 AND gate is not used Lam Fig 6.17 Nothing in AND or connected to AND no inputs connected, i.e., Z = 1 So what is the output of this OR gate? 16 8
9 Programmable Array Logic (PAL) PAL is a special case of PLAs PALs have have a fixed OR array (instead of the programmable OR Array for the PLA), i.e., PALs do NOT share (each OR needs its own ANDs) PALs are cheaper than PLA, but less flexible 17 PAL 16V8 16V8B_PAL.pdf 18 9
10 PAL 16V8 16V8B_PAL.pdf 19 16V8 Combinational Mode Option 16V8B_PAL.pdf gal22v10.pdf 20 10
11 16V8 Registered Mode Option 16V8B_PAL.pdf gal22v10.pdf 21 MAX 3064 CPLDs MAX 3064 (m3000a.pdf) > Device Features: Table 1 (page 1) > Device Block Diagram: Figure 1 (page 5) > Device Macrocell: Figure 2 (page 6) > Shareable Expanders: Figure 3 (page 8) > I/O Control Block: Figure 6 (page 11) m3000a.pdf 22 11
12 MAX V CPLDs Ours is a 5M570ZT100C5N (Figure 1-1) > 5M ==> Max V > 570Z ==> 570 Logic Elements > T ==> TQFP (Thin quad flat pack) > 100 ==> Pin count > C ==> Temp range 0 to 85 degrees C > 5 ==> a speed classification (not as fast a 4) > N ==> Lead free MAX 5 Handbook > Device Features: Table 1 (page 2) > Device Block Diagram: Figure 2-1 (page 2-2) > Device Macrocell: Figure 2 (page 6) > Shareable Expanders: Figure 3 (page 8) > I/O Control Block: Figure 6 (page 11) max5_handbook.pdf 23 MAX V CPLDs MAX 5 Handbook >Device Features: Table 1-1 Each of 570 Logic Array Blocks (LABs) have the following 10 Logic Elements (LEs), each with an carry chains LAB control signals A local interconnect A look-up table (LUT) Flash available (8k bits = 1K bytes = 512 x 16 bits) >Device Block Diagram: Figure 2-1 >LAB Structure: Figure 2-3 >Logic Element (LE): Figure 2-6 >LE s can be used as RAM max5_handbook.pdf 24 12
13 The End! 25 13
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