SH66K12. MASK 4-bit Microcontroller with LCD Driver. Features. General Description. Pad Configuration 1 V1.0 SH66K12

Transcription

1 H66K MAK 4-bit Microcontroller with LCD Driver Features H660C-based single-chip 4-bit microcontroller with LCD driver M: 048 X 6 bits AM: 56 X 4 bits (Data memory) peration voltage:.5v - 5.4V 6 CM I/ pins - CM or pen Drain (code option) 4 level subroutine nesting (including interrupts) wo 8-bit timer/counter with pre-divider circuit scillator warm-up timer 4 priority interrupt sources: - xternal interrupt (falling edge) - imer0 interrupt - imer interrupt - ortb interrupt (falling edge) scillator KHz crystal or 6K C (code option) Instruction cycle time: - 4/3.768KHz ( µs) for 3.768KHz C clock - 4/6KHz ( 5µs) for 6KHz C clock LCD driver: - 4 X 6 (/4 duty, /3 bias or /3 duty, / bias) wo low power operation modes: HAL or mode Built-in alarm generator carrier frequency: - KHz or 4KHz (code option) Low power consumption (Iop < 0µA, 3.768KHz, 3V) Bonding option for multi-code software Available in CHI FM eneral Description H66K is a single-chip microcontroller integrated with an H660C 4-bit CU core, AM, timer, alarm generator, LCD driver, I/ port, and program M. ad Configuration C M C M CM CM CI C 43 B 44 D H66K 0 D D D C C C B C0 B3 V D D A 0 A A A 3 B 0 B B V.0

2 H66K Block Diagram MAK M (048 X 6) DAA AM (56 X 4 ) 8-Bit IM () C CI C CU C I/ (3*4) A XMAL IN B, C D A.0 (IN) A.(BD) A. (BD) A.3 LCD AM CMMN DIV CM - CM4 ALAM MN DIV - 6 NA CU AIN VLA & LCD VLA DIVID ad Description ad No. Designation I/ Description -, egment signal output for LCD display. eg - 4 as output ports 3 I est pin internally pull-down.(no connect for user) 4 I ad reset input 5 VDD B0 I 6-9 A0-3 I/ ower pin hare with Bonding option, internally pull-low Bit programmable I/ A.0 could be external interrupt input ( IN ) A., A. could be buzzer output A. (BD), A. (BD ) 0-3 B0-3 I/ Bit programmable I/, vector interrupts (active falling edge) 4-7 C0-3 I/ Bit programmable I/ 8 - D0-3 I/ Bit programmable I/ round pin B I hare with Bonding option, internally pull-high 3 C scillator output pin, connected to crystal oscillator 4 CI I scillator input pin, connected to crystal or external resistor 8-5 CM - 4 Common signal output for LCD display otal 5 pads.

3 H66K Functional Description. CU he CU contains the following function blocks: rogram Counter, Arithmetic Logic Unit (ALU), Carry Flag, Accumulator, able Branch egister, Data ointer (INX, DH, DM, and DL), and tack. (a) C (rogram Counter) he rogram Counter is used to address the K program M. It consists of -bits: age egister (C), and ipple Carry Counter (C0, C9, C8, C7, C6, C5, C4, C3, C, C, C0). he program counter normally increases by one (+) with every execution of an instruction except in the following cases: () When executing a jump instruction (such as JM, BA0, BAC); () When executing a subroutine call instruction (CALL); (3) When an interrupt occurs; (4) When the chip is at the INIIAL mode. he program counter is loaded with data corresponding to each instruction. (b) ALU and CY ALU performs arithmetic and logic operations. he ALU provides the following functions: Binary addition/subtraction (ADC, BC, ADD, UB, ADI, BI) Decimal adjustment for addition/subtraction (DAA, DA) Logic operations (AND,,, ANDIM, IM, IM) Decision (BA0, BA, BA, BA3, BAZ, BC) Logic hift (H) he Carry Flag (CY) holds the ALU overflow, which the arithmetic operation generates. During an interrupt service or call instruction, the carry flag is pushed into the stack and restored back from the stack by the NI instruction. It is unaffected by the NW instruction. (c) Accumulator Accumulator is a 4-bit register holding the results of the arithmetic logic unit. In conjunction with ALU, data is transferred between the accumulator and system register, LCD AM, or data memory can be performed. (d) tack A group of registers used to save the contents of CY & C (0-0) sequentially with each subroutine call or interrupt. It is organized 3 bits X 4 levels. he MB is saved for CY. 4 levels are the maximum allowed for subroutine calls and interrupts. he contents of stack are returned sequentially to the C with the return instructions (NI/NW). tack is operated on a first-in, last-out basis. his 4-level nesting includes both subroutine calls and interrupts requests. Note that program execution may enter an abnormal state if the number of calls and interrupt requests exceeds 4, and the bottom of stack will be shifted out.. M he M can address 048 words X 6 bits of program area from $000 to $7FF. (a) Vector Address Area ($000 to $004) he program is sequentially executed. here is an area address $000 through $004 that is reserved for a special interrupt service routine such as starting vector address. Address Instruction Function $000H JM instruction Jump to service routine $00H JM instruction Jump to xternal interrupt service routine $00H JM instruction Jump to IM0 service routine $003H JM instruction Jump to IM service routine $004H JM instruction Jump to B service routine (B) (b) able Data eference able Data can be stored in program memory and can be referenced by using able Branch (JM) and eturn Constant (NW) instructions. he able Branch egister (B) and Accumulator (AC) is placed by an offset address in program M. JM instruction branch into address ((C - C8) X ( 8 ) + (B, AC)). he address is determined by NW to return look-up value into (B, AC). M code bit7-bit4 is placed into B and bit3-bit0 into AC. 3

4 H66K 3. AM Built-in AM contains of general-purpose data memory, LCD AM, and system register. Data memory, LCD AM, and system register can be direct accessed by in one instruction cycle. Because of its static nature, the AM can keep data after the CU enters or HAL. (a) Data memory, LCD AM, and ystem register he following is the memory allocation map: $000 - $0F: ystem register and I/ $00 - $F: Data memory (56 X 4 bits divided into banks) $300 - $39: LCD AM space (6 X 4 bits) (b) Data ointer he Data ointer can indirectly address data memory. ointer address is located in register DM (3-bits) and DL (4-bits). he addressing range can have 8 locations. seudo index address (INX) is used to read or write Data memory, and then AM address bit9-bit0 comes from DH, DM and DL. (c) Configuration of ystem egister Address Bit 3 Bit Bit Bit 0 /W Description $00 IX I0 I I /W Interrupt enable flags $0 IQX IQ0 IQ IQ /W Interrupt request flags $0-0M. 0M. 0M.0 /W Bit0-: imer0 Mode register $03 - M. M. M.0 /W Bit0-: imer Mode register $04 0L.3 0L. 0L. 0L.0 /W imer0 load/counter register low nibble $05 0H.3 0H. 0H. 0H.0 /W imer0 load/counter register high nibble $06 L.3 L. L. L.0 /W imer load/counter register low nibble $07 H.3 H. H. H.0 /W imer load/counter register high nibble $08 A.3 A. A. A.0 /W A $09 B.3 B. B. B.0 /W B $0A C.3 C. C. C.0 /W C $0B D.3 D. D. D.0 /W D $0C LD3 LD LD LD0 W LD nable Control (LD3-0): 00: LD nable (Default); 00: LD Disable $0D - - B B0 Bonding option $0 B.3 B. B. B.0 /W able Branch egister $0F INX.3 INX. INX. INX.0 /W seudo index register $0 DL.3 DL. DL. DL.0 /W Data pointer for INX low nibble $ - DM. DM. DM.0 /W Data pointer for INX middle nibble $ - DH. DH. DH.0 /W Data pointer for INX high nibble $3 / LCDFF HLM AM /W Bit0: set A., A. as Alarm output Bit: HAVY LAD Mode Bit: LCD off or LCD on Bit3: set LCD segment as output $4 AC3 AC AC AC0 /W Alarm nvelope Control $ DUY /W Bit0: change LCD duty to /4 duty, /3 bias $6 - $F eserved 4

5 H66K ystem egister $0D: Address Bit 3 Bit Bit Bit 0 /W emarks ower-on $0D - - B B0 Bit0: Bonding option 0, internal weak drive Bit: Bonding option, internal weak drive ull low ull high X X 0 Yes X X 0 0 B bond to X X B0 bond to VDD X X 0 B bond to and B0 bond to VDD VDD VDD B B0 B B0 CB B = B0 = 0 B = B0 = VDD VDD B B0 B B0 CB B = 0 B0 = 0 B = 0 B0 = H66K Bonding ption Up to 4 different bonding options is possible for the user's needs. he chip's program has 4 different program flows that will vary depending on which bonding option is used. he readable contents of B and B0 will differ depending on bonding. 5

6 H66K ystem egister $3: Address Bit 3 Bit Bit Bit 0 /W emarks ower on $3 / LCDFF HLM AM /W Bit0: set A., A. as ALAM output Bit: HAVY LAD Mode Bit: LCD ower Control Bit3: set seg - 4 as output ports X X X 0 A., A. as I/ port Yes X X X A., A. as ALAM output X X 0 X No Heavy Load Yes X X X HAVY LAD mode X 0 X X LCD on Yes X X X LCD off 0 X X X eg - 4 as LCD output Yes X X X eg - 4 as output ports HAVY LAD Mode (HLM): his mode is designed for the 3KHz crystal oscillator, so that the oscillation can be maintained in a noisy power environment. he power might drop suddenly when the ALAM is driving a speaker. he HLM is designed to control this power variation. he consumption of power will increase during the use of the HLM mode, but it will not affect the C oscillator. Note: he HLM needs about 5 instruction cycles to set-up the oscillation for 3.768KHz crystal oscillator. ystem egister $4 (AC): Address Bit 3 Bit Bit Bit 0 /W emarks ower n $4 AC3 AC AC AC0 /W ALAM envelope control DC envelope Yes X X X Hz envelope X X X Hz envelope X X X 4Hz envelope X X X 8Hz envelope Default carrier frequency is 4KHz. Can be selected to KHz by code option. WI mode: controls the envelope selection. AD mode can read out current envelope waveforms. Below is the ALAM functional block equivalent circuit diagram. o activate the ALAM function, first switch the AM to ALAM UU mode. After setting AM equal to, then set the proper envelope. When the data writes into AC, the envelope counter will be synchronized at the same time. he programmer can read back the envelope from AC register and make any pattern changes needed by programmer. he ead operation will not affect the alarm output waveform. ption setting 4KHz or KHz φ φ φ3 φ4 φ6 φ7 φ8 φ9 φ0 φ 6Hz 8Hz 4Hz Hz Hz D $4 o ound Mixer CI C /4 ption setting 3KHz or 6KHz W $4 6

7 H66K he programming alarm waveform is shown below: 6Hz 8Hz 4Hz Hz Hz BD UU K or 4K AC = $0 AM = AC = $8 AM = AC = $C AM = AC = $A AM = AC = $F AM = ystem egister $5: Address Bit 3 Bit Bit Bit 0 /W Description ower on $ DUY /W Bit0: LCD duty control. 4. LCD Driver LCD driver = /4 duty, /3 bias LCD driver = /3 duty, / bias Yes he LCD driver contains a controller, voltage generator, 4 common signal pins, and 6 segment driver pins. here are two different driving modes that are programmable, one is /4 duty and /3 bias, and the other is /3 duty and / bias. Driving mode is controlled by register $5H and the power-on status is /3 duty, / bias. he controller consists of display data AM and a duty generator. he LCD data AM is a dual port AM that transfers data to segment pins automatically without a program control. LCD segment - 4 can also be used as output ports, it is selected by the bit3 of system register $3H. When segments - 4 are output ports, data can be written to bit 0 of the same address (300H - 303H). LCD AM can be used as data memory if needed. When the "" instruction is executed, the LCD will be turned off, but the data of LCD AM is the same before executing the "" instruction. Configuration of LCD AM area: (a) When segments - 4 are used as output ports: Address Bit 3 Bit Bit Bit 0 CM4 CM3 CM CM 300H DAA_BI 30H DAA_BI 30H DAA_BI 303H DAA_BI 7

8 H66K (b) When segments - 4 are used as segment outputs: Address Bit 3 Bit Bit Bit 0 CM4 CM3 CM CM 300H 30H 30H H (c) egments 5-6 Address Bit 3 Bit Bit Bit 0 CM4 CM3 CM CM 304H H H H H H AH 30BH 30CH DH H FH H H H H H 35H 36H H H H

9 H66K 5. I/ H66K has 6 I/ pins. ach I/ pins are bit programmable. I/ pins are CM (Default) or pen Drain by code option. (a) A, B, C and D ach of these ports contains 4 bit I/ pins. ort I/ mapping address is shown as follows: Address Bit3 Bit Bit Bit0 $08 A.3 A. A. A.0 $09 B.3 B. B. B.0 $0A C.3 C. C. C.0 $0B D.3 D. D. D.0 If ports are pull-high internally, it is weak drive. he equivalent circuit is below: Wr-ime Data-ut I/ AD Data-In 6. imer H66K has two 8-bit timers. he timer/counter has the following features: - 8-bit up-counting timer/counter. - Automatic re-loads counter. - 8-bit prescaler. - Interrupt on overflow from $FF to $00. he following is a simplified timer block diagram. Fosc/4 -CAL osc YNC 8-BI CUN imer Load egister: ince the register H controls the physical AD and WI operations. lease follow these steps: Write peration: Low nibble first; High nibble to update the counter ead peration: High Nibble first; Low nibble followed. 0M (M) (a) imer0 and imer Configuration and peration Both the imer0 and imer consist of an 8-bit write-only timer load register (L0L, L0H; LL, LH) and an 8-bit read-only timer counter (C0L, C0H; CL, CH). ach of them has low order digits and high order digits. Writing data into the timer load register (L0L, L0H; LL, LH) can initialize the timer counter. he low-order digit should be written first, and then the high-order digit. he timer counter is automatically loaded with the contents of the load register when the high order digit is written or counter counts overflow from $FF to $00. Load eg. L Load eg. H 8-bit timer counter Latch eg. L 9

10 H66K (b) imer0 Interrupt he timer overflow will generate an internal interrupt request, when the counter counts overflow from $FF to $00. If the interrupt enable flag is enabled, then a timer interrupt service routine will start. his can also be used to wake CU from HAL mode. (c) imer mode register he timer can be programmed in several different prescaler ratios by setting imer Mode register (M0, M). he 8-bit counter prescaler output pulses. he imer Mode registers (M0, M) are 3-bit registers used for the timer control as shown in able and able. hese mode registers select the input pulse sources into the timer. able. imer0 Mode egister ($0) M0. M0. M0.0 rescaler Divide atio Clock ource / ystem clock 0 0 / 9 ystem clock 0 0 / 7 ystem clock 0 / 5 ystem clock 0 0 / 3 ystem clock 0 / ystem clock 0 / ystem clock / 0 ystem clock able. imer Mode egister ($03) M. M. M.0 rescaler Divide atio Clock ource / ystem clock 0 0 / 9 ystem clock 0 0 / 7 ystem clock 0 / 5 ystem clock 0 0 / 3 ystem clock 0 / ystem clock 0 / ystem clock / 0 ystem clock 0

11 H66K 7. Interrupt Four interrupt sources are available on H66K: - xternal interrupt (IN share with A.0) - imer0 interrupt - imer interrupt - ort s falling edge detection interrupt ( B ) (a) Interrupt Control Bits and Interrupt ervice: he interrupt control flags are mapped on $00 and $0 of the system register. hey can be accessed or tested by program. hose flags are cleared to 0 at initialization by chip reset. Address Bit3 Bit Bit Bit0 emarks $00 IX I0 I I interrupt enable flags $0 IQX IQ0 IQ IQ interrupt request flags When Ix is set to and the interrupt request is generated (IQx is ), the interrupt will be activated and vector address will be generated from the priority LA corresponding to the interrupt sources. When an interrupt occurs, the C and CY flag will be saved into stack memory and jump to interrupt service vector address. After the interrupt occurs, all interrupt enable flags (Ix) are reset to 0 automatically, so when IQx is and Ix is set to again, the interrupt will be activated and vector address will be generated from the priority LA corresponding to the interrupt sources. (b) Interrupt ervicing equence Diagram: Inst. cycle Instruction xecution N Instruction xecution I Instruction xecution I Interrupt enerated Interrupt Accepted Vector enerated tacking Fetch Vector address eset I.X tart at vector address Interrupt Nesting: During the H660C CU interrupt service, the user can enable any INU enable flag before returning from the interrupt. he servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences. If the interrupt request is ready and the instruction of execution N is I enable, then the interrupt will start immediately after the next two instruction executions. However, if instruction I or instruction I disables the interrupt request or enable flag, then the interrupt service will be terminated. (c) xternal Interrupt (IN ) xternal interrupt is shared with the bit0 of A. When bit3 of system register 0 (IX) is set to, the external interrupt will be enabled, and a falling edge signal on A.0 will generate an external interrupt. (Note: while external interrupt is enabled, writing a 0 to bit0 of A will generate an external interrupt). 8. ystem Clock H66K has one clock source. C is 3.768KHz crystal or 6KHz C determined by code option. he C generates the basic clock pulses that provide the system clock to supply CU and on-chip peripherals (IM0, IM, LCD).

12 H66K Initial tate here are 3 types of system reset.. Hardware reset input. ower on reset 3. Low ower Detection reset Hardware After power-on reset rogram counter $000 CY Undefined Data memory Undefined AC Undefined imer counter 0 imer load register 0 Interrupt nable Flags 0 Interrupt equest Flags 0 LD [3:0] 00

13 H66K Instructions et All instructions are one cycle and one-word instructions. he characteristics are memory-oriented operation. Arithmetic and Logical Instruction Accumulator ype Mnemonic Instruction Code Function Flag Change ADC X (, B) bbb xxx xxxx AC Mx + AC + CY CY ADCM X (, B) bbb xxx xxxx AC, Mx Mx + AC + CY CY ADD X (, B) bbb xxx xxxx AC Mx + AC CY ADDM X (, B) 0000 bbb xxx xxxx AC, Mx Mx + AC CY BC X (, B) bbb xxx xxxx AC Mx + -AC + CY CY BCM X (, B) 0000 bbb xxx xxxx AC, Mx Mx + -AC + CY CY UB X (, B) 000 0bbb xxx xxxx AC Mx + -AC + CY UBM X (, B) 000 bbb xxx xxxx AC, Mx Mx + -AC + CY X (, B) bbb xxx xxxx AC Mx AC M X (, B) 0000 bbb xxx xxxx AC, Mx Mx AC X (, B) 000 0bbb xxx xxxx AC Mx AC M X (, B) 000 bbb xxx xxxx AC, Mx Mx AC AND X (, B) 000 0bbb xxx xxxx AC Mx & AC ANDM X (, B) 000 bbb xxx xxxx AC, Mx Mx & AC H Immediate ype 0 AC [3]; AC [0] CY; AC shift right one bit CY Mnemonic Instruction Code Function Flag Change ADI X, I 0000 iiii xxx xxxx AC Mx + I CY ADIM X, I 000 iiii xxx xxxx AC, Mx Mx + I CY BI X, I 000 iiii xxx xxxx AC Mx + -I + CY BIM X, I 00 iiii xxx xxxx AC, Mx Mx + -I + CY IM X, I 000 iiii xxx xxxx AC, Mx Mx I IM X, I 00 iiii xxx xxxx AC, Mx Mx I ANDIM X, I 00 iiii xxx xxxx AC, Mx Mx & I Decimal Adjust Mnemonic Instruction Code Function Flag Change DAA X xxx xxxx AC; Mx Decimal adjust for add CY DA X xxx xxxx AC; Mx Decimal adjust for sub CY 3

14 H66K ransfer Instruction Mnemonic Instruction Code Function Flag Change LDA X (, B) 00 0bbb xxx xxxx AC Mx A X (, B) 00 bbb xxx xxxx Mx AC LDI X, I 0 iiii xxx xxxx AC, Mx I Control Instruction Mnemonic Instruction Code Function Flag Change BAZ X 000 xxxx xxx xxxx C X if AC = 0 BNZ X 0000 xxxx xxx xxxx C X if AC 0 BC X 00 xxxx xxx xxxx C X if CY = BNC X 000 xxxx xxx xxxx C X if CY BA0 X 000 xxxx xxx xxxx C X if AC (0) = BA X 00 xxxx xxx xxxx C X if AC () = BA X 00 xxxx xxx xxxx C X if AC () = BA3 X 0 xxxx xxx xxxx C X if AC (3) = CALL X 000 xxxx xxx xxxx CY; C + C X (Not include p) NW H, L h hhh llll C ; B hhhh; A llll NI CY;C CY HAL JM X 0p xxxx xxx xxxx C X (Include p) JM 0 C (C-C8) (B) (A) N No peration Where, C rogram counter I Immediate data AC Accumulator Logical exclusive -AC Complement of accumulator Logical CY Carry flag & Logical AND Mx Data memory bbb AM bank p M page = 0 tack B able Branch egister 4

15 H66K Absolute Maximum ating* DC upply Voltage V to + 7.0V Input Voltage V to VDD+ 0.3V perating Ambient emperature C to + 60 C torage emperature C to + 5 C *Comments tresses above those listed under "Absolute Maximum atings" may cause permanent damage to this device. hese are stress ratings only. Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. xposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC lectrical Characteristics (VDD = 3.0V, = 0V, A = 5 C, FC = 3.768KHz, unless otherwise specified) arameter ymbol Min. yp. Max. Unit Conditions perating Voltage VDD V perating Current I 5 0 µa All output pins unload execute N instruction tandby Current IB 4 µa tandby Current IB µa All output pins unload (HAL mode) exclude LCD current All output pins unload ( mode) exclude LCD current Input High Voltage VIH 0.7 X VDD VDD V A, B, C, D Input Low Voltage VIL X VDD V A, B, C, D utput High Voltage VH.3 V A, B, C (IH = 5µA) utput Low Voltage VL 0. V A, B, C (IL = 300µA) utput High Voltage VH. V utput Low Voltage VL 0.9 V utput High Voltage VH3.8 V utput Low Voltage VL3 0. V BD/ BD (set A.and A. to be ALAM output ), IH = ma BD/ BD (set A.and A. to be ALAM output ), IL = ma x, IH = 3µA, - 4 to be output port (for reference only) x, IL = 3µA, - 4 to be output port (for reference only) utput High Voltage VH4.8 V CMx, IH = 8µA (for reference only) utput Low Voltage VL4 0. V CMx, IL = 8µA (for reference only) LCD Lighting ILCD µa HAL mode 5

16 H66K DC lectrical Characteristics (VDD = 5.0V, = 0V, A = 5 C, FC = 3.768KHz, unless otherwise specified) arameter ymbol Min. yp. Max. Unit Conditions perating Voltage VDD V perating Current I 5 30 µa All output pins unload execute N instruction tandby Current IB 5 8 µa tandby Current IB µa All output pins unload (HAL mode) exclude LCD current All output pins unload ( mode) exclude LCD current Input High Voltage VIH 0.7 X VDD VDD V A, B, C, D Input Low Voltage VIL X VDD V A, B, C, D utput High Voltage VH 4.3 V A, B, C (IH = 5µA) utput Low Voltage VL 0.3 V A, B, C (IL = 300µA) utput High Voltage VH. V utput Low Voltage VL.0 V utput High Voltage VH3 4.8 V utput Low Voltage VL3 0.3 V BD/ BD (set A.and A. to be ALAM output ), IH = ma BD/ BD (set A.and A. to be ALAM output ), IL = ma x, IH = 3µA, - 4 to be output port (for reference only) x, IL = 3µA, - 4 to be output port (for reference only) utput High Voltage VH4 4.8 V CMx, IH = 8µA (for reference only) utput Low Voltage VL4 0.3 V CMx, IL = 8µA (for reference only) LCD Lighting ILCD µa HAL mode Note:. peration frequency vs. IB IBX = (Frequency/3.768KHz) * IB * 0.8. peration frequency vs. I IX = (Frequency/3.768KHz) * I * HLM vs. I, IB and IB If HLM =, IX = I *, IBX = IB *, IBX = IB * 6

17 H66K LD Circuitry ( = 0V, A = 5 C, FC = 3.768KHz, unless otherwise specified) arameter ymbol Min. yp. Max. Unit Condition LD-detected Voltage VLD V AC Characteristics (VDD = 3.0V, = 0V, A = 5 C, FC = 3.768KHz, unless otherwise specified) arameter ymbol Min. yp. Max. Unit Conditions scillation tart ime 5 s Halt ime H 0 s IDD reduces to Isb after instruction executing top ime 0 s IDD reduces to Isb after instruction executing Frequency tability F /F M F(3.0)-F(.4) /F(3.0), crystal oscillator (for reference only) Frequency Variation F /F 0 M C = 5-5 (for reference only) AC Characteristics (VDD = 3.0V, = 0V, A= 5 C, FC= 6KHz, unless otherwise specified) arameter ymbol Min. yp. Max. Unit Conditions scillation tart ime ms Halt ime H 0 s IDD reduces to Isb after instruction executing top ime 0 s IDD reduces to Isb3 after instruction executing Frequency tability F /F 0 % F(3.0)-F(.4) /F(3.0), C oscillator (for reference only) Frequency Variation F /F 5 % variation caused by process variation (for reference only) ypical C oscillator esistor vs. Frequency: (for reference only) 600 -F (KΩ) VDD = 3.0V VDD = 5.0V F (KHz) 7

18 H66K iming Waveform /4 duty, /3 bias LCD waveform elect Unselect Light Unlight CMX X CM4 5.65ms 3.9ms VDD3 CM3 CM VDD VDD VDD3 CM CM VDD VDD CM VDD3 CM3 VDD VDD VDD3 CM4 VDD VDD n+ n n VDD3 VDD VDD n+ VDD3 VDD VDD CM4 - n VDD3 VDD VDD -VDD -VDD -VDD3 8

19 H66K /3 duty, / bias LCD waveform elect Unselect Light Unlight CM.7ms 3.9ms CM3 CM CM CM CM VDD VDD VDD VDD n+ n+ CM3 VDD VDD n CM4 n VDD VDD VDD VDD n+ VDD VDD CM - n VDD VDD -VDD -VDD HLM waveform HLM 0 Heavy load N FF ms or more 9

20 H66K Application Circuits (for reference only) H66K chip substrate connects to system ground. A C: 6K C (code option) LCD: /4 duty, /3 bias A - D: I/ 4 X 6 LCD /3 bias VDD 0K - 50K H66K VDD CI A - D A C: 3.768KHz crystal (code option) LCD: /3 duty, / bias B - D: I/ A.0: external interrupt A., A.: ALAM output (carrier frequency: KHz or 4KHz code option) 3 X 6 LCD / bias VDD 0p 0K - 50K A.0 H66K A. A. CI C 3768Hz 0p BUZZ 0

21 H66K Application Circuits (continued) A3 C: 3.768KHz crystal (code option) LCD: /3 duty, / bias B. = utput When VDD is higher than VLCD, reducing VDD to VDD can regulate the voltage. 3 X 6 LCD / bias VDD VDD 0K - 50K CI 0p B. H66K C 3768Hz 0p VDD VDD VDD

22 H66K Bonding Diagram C M C M CM CM H66K 4 3 CI C 43 Y B 44 D (0, 0) X 0 9 D 970µm D D C C C B C0 B3 V D D A 0 A 890µm A A 3 B 0 B B ad No. Designation X Y VDD B A A A A B B B B C C C C D D D D B C CI CM * ubstrate connects to. he bonding wire with diameter of.0mil is recommended. Unit: µm ad No. Designation X Y 6 CM CM CM

23 H66K rdering Information art No. H66KH ackage CHI FM 3

24 H66K eplace Notice: When user replaces H66K with H66 (mask) or H66A (mask), please pay attention to the different between them. he different is: Item H66K H66 H66A LCD driving current No select Low / Normal select by mask option. Low / Normal / High /Higher select by mask option. eset pin internal pull-up resister nable / Disable select by mask option. No reset pin internal pull-up resister. nable / Disable select by mask option 4

25 H66K Data heet evision History Version Content Date.0 riginal ct