DSP VLSI Design. Addressing. Byungin Moon. Yonsei University

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1 Byungin Moon Yonsei University

2 Outline Definition of addressing modes Implied addressing Immediate addressing Memory-direct addressing Register-direct addressing Register-indirect addressing with pre- or post-increment/decrement with indexing And combination of the above two with modulo arithmetic addressing with bit reversal Short addressing modes 1

3 What is? Definition of Refers to the means by which the locations of operands are specified for instructions in general Operands encompass both input data and output data There are various addressing modes on DSPs A particular processor supports a subset of the addressing modes described in the following pages Also, places restrictions on the use of a given mode In many cases, a particular mode can be used with a subset of the instruction set or only one particular instruction It is common for a single instruction to combine two or more addressing modes Related to instruction set orthogonality Address generation unit (AGU) Also called a data address generator (Analog Devices) and control arithmetic unit (AT&T) Perform one or more complex address calculations per instruction in parallel with arithmetic operations on data 2

4 Implied The operand addresses are implied by the instruction with no choice of operand locations Example form AT&T DSP16xx All multiplication operations take their inputs from the multiplier input registers X and Y, and deposit their result into the product register A multiplication operation implies the location of the operands So, The assembly language syntax for a multiplication operation P = X * Y is easily written simply as * 3

5 Immediate The operand itself is encoded in the instruction word or in a separate data word that follows the instruction word Example from ADSP-21xx The constant 1234 is considered to be specified as immediate data and encoded as part of the instruction in in AX0 = 1234 Data size with immediate addressing Small data words Usually encoded in the instruction word specifying the operation, resulting in a single-word instruction Larger data words Placed in a separate memory word from the instruction, resulting a two-word instruction 4

6 Memory-Direct The operand being addressed resides in memory at an address encoded in the instruction word or in a separate data word following the instruction word Example from the ADSP-21xx The data located at address 1000 is loaded into the register AX0 and 1000 is encoded as part of the instruction by AX0 = DM(1000) Address size with immediate addressing Small addresses Usually encoded in the instruction word specifying the operation, resulting in a single-word instruction Larger addresses Placed in a separate memory word from the instruction, resulting a two-word instruction 5

7 Register-Direct Operand being addressed resides in a register specified as part of the instruction Very important in processors where operands for arithmetic operations always or mostly come from registers rather than from memory There is a choice of registers, (whereas with implied addressing the nature of the instruction itself specifies the registers Example from TMS320C3x The value in register R1 is subtracted from the value in register R2 and the result is placed in register R2 by SUBF R1, R2 6

8 Register-Indirect Data being addressed reside in memory, and the address of the memory location containing the data is held in a register specified in the instruction One of the most important addressing modes Works efficiently with array of data Pre- and post-increment and decrement Flexible addressing with relatively few bits Registers for addresses A special group of registers reserved for holding addresses Or general-purpose registers Assembly for Register-indirect addressing *Rn, (Rn), [Rn], etc. There are many variations on register-indirect addressing Example from AT&T DSP32xx The following instruction causes the value stored in the memory location pointed by the contents of the register R5 to be added to the value in the accumulator register A0 A0 = A0 + *R5 7

9 Example of Register-Indirect 8

10 Register-Indirect with Pre- or Post-Increment/Decrement Change the value(s) in the address register(s) in addition to the basic register-indirect addressing capability One class of addressing modes designed to speed access to groups of related memory locations Many DSP applications involve accessing blocks of data in memory Post-increment/decrement Add an increment/decrement of one after the address register is used to access the operand Provide a simple means for stepping through an array of valued stored sequentially in memory Examples from AT&T DSP32xx A0 = A0 + *R5++ (increment) A0 = A0 + *R5-- (decrement) 9

11 Register-Indirect with Pre- or Post-Increment/Decrement Pre-increment/decrement Similar to Post-increment/decrement, but the address register is modified before it is used to access operand Requires an extra instruction cycle to update the address register contents before they are used to address memory Example from Motorola DSP 5600x MOVE X:-(R0), A1 Decrements address register R0 before it is used to point the memory location containing the data value to be moved into the accumulator Registers for pre- or post-increment/decrement A special group of registers or general-purpose registers 10

12 Register-Indirect with Indexing Two values are added together to form an effective address that will be used to access memory At least one of the two values are stored in a register The other value is a constant (offset or index) or a value stored in a register (offset or index register) Example from Motorola DSP5600x MOVE Y1, X: (R6 + N6) causes the value in register Y1 to be moved to the memory location in the X memory space whose address is the sum of the values of registers R6 and N6 (index register) Example from TI TMS320C3x LDI *-AR1(1), R7 computes an effect address by subtracting one from the value in the address register AR1 11

13 Register-Indirect with Indexing Useful when the same program code is used multiple sets of data The index register can be used to point to the beginning of the data set in memory and changed when the program is ready to operate on the next data set The regular address registers can be pre- or post-modified to step through the data in the desired fashion Useful for communicating arguments to subroutines by passing data on the stack Each time a subroutine is called The location pointed to by the stack frame pointer contains the address of the previous stack frame The next location contains the number of arguments Subsequent locations contain the arguments themselves Example from TI TMS320C3x LDI *+AR1(2), R0 could be used by any subroutine to copy its first argument into register R0 12

14 Combination of Increment/Decrement and Indexing Modify the value of the register address by index value (other than one) or the value of the index register Pre or post modification can be supported Index value is added to or subtracted from the address register value Example from the AT&T DSP32xx A0 = A0 + *R5++R17 Adds the value in the memory location pointed to by register R5 to the accumulator and then adds the value stored in register R17 to the value in the address register R6 * An orthogonal ISA (e.g. ARM) may provide three types of bits for various addressing modes * Post/pre bit, update bit, and add/subtract bit 13

15 Register-Indirect with Modulo/Circular Address Arithmetic For circular buffer management Many DSP applications need to mange data buffers Data buffer A section of memory that is used to store data that arrive from an off-chip or from a previous computation until the processor is ready to process the data Generally FIFO Management of data buffers A data buffer is managed by two pointer Write pointer pointing to the location where the next data value to arrive will be written Read pointer pointing to the location containing the next data value that will be read from the buffer Each time a read or write operation is performed the read or write pointer is advanced 14

16 Register-Indirect with Modulo/Circular Address Arithmetic What is modulo addressing? When the read/write pointer reaches the end of the buffer, it is reset to point to the first location in the buffer Time-consuming Modulo addressing is a special addressing capability that allows DSPs to automatically perform the action of checking after each buffer address calculation whether the pointer has reached the end of the buffer Eliminate the need for the programmer to check the read and write pointer to see whether they have reached the end of the buffer and to reset the pointers to the beginning of the buffer one they have reached the end Pre- and/or post-increment register-indirect addressing 15

17 FIFO buffers with Linear and Circular Linear addressing Circular addressing 16

18 Methods for Modulo First, by a pair of a modifier register and a start register Modifier (modulo) register Contains the length of the circular buffer One or several modifier registers Each modifier register is associated with one or more address registers Start register Contains the start address of the data buffer K-word boundary K is the smallest power of 2 that is equal to or greater than the size of the circular buffer TI TMS320C3x and TMS320C4x, and processors from Motorola, Analog Devices, NEC, and DSP Group 17

19 Methods for Modulo Second, start and end registers End register Holds the end addresses of each circular buffer TI TMS320C5x Address registers associated with a circular buffer Only one address register or any address register can be associated with a given circular buffer depending on DSP processors Number of simultaneously active circular buffers AT&T DSP16xx: one TI TMS320C5x: two Motorola DSP561xx: four Motorola DSP5600x and all Analog Devices: eight 18

20 Register-Indirect with Bit Reversal Bit reversal FFT or IFFT, which is frequently used in may DSP applications, has the disadvantage that it either takes its input or leaves its output in a scrambled order The data need to be rearranged to or from natural order at some point Radix-2 FFT (very common form) requires reordering of a particularly simple nature, called bit-reversed ordering Many DSP processors include special hardware to facilitate generating bit-reversed address sequences In ADSP-210xx, the output of one of its address registers can be bit-reversed before being applied to the address bus Reverse-carry arithmetic as an alternative to bit-reversed addressing Reverses the direction in which carry bits propagate AT&T DSP32C and DSP32xx 19

21 Output of an FFT Algorithm Produced in Scrambled Order X(0) X(4) W0 W0 W0 X(0) X(4) X(2) X(1) a + C = a+b X(6) W2 W2 W0 X(5) X(1) X(2) b - x D = (a-b)w X(5) W1 W0 W0 X(6) X(3) X(3) W X(7) W3 W2 W0 X(7) 20

22 Short Modes Short versions that squeeze the instruction and the address into a single instruction word at the expense of some restrictions on the address Short immediate data Small immediate data is encoded in one instruction word Motorola DSP5600x (12 bits long or smaller) Short Memory-direct addressing Small address is encoded in one instruction word Motorola DSP5600x (addresses up to six bits in length) Additional versions with an implied offset Paged Memory-direct addressing Specifies the relative location of the desired word within the page TI TMS320C2x and TMS320C5x Up to 64 Kwords of data memory Short memory-direct addressing up to seven bits Data memory is divided into pages of 128 words each A page is selected by loading a page number into the page pointer register 21