CA226 Advanced Computer Architecture

Transcription

1 Table of Contents Stephen Blott 1

2 Instruction-Set Architectures (ISAs) The functionality of a processor is defined by its: instruction-set architecture (ISA) e.g. 8086, MIPS, ARM, Given the ISA: many possible physical designs are possible the ISA effectively defines the contract between hardware and software 2

3 Four Approaches to ISAs Approaches to ISA differ in their approach to internal memory: stack architecture accumulator architecture general-purpose register (GPRs) architectures: register-memory (RM) memory-memory (MM) 3

4 Stack Architectures Stack architectures: operands for all ALU instructions are implicitly at the top of the stack Example: Push A Push B Add Pop C The only memory operations are Push and Pop. 4

5 Stack Architectures Diagram 5

6 Aside Note Figures from 6

7 Another Example E=(A*B)+(C*D): Push A Push B Mult Push C Push D Mult Add Pop E Note This is essentially the same as operating an RPN Calculator [ wiki/rpn_calculator]. 7

8 Another Example E=(A*B)+(A*D): Push A Push B Mult Push A // fetched again! Push D Mult Add Pop E Note May require additional memory operations. 8

9 Stack Architectures Compact code (just a few bits for each ALU instruction). Specialised addressing for parameters and local variables (e.g. a small offset form the stack pointer). Easy-to-write compilers. Typically require more instructions than a register machine (but resulting code is nevertheless typically denser). Slower than modern GPR machines (there s not much an optimising compiler can do). 9

10 Accumulator Architectures Accumulator architectures: one operand for all ALU instructions is implicitly the accumulator register Example: Load A Add B Store C 10

11 Accumulator Architectures Diagram 11

12 Another Example E=(A*B)+(C*D): Load A Mult B Store E // here Load C Mult B Add E // and here Store E Note That s two additional memory operations. 12

13 Note Both stack and accumulator architectures: are now virtually extinct they: generate too much memory traffic (slow, blocking) make compiler/hardware optimisation difficult 13

14 Example Consider: ` (AxxB)-(BxxC)-(AxxD) ` On a stack architecture: the calculation must be done in (pretty much) one way there may be repeated loads from memory: operands are trapped on the stack On a general-purpose register architecture: the calculation can be done in many ways 14

15 General-Purpose Register (GPR) Architectures GPR trends: more registers more general-purpose registers Why? uniform model for compilers makes possible more compiler optimisations (compiler decides how to make best use of registers) 15

16 GPR: Register-Memory Architectures GPR-RM: CISC is typical of this architecture memory addressing for all/many ALU instructions (usually) complex addressing modes Example: Load R1,A Add R3,R1,B // mixed register/memory addressing Store R3,C 16

17 GPR-RM Diagram 17

18 Another Example E=(A*B)+(C*D): Load R1,A Mult R2,R1,B Load R1,C Mult R3,R1,D Add R4,R2,R3 Store R4,E Note Fewer instructions. Compiler is free to use registers as it likes, and frequently re-use register contents. 18

19 An Unexpected Turn At one point: it was expected that ISAs would become increasingly complex it was even thought C might be supported directly in hardware Note All of which turned out to be wrong! 19

20 Why? it turned out we could write very good compilers (so, complexity at the hardware level wasn t needed) RISC ISAs were better suited to hardware opimisation (particularly instruction-level parallelism via pipelining) 20

21 GPR: Register-Register Architecture GPR-RR: all ALU instructions are register-register all memory operations are load/store (usually) fewer addressing modes Example: Load R1,A Load R2,B Add R3,R1,R2 Store R3,C 21

22 GPR-RR Diagram 22

23 Classification Memory Max. Type Examples Addresses Num. of Operands 0 3 Load-Store Alpha, ARM, MIPS, PowerPC, SPARC, 1 2 Register-Memory IBM 360/370, Intel 8086, 2 2 Memory-Memory Vax 3 3 Memory-Memory Vax 23

24 Instruction Size Two approaches: variable-size instructions fixed-size instructions 24

25 Variable-Size Instructions Examples: 8086, VAX, for 8086, instructions vary from 1 to 17 bytes! 25

26 Variable-Size Instructions 8086 Example 26

27 Variable-Size Instructions Considerations: additional bits required to indicate instruction format multiple steps to fetch and decode instructions: fetch first part, workout how long instruction is, fetch rest, inhibits out-of-order execution optimisations short instructions lead to compact code: especially if they are well chosen and frequently occurring 27

28 Fixed-Size Instructions Examples: MIPS, ARM (both 32 bits for all instructions) Considerations: simple/fast fetch/decode cycle simplifies hardware optimisation (pipelining, out-of-order execution) constrains instruction design: for example, the number of bits available to represent displacement and immediate addresses is limited (see anon) 28

29 Variable-Size Instructions MIPS Example 29

30 Memory Addressing Main memory is: a sequence of linearly addressable bytes Bytes Commonly termed 1 bytes 2 half words (sometimes short words) 4 words 8 double words (or, helpfully, sometimes "words") 30

31 Memory Alignment Usually: memory accesses must usually be memory aligned when not, additional costs are incurred (either in hardware or in software) Example: half words can be accessed efficiently only at addresses which are divisible by 2 words can be accessed efficiently only at addresses which are divisible by 4 31

32 Addressing Modes How, in various ISAs, can bytes in memory be addressed? 32

33 Addressing Mode Register Example: Add R4,R3 // Regs[R4] = Regs[R4] + Regs[R3] Typical usage: values needed are already in registers (or must initially be loaded into registers) 33

34 Addressing Mode Immediate Example: Add R4,#123 // Regs[R4] = Regs[R4] Typical usage: constants 34

35 Addressing Example Example: // Assume i is in a register, say R4 i = i + 123; 35

36 Addressing Mode Displacement Example: Add R4,100(R1) // Regs[R4] = Regs[R4] + Mem[Regs[R1]+100] Typical usage: parameters, local variables (e.g. offset within current stack frame) instance variables (Java) (e.g. offset from address of object) static index into array (e.g. offset from base of array, A[1]) 36

37 Addressing Example Example: Add R4,100(R1) // Regs[R4] = Regs[R4] + Mem[Regs[R1]+100] Example: int func(char *str, int n) { int i = 0; // assume that i is in a register, say R4 // and that R1 is the stack pointer; then // n is at a known offset from R1 i = i + n; } 37

38 Addressing Example Example: Add R4,100(R1) // Regs[R4] = Regs[R4] + Mem[Regs[R1]+100] Example: class Something { String some_string = "Whatever"; int value = 7; } void add_value(int n) { // assume that n is in a register, say R4 // and that R1 is the address of the object; // then value is at a known offset from R1 return n + value; } 38

39 Addressing Mode Register Indirect Example: Add R4,(R1) // Regs[R4] = Regs[R4] + Mem[Regs[R1]] Typical usage: access using a pointer, or a computed memory address special case of displacement addressing (displacement is 0) 39

40 Addressing Mode Indexed Example: Add R4,(R1 + R2) // Regs[R4] = Regs[R4] + Mem[Regs[R1]+Regs[R2]] Typical usage: index into an array (e.g. R1 might contain the base of the array, R2 the offset) 40

41 Addressing Example Example: char vs[] = { 87, 56, 90, 1, 56 }; int total = 0, index = 3; // assume total is in R4 // vs is in R1 // index is in R2 total = total + vs[index]; 41

42 Addressing Mode Direct (or Absolute) Example: Add R4,(120096) // Regs[R4] = Regs[R4] + Mem[120096] Typical usage: accessing static data address constant may need to be large (c.f. limitations on sizes of immediates in fixed-sized instructions) another special case of displacement addressing (the register value is 0) 42

43 Addressing Example Example: static int n = 123; int something() { int i = 7896; } // assume i is in R4 i = i + n; The address of n is (well, it might be) known at compile time. Note Warning: 43

44 This example may not be valid; for example, if the code is position independent. 44

45 Addressing Mode Memory Indirect Example: Add // Regs[R4] = Regs[R4] + Mem[Mem[Regs[R3]]] Typical usage: pointer chasing 45

46 Addressing Example Example: struct { int *ip; } thing; void something() { int tot = 0; // assume tot is in R4 } // assume address of thing is in R3 tot = tot + *(thing->ip); Note Warning: This is a pretty strange example. 46

47 Addressing Mode Autoincrement (or Decrement) Example: Add R4,100(R1) // Regs[R4] = Regs[R4] + Mem[Regs[R1]] // Regs[R1] = Regs[R1] + d // where d is the data size of the access Typical usage: step through arrays (where size of element is d) like register indirect, but with a side effect Note Autodecrement is the same, just with subtraction. 47

48 Addressing Example Example: int a[100]; int i, tot; // assume tot is in R4 // assume address of a[0] is in R1 for (i=0; i<100; i+=1) tot = tot + a[i]; 48

49 Addressing Mode Scaled Example: Add R1,100(R2)[R3] // Regs[R4] = // Regs[R4] + Mem[ Regs[R2] + Regs[R3]*d ] // where d is the data size of the access Typical usage: index into arrays (e.g. R2 might contain the base of the array, R3 the index) 49

50 Addressing Example Example: struct { int x; int y; } a[100]; int i, tot; // assume tot is in R4 // assume the base address of a is in R2 // assume i is in R3 // d is 2*sizeof(int), which may be 8 for (i=0; i<100; i+=1) tot = tot + a[i].x; 50

51 Frequency of Use The addressing modes used in practice are determined by: compilers application characteristics 51

52 Frequency of Use in Practice 52

53 Obviously: we should worry most about the most frequently-occurring modes 53

54 MIPS ALU operations: register addressing only (it s a RISC architecture) Loads and stores: displacement addressing only Mem[Regs[R1]+n] 54

55 MIPS However: displacement addressing can emulate register indirect addressing (just use a displacement of 0) displacement addressing can emulate immediate addressing (just use a register containing the value 0, specifically R0) 55

56 Displacement Addressing (Again) Example: Add R4,100(R1) // Regs[R4] = Regs[R4] + Mem[Regs[R1]+100] Key question: what range of displacements is available? Note This is a major issue for fixed instruction size ISAs like PowerPC, MIPS and ARM. 56

57 MIPS Displacements 57

58 Displacement Addressing Displacements See: here [figures-slidy/picdisplacements.png]. Comments: many displacements are small but a non-negligible number are large, particularly for FP ops most small displacements are positive, most large displacements are negative (these usually refer to different memory segments) (not shown on graph) Note These measurements are from an Alpha machine with 16 bits of displacement available. 58

59 MIPS and PowerPC Immediate values: 16 bits so values from 0 to

60 ARM Immediate values: just 12 bits so values from 0 to 4095 That s not a lot! 60

61 A neat trick of ARM processors An 12-bit ARM immediate value is divided into two parts: 4 bits of rotation 8 bits of immediate value 61

62 The rotation bits 4 bits of rotation: gives 16 possible rotations (of a 32-bit value) This is multiplied by 2 to give: 16 possible rotations for the even values only or rotations of 0 to 30 bits, even values only 62

63 Examples

64 Examples So; while only `2^{12}` values can be encoded the range of possible values is large 64

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