Week 4 Tutorial: Verilog Primer Part 2. By Steve Engels
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1 Week 4 Tutorial: Verilog Primer Part 2 By Steve Engels
2 Reflections on Verilog By now, you ve seen several elements of the Verilog language, but it s good to put them into perspective again. Verilog is used to specify circuit diagrams. ú If you had to describe a circuit diagram in text form, the result would strongly resemble Verilog syntax. I need two AND gates, one with inputs A and B, the other with inputs C and D, with an OR gate whose inputs are the outputs of the two AND gates and with an output called Y wire ab, cd; and(ab, A, B); and(cd, C, D); or(y, ab, cd);
3 More reflections on Verilog If you can describe a circuit diagram, you have the ability to specify your circuit in Verilog! Verilog also tries to provide shorter syntax for describing certain circuits. ú Example: Simple boolean circuits: wire ab, cd; and(ab, A, B); and(cd, C, D); or(y, ab, cd); assign Y = A & B C & D; *Quartus makes these equivalent at compile time!
4 Other simplification syntax What about sequential circuits? ú i.e. circuits involving flip-flops. One way to specify them is using gate design: // A gated D latch module d_latch (D, Clk, Q); input D, Clk; output Q; wire R, S, Qa, Qb /* synthesis keep */ ; nand (R, D, Clk); nand (S, ~D, Clk); nand (Qa, R, Qb); nand (Qb, S, Qa); assign Q = Qa; endmodule
5 Other simplification syntax Another way of specifying this latch is: ú Set Q to the value of D whenever Clk is high. This is based on the concept of polling, where the software keeps checking the values of D and Clk to see if the output Q needs to be updated. The better version is based on interrupts, where the circuit reacts when certain signal values change ú Whenever D or Clkchange, do the following. (D, Clk) begin... end
6 Using always The always keyword provides even more abstraction than boolean equations, but in the end, everything is translated into simple gates. Other related high-level keywords: ú if/else ú for ú case
7 Using always Best to show always through examples. ú Example #1: An RS latch. If R and S are 0 and 0, output is unchanged. If R and S are 1 and 0, Q is set high and Q is set low. If R and S are 0 and 1, Q is set low and Q is set high. If R and S are 1 and 1, Q and Q are both set low.
8 Always example: SR latch module sr_latch(r, S, Clk, Q, Q_not); input R, S, Clk; output reg Q, Q_not; (R, S, Clk) if (Clk & (R S)) begin if (R & ~S) Q_not = 1; else Q_not = 0; if (S & ~R) Q = 1; else Q = 0; end endmodule R S Q Q
9 Using if, else & else if The if and else keywords are most useful within an always block. ú Using them outside the always block doesn t work. ú The if/else statements are meant to turn signals on or off in response to certain conditions. The always statement is needed to tell the Verilog compiler when to test for those conditions. The if, else if and else statements can be nested, just like any other language.
10 if/else, begin and end Just like in other languages, the if condition can be followed by a single statement. If you want the circuit to perform multiple statements in response to a condition, use the begin and end keywords, like braces in C or Java. ú Note: If you forget to use begin and end, the compiler will assume that only the next line belongs in the if statement. if (S & ~R) Q = 1; else Q = 0; if (S & ~R) begin Q = 1; Q_not = 0; end
11 always and initial The always keyword tells the compiler to listen for conditions in certain signals, and make the circuit respond in those cases. The initial keyword does something similar (makes the circuit perform a set of operations), but only when the circuit starts. ú Only occurs once, at beginning. ú Useful for initiating circuit elements.
12 for loops The initial keyword and for loops go well together, as a result. ú for loop syntax is similar to C and Java: reg [15:0] memory [255:0]; integer index; initial begin for(index = 0; index < 256; index = index + 1) begin memory [index] = 0; end end
13 case statements One more important control statement! The case statement works similarly to its Python, C and Java counterparts: case (<variable name>) < case1 > : < statement > < case2 > : < statement >... default : < statement > endcase Good for creating decoders, or reacting to inputs that could have many possible values.
14 case example: 7-seg decoder Easier to specify decoders like the sevensegment decoder using case syntax. ú Result is the same as the version obtained through K-maps and reduction. module SevenSegmentDisplayDecoder(ss_out, bcd_in); output reg [6:0] ss_out; input [3:0] bcd_in; case (bcd_in) 4'h0: ss_out = 7'b ; 4'h1: ss_out = 7'b ; 4'h2: ss_out = 7'b ; 4'h3: ss_out = 7'b ; 4'h4: ss_out = 7'b ; 4'h5: ss_out = 7'b ; 4'h6: ss_out = 7'b ; 4'h7: ss_out = 7'b ; 4'h8: ss_out = 7'b ; 4'h9: ss_out = 7'b ; 4'hA: ss_out = 7'b ; 4'hB: ss_out = 7'b ; 4'hC: ss_out = 7'b ; 4'hD: ss_out = 7'b ; 4'hE: ss_out = 7'b ; 4'hF: ss_out = 7'b ; default: ss_out = 7'b ; endcase endmodule
15 Reflection time Remember: This course is about circuits, not Verilog J However designing and testing these circuits is easier with tools or specification languages. ú Designing complex circuits by wiring chips and gates together can take forever and be full of bugs. ú Designing gate-by-gate in Verilog is faster, reproducible, and yields fewer bugs. ú More powerful keywords like always, if/else and case create the same logic with less work, by simply specifying the behaviour that you want instead of the specific circuit. Like specifying string and dictionary behaviour in Python or C, instead of creating your own objects from scratch.
16 Reflection time Take a moment to think about this! People often get unduly distressed about higher-level Verilog statements. Really though, these statements make life a lot easier, once you get the hang of using these keywords to say what the circuit s behaviourshould be.
17 Storing and assigning data Flip-flops and sequential circuits allow us to design circuits that can store values. ú Some are implicit, in latch-style feedback circuits. ú Others can be made explicit, using reg values. We ve used reg before, in the SR latch example.
18 Storing and assigning data Labels can be given to both wire and reg values. ú Main difference: reg values can drive output; wire values can t. A B module reg_example( a, b, y); input a, b; output y; Y module wire_example( a, b, y); input a, b; output y; wire a, b, y; assign y = a & b; endmodule reg y; wire a, b; ( a or b) begin y = a & b; end endmodule
19 Reg versus wire Driving output? What does that mean? ú Remember that Verilog is used to specify a circuit layout. The wire keyword specifies where an actual wire would be, and connecting two points with a wire (or wire) just makes them logically equivalent. ú A reg (short for register) can actually store a value and drive an output signal. Any always or initial blocks that need to set a value must do so by setting reg values. Similarly, wires can t be reassigned to connect new points together partway through a circuit s operation.
20 Literal values Sometimes you need to assign a set of wire or reg values at the same time. ú Example: the seven-segment display. ú Possible to assign each segment one at a time, but easier to assign them all at once. Literal values in Python and C are values like 42, 3.14 and Hello. Verilog has literal values as well. ú But exactly what does 101 represent in Verilog?
21 Literal values 101 can represent different values, depending on what type of number it is. ú Decimal: 101 = one hundred and one (base 10). ú Binary: 101 base 2 = 5 base 10 ú Hexadecimal: 101 base 16 = 257 base 10 ú (Octal: 101 base 8 = 65 base 10) In Verilog: ú Binary: b101 ú Decimal: d101 ú Hexadecimal: h101
22 Example: seven-seg decoder The instructions in the seven-seg decoder code translate to the following: ú in the case where the four-bit BCD input has a hexadecimal value of 0 ú set the value ss_out to a 7-digit binary value of
23 References Verilog Language Reference Guide: ú Verilog Page: ú Verilog Tutorial: ú
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