Pricing of Derivatives by Fast, Hardware-Based Monte-Carlo Simulation
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1 Pricing of Derivatives by Fast, Hardware-Based Monte-Carlo Simulation Prof. Dr. Joachim K. Anlauf Universität Bonn Institut für Informatik II Technische Informatik Römerstr Bonn WWW: Tel.: Tel.: // Fax: Fax: //
2 Overview Introduction Choices to Implement Algorithms What do we mean by Hardware-Based? Monte-Carlo Simulation as a Sample Implementation Results Summary Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 2
3 My Background Studies of Physics, Cologne and KFA Jülich Statistical problems in solid state physics : Postdoc, Gießen Theory of neural networks : Siemens, Munich Corporate research and development Development of neuro-computer SYNAPSE 1 Verification of neuro-chips MA16 Operating-system & library-software for SYNAPSE today: University of Bonn Leader of working group Technische Informatik (HW-oriented computer science) Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 3
4 Topics of Research Technical Applications Distributed Simulation Unified Unified Representation HW HW SW SW Neural Neural Networks SystemC SystemC VHDL VHDL Bayesian Bayesian Methods Methods HW/SW- HW/SW- Codesign Codesign Acceleration- HW HW Reconfigurable Systems Systems Application: Financial Engineering Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 4
5 Contacts to Industry T-Mobile, Bonn Determination of Position of Mobile Phones DaimlerChrysler, Ulm Recognition of Pedestrians and Passing Cars Bayer, Leverkusen Cooperating Neural Networks for a Corrosion Data Base Generalized Neural Networks with Bayesian Networks EADS, Ottobrunn Reconfigurable Embedded Systems High Level System Design BMW, Munich Optimization of Neural Networks for Motor Control Unit Application of FPGA s in the Motor Control Unit Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 5
6 Choices to Implement Algorithms Several possibilities to implement a certain algorithm Software Hardware Programmable Hardware Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 6
7 Software Implementation Algorithm is implemented using a sequential program running on a standard processor hardware for each possible operation is implemented once (ALU) at each instance of time one of these operations is selected by a machine instruction (program) Advantages one hardware for all algorithms very flexible Disadvantages slow controls e=(a+b)*(c+d) Registers (a,b,c,d,e,f,g) ALU (+, -, *, ) Program Memory (sequence of operations) f=a+b; g=c+d; e=f*g; Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 7
8 Hardware Implementation Algorithm is implemented as a specialized circuit every operation is performed on dedicated hardware Advantages very fast Disadvantages each algorithm needs its own specialized hardware long construction time if a new algorithm has to be implemented same is true, if new and faster technology arises e=(a+b)*(c+d) a b c d + + * e Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 8
9 Solution: Programmable Hardware Algorithm is implemented as a special configuration of a general purpose circuit connections between prefabricated wires are programmable function of calculating elements itself is programmable Advantages fast flexible cheap (general purpose hardware) Disadvantages none! (well, there are some "minor" challenges left, see below) a b + + * e=(a+b)*(c+d) Configuration Memory (loaded into HW at power up time) e * controls c d Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 9
10 What do we mean by Hardware-Based? FPGA s (Field Programmable Gate Arrays) FPGA s are working massively parallel FPGA s are optimized to solve certain problems very fast we use FPGA's of the Xilinx Virtex-II (now) Virtex-4 (later) Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 10
11 FPGA's Characteristics: Programmable Logic Device Two-dimensional matrix-structure of Configurable Logic Blocks (CLB's) CLB's are surrounded by Input/Output blocks ( Pins) to allow communication with environment Single CLB's are used to implement logical functions CLB's can be connected via vertical and horizontal lines of interconnection realization of more complex functions Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 11
12 Xilinx FPGA's (Theoretical Layout) Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 12
13 Configurable Logic Blocks (CLB's) CLB's... have fast connections to their neighbours contain simple logic cells use registers to store intermediate results offer freely configurable function generators Function Generators (FG's) within CLB's are a key element to implement complex functions Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 13
14 Function Generator Schematic Read Address Usage Mode Output Write Address ShiftOut WriteEnable DataIn Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 14
15 Function Generators (FG's) a FG is a configurable distributed memory every CLB has two of them FG's can be used as: Look-Up Tables Shift Registers Distributed Select RAM FG's are capable of implementing any arbitrarily defined Boolean function of four inputs Multiple function generators can be combined to realize more complex functions ( e.g. functions of up to eight inputs) Registers are used to store intermediate results The combination of many CLB's allows the realization of complex functions Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 15
16 Specialized Blocks Multipliers 18x18 -> 36 Bit Multipliers fixed wired, ready to use implement fixed point multiplication in a single clock cycle different FPGA's contain different number of multipliers key element to implement fast algorithms Distributed Block RAM's 1024x18 Bits RAM blocks to store intermediate results configurable to get other organizations PowerPC processors Virtex-II Pro contains up to 4 PowerPC processors Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 16
17 Virtex-II vs. Virtex-4 FPGA's are often compared regarding the number of ASIC-gate-equivalents The number of ASIC-gate-equivalents is determined by the number of logic cells More CLB's more complex functions can be realized The Hardware used at the moment (AVNET board with Virtex-II XC2V1500, SpeedGrade -4) offers logic cells, maximum clock-frequency: 360MHz, 48 multipliers A Virtex-4 device (XC4VSX55) offers logic cells and a maximum clock-frequency of 500MHz, 512 multipliers Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 17
18 How to program an FPGA? Hardware description languages VHDL, Verilog low level, very flexible languages used by engineers SystemC high level language, also used by computer scientists, and more and more by engineers, too open source, C++ class library compilation of the code results in a simulation of the described hardware synthesis tools allow (in principle automatic) compilation to a circuit description place and route tools allocate and wire the circuit to a target FPGA Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 18
19 Sample Implementation Why Monte-Carlo Simulation? easy to implement in FPGA's easy to adapt to new and exotic derivatives implementation in software is relatively slow acceleration by hardware seems to be very useful Our Model underlying modelled as a Wiener process ds = rsdt+σsdw simple payoff functions T (piecewise constant or linear) two arbitrary barriers (e.g. "one touch options") discounted payoffs are averaged) P= exp( rt) PS (, T) T PS (, T) (+ error estimation) Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 19
20 Current Implementation discount factor one value every clock cycle one value every simulation path of underlying... d*p p p 2 2 nd path (antithetic) d*p... p p 2 Mersenne- Twister Pathgenerator Thresholdobserver Payoutfunction Discount Summation Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 20
21 System Architecture FPGA random numbers Path-Generator (underlying) PC (user) Bus Evaluator (derivative) Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 21
22 Parallelization many evaluators may be connected to one path-generator arbitrary many derivatives of a common underlying may be evaluated in parallel limited by size of FPGA only computing time is not affected many path-generators may be used in parallel to speed up the Monte-Carlo calculation of the value of a single derivate Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 22
23 Challenges Arithmetic fixed point arithmetic is currently used for all variables the number of bits and the position of the binary point have to be chosen currently by hand alternatives automatic determination of fixed point format floating point needs much more space on the FPGA logarithmic number system trivial: multiplication, division, roots, powers hard: addition, subtraction (evaluation of a nontrivial function must be performed) Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 23
24 Challenges (2) Function Evaluation functions normally are evaluated table driven large tables are needed if high accuracy is an issue methods exist to reduce table size significantly at the cost of computing latency currently we need about 10 cycles to calculate an arbitrary function in a pipeline Automatic Compilation from SystemC to FPGA does not run smoothly yet a lot of experience is still needed to prepare synthesizable hardware descriptions Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 24
25 FPGA vs. PC Test Setup PC Test Setup Hardware: Dual Opteron 250 2,4 GHz, 4GB RAM, Windows XP Ent. Server bit Edition Software: MBRM Universal Exotic Options Add-In v9.0.2, XPrice called from C++ wrapper Derivative: Exotic Option - European Digital Call Underlying: Current Value 100 Strike 105, Payout if hit 100, Payout if not hit 0 Volatility 20%, Interest rate 3% time to maturity: 1/3 year no external force / dividend Monte-Carlo Sim.: steps, simulations FPGA Test Setup small Virtex-II XC2V1500 on Developer Board, serial connection to Standard PC running at 40 MHz only (for test purposes only) 4 options evaluated in parallel for same underlying mix of plain vanilla and digital options Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 25
26 Evaluation Board small Virtex-II XC2V1500 on developer board serial connection to standard PC Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 26
27 Results MBRM (MB Risk Management) Software 7.84 seconds for pricing one option seconds for pricing four options FPGA implementation 2.56 seconds for pricing four options in parallel Speedup: Results for Price MBRM: FPGA: / results are consistent (error not calculated) Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 27
28 FPGA vs. PC Speedup Current Test Setup Speedup against Opteron server 12 Prediction (still to be demonstrated) *3 if Virtex-II (48 mult.) runs at 120 MHz => 36 *10 for new Virtex-4 SX (512 mult.) => 360 *2 if Virtex-4 runs at 240 MHz => 720 Prediction is conservative higher frequencies should be possible more parallel calculations will fit to a single chip if resources are shared One One FPGA FPGA in in one one Host Host can can be be faster faster than than Opteron servers! does does not not include reconfiguration time time Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 28
29 Possible Applications Real Time Evaluation of Derivatives change of price on underlying triggers the evaluation of many dependent derivatives Risk Management evaluation of value at risk (VAR) for many different scenarios of underlyings (itself a Monte-Carlo calculation) all derivatives in a large portfolio have to be re-evaluated at least the re-evaluation of the derivatives can be accelerated considerably FPGA s are not restricted to those applications! Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 29
30 Arguments against Specialized HW To implement an algorithm in specialized HW is expensive due to long construction time can be done by a HW experts only inflexible when faster HW becomes available it starts all over again But use of standard HW (main stream FPGA's) makes it cheap programming it in SystemC is not that difficult since FPGS's are programmable they are as flexible as SW HW descriptions in SystemC or VHDL remain valid when new FPGA's get to the market Accompanying synthesis tools "compile" the code for the new HW without any changes Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 30
31 Future Work Partially Dynamic Reconfiguration while the FPGA is running, it is technically possible to exchange parts of the circuitry tools are not available yet to exploit this property it would be useful if for example many different types of derivates have to be calculated Implementation of other Algorithms trivial: Path Dependent Derivatives Binomial Tree Algorithms Monte Carlo with Importance Sampling Correlated Random Numbers to Simulate Portfolios Just tell me what you need! Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 31
32 Summary Sample Application Evaluation of Derivatives by Monte Carlo Simulation easy to adapt to new and exotic instruments Speedup of Current Implementation demonstrated against state of the art hardware and professional software: about 12 Expected Speedup with one large FPGA more than 500 current price of an evaluation board: Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 32
33 Discussion Thank you for listening. I think there are some questions. I have questions, too! We have the solution. Where is the problem? Where do you need it most? Prof. Dr. Joachim K. Anlauf, Inst. f. Informatik II, Univ. Bonn 33
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Course: VLSI Circuits (Video Course) Faculty Coordinator(s) : Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology Madras Chennai 600036 Email Telephone : srinis@iitm.ac.in,