(12) United States Patent Ogawa et al.

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1 US B1 (12) Unted States Patent Ogawa et al. (o) Patent No.: (45) Date of Patent: US 7,151,027 Bl Dec. 19, 2006 (54) METHOD AND DEVICE FOR REDUCING INTERFACE AREA OF A MEMORY DEVICE (75) Inventors: Hroyuk Ogawa, Sunnyvale, CA (US); Yder Wu, Campbell, CA (US); Kuo-Tung Chang, Saratoga, CA (US); Yu Sun, Saratoga, CA (US) (73) Assgnee: Spanson LLC, Sunnyvale, CA (US) (*) Notce: Subject to any dsclamer, the term of ths patent s extended or adjusted under 35 U.S.C. 154(b) by 29 days. (21) Appl. No.: 10/859,369 (22) Fled: Jun. 1, 2004 (51) Int. CI. H01L 21/336 ( ) (52) U.S. CI 438/257; 438/238; 438/381; 257/E21; 257/613; 257/694; 257/645 (58) Feld of Classfcaton Search 438/257, 438/258, 238, 381, 647, 657, 734, 735, 954 See applcaton fle for complete search hstory. (56) References Cted U.S. PATENT DOCUMENTS 5,303,185 A * 4/1994 Hazan 365/ ,666,307 A * 9/1997 Chang 365/ ,953,254 A * 9/1999 Pourkeramat 365/ ,037,222 A * 3/2000 Huang et al 438/257 6,808,985 Bl * 10/2004 Lee et al 438/ / Al* 6/2005 MokWes et al 257/315 * cted by examner Prmary Examner Davd Nhu (57) ABSTRACT A method and devce for reducng nterface area of a memory devce. A poly-2 layer s formed above a substrate at an nterface between a memory array and a perphery of the memory devce. The poly-2 layer s etched proxmate to the memory array. The poly-2 layer s etched proxmate to the perphery such that a porton of the poly-2 layer remans at the nterface. 14 Clams, 6 Drawng Sheets

2 U.S. Patent Dec. 19,2006 Sheet 1 of 6 US 7,151,027 Bl 100 Fgure 1 (Pror Art)

3 U.S. Patent Dec. 19,2006 Sheet 2 of 6 US 7,151,027 Bl 200 Perphery Components 210 Memory Array 220 Fgure 2

4 U.S. Patent Dec. 19,2006 Sheet 3 of 6 US 7,151,027 Bl core nterface perphery 31 oa 1 310b Q5, 300 p-302 Faure 3A ~ core ' <. 315 V /' 31 oa I I ' 31 Ob I perphery 4- > I core ' <+ I 7 s* 3 oa l 305 l 1 Faure 3B 312 / / Fgure 3C perphery I >

5 U.S. Patent Dec. 19,2006 Sheet 4 of 6 US 7,151,027 Bl perphery Fgure 3D core ** perphery > l_r Fgure 3E core < Interface Structure perphery > 31 oa U 300 Fgure 3 F

6 U.S. Patent Dec. 19,2006 Sheet 5 of 6 US 7,151,027 Bl Fgure 3G

7 U.S. Patent Dec. 19,2006 Sheet 6 of 6 US 7,151,027 Bl Form a poly-1 layer on a substrate n an nterface area between a memory array and a perphery of a memory devce 420 Apply a delectrc layer over the poly-1 layer I 430 Form a poly-1 layer over the delectrc layer 440 Etch the poly-1 layer and poly-2 layer proxmate to the memory array 450 Etch the poy-2 layer proxmate to the perphery 460 Form spacers proxmate to the memory array and to the perphery Fgure 4

US 7,151,027 Bl METHOD AND DEVICE FOR REDUCING INTERFACE AREA OF A MEMORY DEVICE TECHNICAL FIELD The present nventon relates to the feld of floatng gate devces.

8 US 7,151,027 Bl METHOD AND DEVICE FOR REDUCING INTERFACE AREA OF A MEMORY DEVICE TECHNICAL FIELD The present nventon relates to the feld of floatng gate devces. Specfcally, the present nventon relates to reducng the nterface area between a memory array and a perphery of a memory devce. BACKGROUND ART A modem ntegrated crcut (IC), for example a flash memory devce, may have mllons to hundreds of mllons of devces made up of complex, mult-layered structures that 15 are fabrcated through hundreds of processng steps. Those structures are formed by repeated deposton and patternng of thn flms on a slcon substrate, also known as a wafer. One mportant goal of the semconductor ndustry s to reduce the sze of memory devces. In reducng the sze of 20 operatonal components (e.g., a memory array) and perphery components, an mportant consderaton s the nterface between the operatonal components and perphery components. Current fabrcaton processes for formng memory devces typcally form the operatonal components and the 25 perphery components usng separate processes. For example, when the perphery components are formed only the perphery s etched, and when the memory array s formed, only the memory array s etched. By formng the perphery components and the memory array usng dfferent 30 processes, a number of steps n the nterface area are created. A step exsts where two adjacent structures have a dfferent heght, as shown n FIG. 1. FIG. 1 s a dagram of a sde vew of a porton of an nterface area of an exemplary memory devce 100, n 35 accordance wth the pror art. By usng dfferent processes to form the memory array and the perphery components, respectvely, steps are created. Substrate 110 has been etched wheren two structures 115 and 120 reman. As can be seen, structure 120 s hgher than structure 115. In partcular, the 40 heght of the step s hard to control because the dfferent heghts are created usng dfferent processes. Sdewall spacers are commonly formed after the ndvdual transstors of the memory array have been formed. When the sdewall spacers are formed, strnger spacers (e.g., 45 strnger spacers 130 of FIG. 1) are formed n the nterface area at the steps. A strnger spacer s a small component that s easly peeled or removed from the memory devce. If removed, the debrs may be dsplaced to the memory array or perphery componentry. Ths debrs may result n a yeld 50 loss of performance by the memory array. Furthermore, because t s dffcult to control the heght of the steps, t s also hard to control the heght of the strnger spacers. In order to elmnate the rsks caused by strnger spacer debrs, current memory devces nclude a salcde block 55 fabrcated over the nterface area (e.g., salcde layer 140 of FIG. 1). After transstor formaton, a salcde block s formed over the nterface, requrng an addtonal mask, addng costs to the fabrcaton process. Moreover, the salcde block requres addtonal area of the nterface. In partcular, the 60 area requred by the salcde block consderably lmts the ablty to reduce the sze of the nterface area. DISCLOSURE OF INVENTION Varous embodments of the present nventon, a method and devce for reducng nterface area of a memory devce, 65 are descrbed. In one embodment, a memory devce s fabrcated, n whch a poly-2 layer s formed above a substrate at an nterface between a memory array and a perphery of the memory devce. The poly-2 layer s etched proxmate to the memory array. The poly-2 layer s etched proxmate to the perphery such that a porton of the poly-2 layer remans at the nterface. In one embodment, the porton of the poly-2 layer remanng at the nterface s the same heght as the memory array proxmate to the memory array and the same heght as the perphery proxmate to the perphery, such that step sze s smoothed out reducng the occurrence of strngers from spacer etchng. BRIEF DESCRIPTION OF DRAWINGS The accompanyng drawngs, whch are ncorporated n and form a part of ths specfcaton, llustrate embodments of the nventon and, together wth the descrpton, serve to explan the prncples of the nventon. FIG. 1 s a dagram of a sde vew of a porton of an nterface area of an exemplary memory devce, n accordance wth the pror art. FIG. 2 s a block dagram of a memory devce n accordance wth an embodment of the present nventon. FIGS. 3 A through 3G are dagrams of the sde vew of an exemplary nterface area of a memory devce llustratng steps n a process for formng an nterface structure, n accordance wth an embodment of the present nventon. FIG. 4 s a flowchart llustratng steps n a process for fabrcatng a memory devce, n accordance wth an embodment of the present nventon. The drawngs referred to n ths descrpton should be understood as not beng drawn to scale except f specfcally noted. MODE(S) FOR CARRYING OUT THE INVENTION Reference wll now be made n detal to embodments of the nventon, examples of whch are llustrated n the accompanyng drawngs. Whle the nventon wll be descrbed n conjuncton wth the descrbed embodments, t wll be understood that they are not ntended to lmt the nventon to these embodments. On the contrary, the nventon s ntended to cover alternatves, modfcatons and equvalents, whch may be ncluded wthn the sprt and scope of the nventon as defned by the appended clams. Furthermore, n the followng detaled descrpton of the present nventon, numerous specfc detals are set forth n order to provde a thorough understandng of the present nventon. However, the present nventon may be practced wthout these specfc detals. In other nstances, well-known methods, procedures, components, and crcuts have not been descrbed n detal as not to unnecessarly obscure aspects of the present nventon. The present nventon provdes a method and structure for reducng nterface area between the memory array and the perphery of a memory devce. In one embodment, the boundares of the varous masks used to form a polyslcon layer are adjusted such that a polyslcon nterface structure remans n the nterface. The polyslcon nterface structure s operable to smooth out any steps caused by the etchng. In partcular, the heght of the polyslcon nterface structure s easy to control, elmnatng the creaton of strnger spacers. Furthermore, embodments of the present nventon do not requre a salcde layer, thereby reducng the number of

US 7,151,027 Bl masks needed to fabrcate the memory devce and to allow for a reducton n nterface area. FIG. 2 s a block dagram of a memory devce n accordance wth an embodment of the present nventon.

9 US 7,151,027 Bl masks needed to fabrcate the memory devce and to allow for a reducton n nterface area. FIG. 2 s a block dagram of a memory devce n accordance wth an embodment of the present nventon. Memory devce 200 ncludes a perphery components por- 5 ton 210 and a memory array porton 220. In one embodment, memory devce 200 s a flash memory devce. Although only one memory array 220 s shown n memory devce 200, t s completely vable for there to be more than one memory array 220 beng formed on memory devce In one embodment, memory array 220 s manufactured n a flash memory process that s well known n the art. Included n the manufacture of memory array 220 may be source-dran portons, poly one and poly-2 layers, tunnel oxde, slcon, feld oxde, and the lke. In addton, nterface 15 area 230 of FIG. 2, whch s better llustrated n FIGS. 3A through 3G, ncludes poly-1 and poly-2 layers. FIGS. 3A through 3G are dagrams of the sde vew of an exemplary nterface area of a memory devce llustratng steps n a process for formng an nterface structure (FIG. 3G), n accordance wth an embodment of the present nventon. Specfcally, FIGS. 3A, 3B, 3C, 3D, 3E, 3F and 3G llustrate a process for fabrcatng an nterface structure 360 accordng to one embodment of the present nventon. In one embodment, nterface structure 360 ncludes poly- 25 slcon. In one such embodment, nterface structure 360 ncludes a poly-1 layer and a poly-2 layer. It s understood that FIGS. 3A through 3G are not drawn to scale and that only portons of the substrate 300 and other layers are shown. For smplcty of dscusson and llustra- 30 ton, the process s descrbed for a sngle nterface structure 360, although n actualty multple nterface structures may be formed. Furthermore, although the devce beng formed s referred to as a an nterface structure, t s apprecated that FIGS. 3A 35 through 3G only show an nterface structure n the process of beng formed, and not necessarly a completely formed nterface structure. It s apprecated that other processes and steps assocated wth the fabrcaton of an nterface structure may be performed along wth the process llustrated by 40 FIGS. 3A through 3G; that s, there may be a number of process steps before and after the steps shown and descrbed by FIGS. 3A through 3G. Importantly, embodments of the present nventon can be mplemented n conjuncton wth these other (conventonal) processes and steps wthout sg- 45 nfcantly perturbng them. Generally speakng, the varous embodments of the present nventon can replace a conventonal process wthout sgnfcantly affectng the perpheral processes and steps. Referrng frst to FIG. 3A, n the present embodment, 50 substrate 300, solaton area 305 (e.g., a shallow trenched area), and gate polyslcon ("poly-1") 310a and 3106 are shown n cross secton. In one embodment, solaton area 305 s flled wth S0 2. Lne 302 ndcates the approxmate border between the memory array (e.g., care) and the 55 nterface area. Smlarly, lne 304 ndcates the approxmate border between the nterface area and the perphery. The porton of substrate 300 of the memory array s typcally doped wth n-type and p-type materals to form a number of regons n the memory array. For example, n an n-channel 60 transstor n partcular, n a hgh voltage n-channel transstor the substrate 300 may nclude slcon doped wth a p-type materal, a deep n-well, a hgh voltage p-well, and hgh voltage n-wells. It should be apprecated that the porton of poly that resdes n the nterface and 65 perphery regons may not be needed to form actve transstors, and s therefore optonal. Referrng now to FIG. 3B, n the present embodment, a flm of delectrc materal 315 s appled over substrate 300 and poly-1 310a and 3106, essentally coatng the exposed (upper) surfaces of substrate 300 and poly-1 310a and Dfferent delectrc materals may be used; n one embodment, the delectrc materal ncludes S0 2, and n another embodment the delectrc materal ncludes S 3 N 4. In one embodment a oxde-ntrde-oxde (ONO) delectrc layer s appled. Referrng next to FIG. 3C, n the present embodment, a known process (such as an etch back process) s used to remove selectvely the delectrc materal 315 and poly Sgnfcantly, a porton of the delectrc materal 315 overlyng poly and a porton of substrate 300 s deposted and then selectvely removed. In one embodment, the deposton and removal s necessary for the fabrcaton of transstors of the memory array. In one embodment, notch 312 s etched nto solaton area 305. It should be apprecated that notch 312 s a small trench that s etched as a result of the process used to remove delectrc materal 315 and poly Wth reference to FIG. 3D, n the present embodment, a second polyslcon layer (poly-2) 320 s deposted above delectrc materal 315 and substrate 300. In one embodment, poly-2 layer 320 s used to form a word lne for use n the actve transstor of the memory array. Wth reference next to FIG. 3E, n the present embodment, a known process (such as a stacked gate etch) s used to etch a porton of poly-1 310a, delectrc materal 315, and poly proxmate to the memory array. The etch s used to form ndvdual transstors of from the polyslcon layers. In one embodment, the stacked gate edge uses a stacked gate mask above the nterface regon and the perphery. The etch creates a dstnct boundary between the memory array and the nterface regon. By locatng the stacked gate mask close to the core regon, poly-1 310a and poly reman n the nterface regon. Wth reference next to FIG. 3F, n the present embodment, a known process (such as a second gate etch) s used to etch a porton of poly proxmate to the perphery. The etch s used to form nterface structure 360. In one embodment, the second gate edge uses a second gate mask above the nterface regon and the memory array. The second gate etch creates a dstnct boundary between the memory array and the nterface regon. By locatng the second gate etch close to the perphery regon, only part of the poly n the nterface regon s etched, keepng nterface structure 360, ncludng poly-1 310a and poly-2 320, n the nterface regon. In one embodment, nterface structure 360 s the same heght as the memory array proxmate to the memory array and the same heght as the perphery proxmate to the perphery, such that step sze s smoothed out reducng the occurrence of strngers from spacer etchng. Referrng now to FIG. 3G, the memory devce now ncludes nterface structure 360 as well as transstor 330 and perphery poly It should be apprecated that transstor 330 s the last actve transstor of the memory array next to the nterface area. A flm of delectrc materal 345 s appled over substrate 300, nterface structure 360, transstor 330 and perphery poly-2 340, essentally coatng the exposed (upper) surfaces of substrate nterface structure 360, transstor 330 and perphery poly Dfferent delectrc materals may be used; n one embodment, the delectrc materal ncludes S0 2, and n another embodment the delectrc materal ncludes S 3 N4. A known process (such as an etch back process) s used to remove selectvely the

delectrc materal to form a frst set of spacers 350 along the sde walls of nterface structure 360, transstor 330 and perphery poly-2 340.

10 delectrc materal to form a frst set of spacers 350 along the sde walls of nterface structure 360, transstor 330 and perphery poly In one embodment, a second set of spacers are formed adjacent to the frst spacers 350. FIG. 4 s a flowchart llustratng steps n a process 400 for fabrcatng a memory devce, n accordance wth an embodment of the present nventon. Although specfc steps are dsclosed n process 400, such steps are exemplary. That s, the present nventon s well suted to performng varous other steps or varatons of the steps rected n process 400. US 7,151,027 Bl At step 410, a frst polyslcon layer (e.g., poly-1) s formed on a substrate n an nterface area between a memory array and a perphery of the memory devce. In one embodment, a gate oxde s grown on the substrate. At step 420, n 15 one embodment, a delectrc layer s appled over the frst polyslcon layer. In one embodment, the delectrc layer s an ONO layer. At step 430, a second polyslcon layer (e.g., poly-2) s formed over the delectrc layer. In one embodment, a gate or gate poly s formed over the gate oxde). At step 440, the poly-1 layer and the poly-2 layer are etched proxmate to the memory array. In one embodment, the etchng s accomplshed by performng a stacked gate etch. At step 450, the poly-2 layer s etched proxmate to the 25 perphery, such that an nterface structure ncludng a porton of the poly-1 layer and a porton of the poly-2 layer remans at the nterface. In one embodment, the etchng s accomplshed by performng a second gate etch. Thus, accordng to the varous embodments of the 30 present nventon, the nterface structure s the same heght as the memory array proxmate to the memory array and the same heght as the perphery proxmate to the perphery, such that step sze s smoothed out reducng the occurrence of strngers from spacer etchng. At step 460, spacers are 35 formed proxmate to the memory array and proxmate to the perphery. In one embodment, the spacers are ntrde spacers. To summarze, the descrbed embodments provde a 40 method and structure for reducng nterface area between the memory array and the perphery of a memory devce. In one embodment, the boundares of the varous masks used to form a polyslcon layer are adjusted such that a polyslcon nterface structure remans n the nterface. The polyslcon 45 nterface structure s operable to smooth out any steps caused by the etchng. In partcular, the heght of the polyslcon nterface structure s easy to control, elmnatng the creaton of strnger spacers. Furthermore, embodments of the present nventon do not requre a salcde layer, thereby reducng the number of masks needed to fabrcate the memory devce and to allow for a reducton n nterface area. The foregong descrptons of specfc embodments of the 55 present nventon have been presented for purposes of llustraton and descrpton. They are not ntended to be exhaustve or to lmt the nventon to the precse forms dsclosed, and obvously many modfcatons and varatons are possble n lght of the above teachng. The embodments 60 were chosen and descrbed n order to best explan the prncples of the nventon and ts practcal applcaton, to thereby enable others sklled n the art to best utlze the nventon and varous embodments wth varous modfcatons as are suted to the partcular use contemplated. It s 65 ntended that the scope of the nventon be defned by the Clams appended hereto and ther equvalents What s clamed s: 1. A method for fabrcatng a memory devce, sad method comprsng: formng a poly-2 layer above a substrate at an nterface between a memory array and a perphery of sad memory devce; etchng sad poly-2 layer proxmate to sad memory array; and etchng sad poly-2 layer proxmate to sad perphery such that a porton of sad poly-2 layer remans at sad nterface. 2. The method as rected n clam 1 further comprsng: formng a poly-1 layer above sad substrate at sad nterface, such that sad poly-1 layer s above sad substrate and beneath sad poly-2 layer; etchng sad poly-1 layer proxmate to sad memory array; and etchng sad poly-1 layer proxmate to sad perphery such that a porton of sad poly-1 layer remans at sad nterface. 3. The method as rected n clam 1 wheren sad etchng sad poly-2 layer proxmate to sad memory array s accomplshed by performng a stacked gate etch. 4. The method as rected n clam 1 wheren sad etchng sad poly-2 layer proxmate to sad perphery s accomplshed by performng a second gate etch. 5. The method as rected n clam 1 further comprsng: formng spacers proxmate to sad memory array; and formng spacers proxmate to sad perphery. 6. The method as rected n clam 2 further comprsng formng an ONO layer above sad poly-1 layer such that sad ONO layer s above sad poly-1 layer and beneath sad poly-2 layer. 7. The method as rected n clam 1 wheren sad porton of sad poly-2 layer remanng at sad nterface s a same heght as sad memory array proxmate to sad memory array a same heght as sad perphery proxmate to sad perphery, such that step sze s smoothed out reducng an occurrence of strngers from spacer etchng. 8. A method for fabrcatng a memory devce, sad method comprsng: formng a poly-1 layer above a substrate at an nterface between a memory array and a perphery of sad memory devce; formng a poly-2 layer above sad poly-1 layer at sad nterface; etchng sad poly-1 layer and sad poly-2 layer proxmate to sad memory array; and etchng sad poly-2 layer proxmate to sad perphery, such that an nterface structure ncludng a porton of sad poly-1 layer and a porton of sad poly-2 layer remans at sad nterface. 9. The method as rected n clam 8 wheren sad etchng sad poly-1 layer and sad poly-2 layer proxmate to sad memory array s accomplshed by performng a stacked gate etch. 10. The method as rected n clam 8 wheren sad etchng sad poly-2 layer proxmate to sad perphery s accomplshed by performng a second gate etch. 11. The method as rected n clam 8 further comprsng: formng spacers proxmate to sad memory array; and formng spacers proxmate to sad perphery. 12. The method as rected n clam 11 wheren sad spacers are ntrde spacers.

11 13. The method as rected n clam 8 further comprsng formng an ONO layer above sad poly-1 layer such that sad ONO layer s above sad poly-1 layer and beneath sad poly-2 layer. 14. The method as rected n clam 8 wheren sad nterface structure s a same heght as sad memory array US 7,151,027 Bl 8 proxmate to sad memory array and a same heght as sad perphery proxmate to sad perphery, such that step sze s smoothed out reducng an occurrence of strngers from spacer etchng.

R s s f. m y s. SPH3UW Unit 7.3 Spherical Concave Mirrors Page 1 of 12. Notes

R s s f. m y s. SPH3UW Unit 7.3 Spherical Concave Mirrors Page 1 of 12. Notes SPH3UW Unt 7.3 Sphercal Concave Mrrors Page 1 of 1 Notes Physcs Tool box Concave Mrror If the reflectng surface takes place on the nner surface of the sphercal shape so that the centre of the mrror bulges