CHAPTER 4 PARALLEL PREFIX ADDER

Transcription

1 93 CHAPTER 4 PARALLEL PREFIX ADDER 4.1 INTRODUCTION VLSI Integer adders fnd applcatons n Arthmetc and Logc Unts (ALUs), mcroprocessors and memory addressng unts. Speed of the adder often decdes the mnmum clock cycle tme n a mcroprocessor. The need for a Parallel Prefx Adder (PPA) s that t s prmarly fast when compared wth a rpple carry adder. PPA s a famly of adders derved from the commonly known carry look ahead adders. These adders are suted for addtons wth wder word lengths. PPA crcuts use a tree network to reduce the latency to O(log 2 n ) where n represents the number of bts. Ths chapter deals wth the desgn proposal and mplementaton of new prefx adder archtecture for 8-bt, 16-bt, 32-bt and 64-bt addton. The proposed archtectures have the least number of computaton nodes when compared wth exstng one s. Ths reducton n hardware of the proposed archtectures helps to reap a beneft n the form of reduced power and power-delay product. The proposed archtectures are realzed usng three schemes namely Scheme I, Scheme II and Scheme III. Scheme III Consumes least power when compared to Scheme I and Scheme II. Scheme I performs computaton at a faster rate when compared wth other schemes. 4.2 RELATED BACKGROUND A varety of prefx adders are dscussed n the lterature to acheve area and performance optmzaton. Condtonal sum addton logc for prefx

2 94 addton proposed by Sklansky (1960) offers a mnmum depth prefx network at the cost of ncreased fan-out for certan computaton nodes. The algorthm nvented by Kogge and Stone (1973) has both optmal depth and low fan-out but produces massvely complex crcut realzatons and also accounts for large number of nterconnects. The algorthm proposed by Brent and Kung (1982) uses less computaton nodes but possesses maxmal depth whch accounts for ncreased latency. A general method to construct a prefx network wth slghtly hgher depth when compared wth Sklansky topology s proposed by Ladner and Fscher (1980). Ths method reduces the maxmum fan-out for computaton nodes n the crtcal path. The prefx adder proposed by Han and Carlson (1987) combnes Brent-Kung and Kogge-Stone adders n-order to acheve a trade-off between logc depth, nterconnect count and number of computaton nodes. Reto Zmmermann (1996) proposed a heurstc approach for prefx adder optmzaton usng depth controlled compresson and expanson. Matthew Zegler and Stan (2001) proposed prefx adder structures wth a maxmum fan-out of two for mnmzng the area-delay product. Knowles (2001) presented a class of logarthmc adders wth mnmum depth by allowng the fan-out to grow. Algorthm for generatng prefx carry trees proposed by Andrew Beaumont-Smth and Cheng-Chew Lm (2001) uses hgher valency prefx cells n the ntal stages of the archtecture to accomadate less number of prefx cells n the crtcal path and to acheve less nterconnect length. An algorthmc approach to generate rregular PPA proposed by Janhua Lu et al (2003) acheves mnmal delay for a gven profle of nput sgnals. The use of hgher valency prefx cells for standard prefx archtectures such as Brent-Kung, Sklansky, Ladner Fscher, Kogge-Stone and Han-Carlson was proposed by Harrs (2004). Ths leads to reduced number of logc levels at the expense of greater fan-n at each level. A zero defcent PPA wth mnmal depth for a gven wdth was proposed by Hakun Zhu et al (2005). The parallel prefx Lng adder proposed

3 95 by Gorgos Dmtrakopoulos and Dmtrs Nkolos (2005) save one logc level of mplementaton and reduce fan-out requrements of the desgn by modfyng the prefx equatons. Zhanpen Jn et al (2005) proposed a modfed 64-bt Kogge-Stone based PPA usng clocked domno logc to mprove the performance. Sparse tree bnary adder proposed by Yan Sun et al (2006) combnes the benefts of prefx adder and carry select adder to yeld a smaller power-delay product. An nteger lnear programmng method to buld mnmal power prefx adders wthn the gven tmng and area constrants s proposed by Janhua Lu et al (2007). The performance of standard prefx adder archtectures namely Brent-Kung, Sklansky, Ladner Fscher, Kogge- Stone and Han-Carlson mplemented wth Feld Programmable Gate Array (FPGA) technology was nvestgated by Konstantnos Vtorouls and Al- Khall (2007). A scheme to enhance parallel prefx addton by ncorporatng carry save notaton was proposed by Chen and Stne (2008). A new technque for explotng energy savngs offered by Data Drven Dynamc Logc (D3L) was proposed for Kogge-Stone adder by Fabo Frustac et al (2009). Most of the PPA adders dscussed n the lterature to speed up the bnary addton, use large number of computaton nodes to attan parallelsm. Ths accounts for ncreased power consumpton. 4.3 STANDARD PREFIX ADDERS Let A an 1... a1a0 and B bn 1... b1b 0 be the n-bt augend and n-bt addend respectvely, then bnary addton s defned by the equatons (4.1) and (4.2) S a b c 1 (4.1) c a b a c b c (4.2) 1 1 There are two methods for prefx addton.

4 96 Method 1: In ths method prefx addton s carred out n three steps. Step 1: Pre-processng Pre-processng, nvolves creaton of generate and propagate sgnals. Accordng to prefx computaton g (generate) and defned by the equatons (4.3) and (4.4) respectvely. p (propagate) sgnals are g a b (4.3) p a b (4.4) Step 2: Prefx Computaton PPA constructon depends on the noton of group carry propagate and group generate sgnals. Group generate and group propagate sgnals are defned by the equatons (4.5) and (4.6) respectvely. G [ : k ] g, f k G[ : j ] P[ : j ]. G[ j 1: k ], otherw se (4.5) P [ : k ] p, f k P[ : j ]. P[ j 1: k ], otherw se (4.6) To smplfy the representaton of G and P, an operator called as dot operator represented by ' ' s ntroduced to create group generate and group propagate, and s defned by the equaton (4.7) as ( G, P) [ : k] ( G, P) [ : j ] *( G, P) [ j 1: k] (4.7)

5 97 Step 3: Post-processng Post-processng step nvolves formaton of carry and sum bts for each ndvdual operand bt. The equatons for c and S, are defned as per equatons (4.8) and (4.9) respectvely. c G (4.8) [ :0] S p c 1 (4.9) Method 2: In ths method also, prefx addton s carred out n three steps. Step 1: Pre-processng Pre-processng, nvolves creaton of generate ( g ), propagate ( p ) and kll ( k ) sgnals for each bt accordng to the relatons gven below n equatons (4.10) and (4.11) and (4.12) respectvely. g a b (4.10) p a b (4.11) k a b (4.12) Step 2: Prefx Computaton Prefx computaton nvolves creaton of group generate and group kll bar sgnals. Group generate and group kll bar sgnals are defned accordng to the equatons (4.13) and (4.14) respectvely. G K [ : k ] [ : k ] g, f k G[ : j ] K [ : j ]. G[ j 1: k ], otherw se k, f k K [ : j ]. K [ j 1: k ], otherw se (4.13) (4.14)

6 98 To smplfy the representaton of G and K, an operator called as dot operator represented by ' ' s ntroduced to create group generate and group kll bar, and s defned by the equaton (4.15) as ( G, K) [ : k ] ( G, K) [ : j] ( G, K) [ j 1: k ] (4.15) Step 3: Post-processng Post-processng s a step n whch c and equatons (4.16) and (4.17) respectvely. S are computed as per c G (4.16) [ :0] S p c 1 (4.17) In both the methods, the frst and last stages are ntrnscally fast because they nvolve only smple operatons on sgnals local to each bt poston. The ntermedate stage embodes long-dstance propagaton of carres. So the performance of the adder depends on the ntermedate stage. The prefx operator has two essental propertes namely assocatve property and dempotent property whch allow for greater parallelsm. 1) Assocatve property can be explaned as gven n equatons (4.18) and (4.19) G, P G, P G, P G, P (4.18) [ h: j] [ j: k ] [ h: ] [ : k ] G, K G, K G, K G, K (4.19) [ h: j ] [ j: k ] [ h: ] [ : k ] where h j k.

7 99 2) Idempotent property can be explaned as gven n equatons (4.20) and (4.21) G, P G, P G, P (4.20) [ h: j] [ : k ] [ h: k ] G, K G, K G, K (4.21) [ h: j] [ : k ] [ h: k ] where h j k. Assocatvty allows pre-computaton of sub-terms of the prefx equatons. Ths ndcates that a seral teraton mpled by the above prefx operaton can be parallelzed. Idempontency allows these sub-terms to overlap, whch provdes some useful flexblty n the parallelzaton. Ths secton dscusses some of the mportant prefx adder algorthms for 16-bt word length. The algorthms wll be vsualzed usng Drected Acyclc Graphs (DAG s) wth the edges standng for sgnals or sgnal pars. The whte nodes represent the nput nodes. The black crcles ndcate the dot operator. The gray crcles represent the sem-dot operator Sklansky Adder Fgure 4.1 shows a 16-bt Sklansky adder (Sklansky, 1960). It has mnmum depth prefx graph. The longest lateral fannng wres go from a node to 2 n other nodes.

8 100 Inputs Stage 1 Stage 2 Stage 3 Outputs C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 Stage 4 Fgure 4.1 Prefx Graph of a 16-bt Sklansky Adder The structure possesses an optmal depth gven by log2 n and the n number of computatonal nodes s gven by [ (log 2 n )]. The fan-out of the 2 Sklansky s adder ncreases drastcally from the nputs to outputs along the crtcal path, whch accounts for large amount of latency. Ths degrades the performance of the structure when the number of bts of the adder becomes large Kogge-Stone Adder Fgure 4.2 shows the prefx graph for a 16-bt Kogge-Stone adder (Kogge and Stone, 1973). Adders mplemented usng ths technque possess regular layout and a controlled fan-out of two.

9 101 Inputs Outputs C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 Fgure 4.2 Prefx Graph of a 16-bt Kogge-Stone Adder Kogge-Stone structure s very attractve for hgh-speed applcatons. However, t comes at the cost of area and power. The delay of the structure s gven by log2 n. Ths structure possesses [( n)(log 2 n) n 1] computaton nodes. The Kogge-Stone scheme addresses the problem of fanout by ntroducng a recursve doublng algorthm. It uses dempotency property to lmt the lateral fan-out, but at the cost of a dramatc ncrease n the number of lateral wres at each stage. Ths s because there, s a massve overlap between the prefx sub-terms beng pre-computed Brent-Kung Adder Fgure 4.3 shows the prefx graph of a 16-bt Brent-Kung adder (Brent and Kung, 1980). A smpler tree structure could be formed, f only the carry at every power of two postons s computed as proposed by Brent and Kung. An nverse carry tree s added to compute ntermedate carres. Its wre complexty s much less than that of a Kogge-Stone adder. The delay of the structure s gven by [(2)(log 2 n) 2] and the number of computaton nodes s gven by [2( n) 2 log 2 n].

10 102 Inputs T T T Stage 1 Stage 2 Stage 3 Stage 4 Stage 5 Stage 6 Outputs C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 Fgure 4.3 Prefx Graph of a 16-bt Brent-Kung Adder Han-Carlson Adder Fgure 4.4 shows the prefx graph for a 16-bt Han-Carlson adder (Han and Carlson, 1987). It s a hybrd desgn combnng stages from Brent- Kung and Kogge-Stone. It has fve stages, the frst stage resembles Brent- Kung adder and the mddle three stages resemble Kogge-Stone adder. It possess wres wth shorter span than Kogge-Stone. The dot operator was placed n the odd bt postons n the ntal stages, but the dot operator was placed n the even bt postons n the fnal stage. The delay n ths structure s n [ (log n )]. 2 gven by [(log 2 n) 1], whle the computaton hardware complexty s 2 The hardware complexty s reduced compared to Kogge-Stone adder, but at the cost of ntroducng an addtonal stage to ts carry merge path. Ths structure agan trades off an ncrease n logcal depth for a reducton n fanout.

11 103 Inputs Stage 1 Stage 2 Stage 3 Stage 4 Outputs C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 Stage 5 Fgure 4.4 Prefx Graph of a 16-bt Han-Carlson Adder Ladner-Fscher Adder The Fgure 4.5 shows the prefx graph structure for a 16-bt Ladner- Fscher adder (Ladner and Fscher, 1980). Inputs Stage 1 T Stage 2 T Stage 3 Stage 4 Stage 5 Outputs C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 Fgure 4.5 Prefx Graph of a 16-bt Ladner-Fscher Adder

12 104 Ths structure s a modfed verson of Sklansky s adder. In a 16-bt Ladner-Fscher adder, the longest lateral fannng wres go from a node to 4 n other nodes. The delay of the structure s gven by log2 n 1. The number of n computatonal nodes s gven by [ (log 2 n )]. Table 4.1 summarzes the 2 structural detals of the exstng PPAs. Table 4.1 Structural Comparson of n-bt Parallel Prefx Adders Adder Type Number of Computaton Nodes Brent-Kung n 2 Kogge-Stone 2 Han-Carlson 2 [2( ) 2 log n] 2 Logc Depth [(2)( log n) 2] [( n)(log n) n 1] log2 n n [ (log )] 2 n [ (log )] 2 Ladner-Fscher 2 n [ (log )] 2 Sklansky 2 n 2 n 2 n 2 [(log n) 1] [(log n) 1] log n 4.4 PROPOSED HYBRID PREFIX ADDER ARCHITECTURES The Proposed 8-bt, 16-bt, 32-bt and 64-bt PPA archtectures are shown n Fgures 4.6 to 4.9 respectvely. The archtectures employ the assocatve property of the PPA to keep the number of computaton nodes at a mnmum, by elmnatng the massve overlap between the prefx sub-terms beng computed. schemes namely The Proposed adder structures are mplemented usng three 1) Scheme I 2) Scheme II 3) Scheme III

13 105 Inputs Stage 1 Stage 2 Stage 3 Stage 4 Outputs C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 Fgure 4.6 Prefx Graph of the Proposed 8-bt Adder Inputs Stage 1 Stage 2 Stage 3 Stage 4 Stage 5 Outputs C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 Fgure 4.7 Prefx Graph of the Proposed 16-bt Adder

14 106 Inputs Stage 1 Stage 2 Stage 3 Stage 4 Stage 5 Stage 6 Stage 7 Stage 8 Stage 9 Outputs C 31 C 30 C 29 C 28 C27 C 26 C 25 C 24 C 23 C 22 C 21 C 20 C 19 C 18 C17 C16 C 15C14 C 13 C 12 C11 C 10 C 9 C 8 C 7 C 6 C 5 C4 C 3 C C 2 1 C 0 Fgure 4.8 Prefx Graph of the Proposed 32-bt Adder Prefx computaton employed for dervng the carry sgnals n the proposed archtectures shown n Fgures 4.6 to 4.9, ntroduce four dfferent computaton nodes for achevng mproved performance. The proposed archtectures use two cells for the dot operator and two cells for the sem-dot operator n the prefx-computaton step. Frst cell for the dot operator named odd-dot s represented by a, and second cell for the dot operator named even-dot s represented by a. Frst cell for the sem-dot operator named odd-sem-dot s represented by a, and the second cell for the sem-dot operator named even-sem-dot s represented by a. The last computaton node n each column of the proposed archtecture s a sem-dot operator. The stages wth odd ndces use odd-dot and odd-sem-dot cells where as the stages wth even ndces use even-dot and even-sem-dot cells. The lateral fan-out slghtly ncreases n the proposed archtectures, but we get an advantage of lmted nterconnect lengths snce the prefx graph grows only along the man dagonal.

15 C 63 C 62 C 61 C 60 C 59 C C C 56 C 55 C 54 C C C 51 C C C C 47 C C C 44 C 43 C 42 C 41 C 40 C 39 C 38 C C C 35 C 34 C 33 C 32 C C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C C 5 4 C 3 C C C 31 C 30 C 29 C 28 C 27 C C C 24 C 23 C 22 C C C 19 C C C Fgure 4.9 Prefx Graph of the Proposed 64-bt Adder 107

16 108 CMOS logc famly may be used to mplement only nvertng functons. The nvertng property of CMOS logc s employed, by alternatvely cascadng odd computaton cells and even computaton cells. An alternatve cascade of odd computaton cell and even computaton cell provdes the beneft of elmnaton of two pars of nverters between successve stages. Ths beneft s acheved, f both the nputs of a computaton node n stage ' ' are from stage ' (2* j 1) ' where j 0. A par of nverters s ntroduced n the path, f a dot or a sem-dot computaton node n a stage ' ' receves any of ts nputs from stage ' (2* j) '. The par of nverters n a path s represented by a n the prefx graph. From the prefx graph of the proposed structure shown n Fgure 4.6, Fgure 4.7, Fgure 4.8 and Fgure 4.9, t s observed that there are only few edges wth a par of nverters. Thus by ntroducng two cells for dot operator and two cells for sem-dot operator, a large number of nverters are elmnated. Due to nverter elmnaton n paths, the propagaton delay n those paths wll be reduced. Further t accounts for a beneft n power reducton, snce these nverters f not elmnated, would have contrbuted to sgnfcant amount of power dsspaton due to swtchng. The output of the odd-sem-dot cells gves the value of the carry sgnal n that correspondng bt poston. The output of the even-sem-dot cell gves the complemented value of carry sgnal n that correspondng bt poston Scheme I The Pre-processng stage n the proposed prefx adder archtectures, nvolve the creaton of complementary generate and propagate sgnals for ndvdual operand bts. The equatons (4.22) and (4.23) represent the functonalty of the frst stage. g ( a b ) (4.22)

17 109 p a b a b (4.23) In the above equatons, a, b represent nput operand bts for the adder. In ths scheme, the prefx computaton stage s responsble for formaton of group generate and group propagate sgnals. The odd-dot operator and odd-sem-dot operator work wth actve low nputs and generate actve hgh outputs. The even-dot operator and even-sem-dot operator work wth actve hgh nputs and generate actve low outputs. The equatons (4.24) and (4.25) represent the functonalty of odd-dot and even-dot cells respectvely. ( G, P) ( G, P) ( G, P) [ : k ] [ : j] [ j 1: k ] (( G.( P G ), P P ) [ : j] [ : j] [ j 1: k ] [ : j] [ j 1: k ] ( G P. G, P. P ) [ : j] [ : j] [ j 1: k ] [ : j] [ j 1: k ] (4.24) ( G, P) ( G, P) ( G, P) [ : k ] [ : j] [ j 1: k ] ( G P. G, P. P ) [ : j] [ : j] [ j 1: k ] [ : j] [ j 1: k ] (4.25) The equatons (4.26) and (4.27) represent the functonalty of oddsem-dot and even-sem-dot cells respectvely. ( G) ( G, P) ( G, P) [ :0] [ : j] [ j 1:0] (( G[ : j].( P[ : j] G[ j 1:0] ) ) ( G P. G ) c [ : j] [ : j] [ j 1:0] (4.26) ( G) ( G, P) ( G, P) [ :0] [ : j] [ j 1:0] ( G P. G ) c (4.27) [ : j] [ : j] [ j 1:0]

18 110 The output of the odd-sem-dot cells gves the value of the carry sgnal n that correspondng bt poston. The output of the even-sem-dot cell gves the complemented value of carry sgnal n that correspondng bt poston. The fnal stage n the prefx addton s termed as post-processng. The fnal stage nvolves generaton of sum bts from the actve low propagate sgnals of the ndvdual operand bts and the carry bts generated n true form or complement form Scheme II The frst stage n the archtectures of the proposed prefx adder structures nvolves the creaton of kll, propagate and complementary generate sgnals for ndvdual operand bts usng the equatons (4.28) to (4.30) respectvely. k a b a. b (4.28) g ( a b ) (4.29) p ( a b ) ( a b ) (4.30) In the above equatons, a, b represent nput operand bts for the adder. The prefx computaton n ths scheme s responsble for creatng group generate and group kll sgnals. The odd-dot operator and the odd-sem-dot operator use actve low group generate and actve hgh group kll nputs to produce actve hgh group generate and actve low group kll outputs. The even-dot operator and even-sem-dot operator use actve hgh group generate and actve low group kll as nputs to yeld actve low group generate and actve hgh group kll outputs.

19 111 equaton (4.31) The computaton for odd-dot operator s defned by the ( G, K) ( G, K) ( G, K) [ : k ] [ : j] [ j 1: k ] (( G.( K G ), K K ) [ : j] [ : j] [ j 1: k ] [ : j] [ j 1: k ] ( G K. G, K. K ) [ : j] [ : j] [ j 1: k ] [ : j] [ j 1: k ] (4.31) The second cell for the dot operator named even-dot represented by a, s defned by the equaton (4.32) ( G, K) ( G, K) ( G, K) [ : k ] [ : j] [ j 1: k ] ( G K. G, K. K ) [ : j] [ : j] [ j 1: k ] [ : j] [ j 1: k ] (4.32) Smlarly, there are two cells desgned for the sem-dot operator. Frst cell for the sem-dot operator named odd-sem-dot represented by a, the second cell for the sem-dot operator named even-sem-dot represented by a, work based on equatons (4.33) and (4.34) respectvely. ( G) ( G, K) ( G, K) [ : k ] [ : j] [ j 1: k ] (( G.( K G )) [ : j] [ : j] [ j 1: k ] ( G K. G ) c [ : j] [ : j] [ j 1: k ] (4.33) ( G) ( G, K) ( G, K) [ : k ] [ : j] [ j 1: k ] ( G K. G ) c [ : j] [ : j] [ j 1: k ] (4.34) The output of the odd-sem-dot cells gves the value of the carry sgnal n that correspondng bt poston. The output of the even-sem-dot cell gves the complemented value of carry sgnal n that correspondng bt poston. The fnal stage nvolves generaton of sum bts from the propagate

20 112 sgnals of the ndvdual operand bts and the carry bts generated n true form or complement form Scheme III Ths scheme s a slght varaton of Scheme II. The frst stage nvolves creaton of kll and complementary generate sgnal only for the ndvdual operand bts. The propagate sgnal s derved from the kll and the complementary generate sgnal. The equaton for the propagate sgnal s gven n equaton (4.35) p g k (4.35) where g and k are generate and kll sgnals for the ndvdual nput operand bts a and b respectvely. The rest of the archtecture s smlar to Scheme II. Snce propagate s derved usng NOR operaton, further reducton n the swtchng actvty s attaned, whch accounts for a consderable amount of power savngs. 4.5 SIMULATION Smulaton for the PPA desgns s done usng Tanner EDA tool n 180 nm and 130 nm technologes. All the PPA structures are mplemented usng CMOS logc famly. For TSMC 180 nm technology, threshold voltages of NMOS and PMOS transstors are around V and V respectvely and the supply voltage s 1.8 V. For TSMC 130 nm technology, threshold voltages of NMOS and PMOS transstors are around V and V respectvely and the supply voltage s 1.3 V. The rse tme and fall tmes of the nputs are set to 0.10 ns. The aspect rato of the MOS transstor W W devces were chosen such that 3. The nput patterns are L L swtched after every 10 ns. The parameters consdered for comparson are p n

21 113 power consumpton, worst case delay and power-delay product. The varous PPA structures are then compared wth the number of computaton nodes needed for crcut realzatons. 4.6 SIMULATION RESULTS AND ANALYSIS Tables 4.2 to 4.5 lst out the structural characterstcs of varous 8- bt, 16-bt, 32-bt and 64-bt PPAs. Table 4.2 Structural Comparson of 8-bt Parallel Prefx Adders Adder Type Number of Computaton Nodes Dot Sem-Dot Logc Depth Brent-Kung Kogge-Stone Han-Carlson Ladner-Fscher Sklansky Proposed Table 4.3 Structural comparson of 16-bt Parallel Prefx Adders Adder Type Number of Computaton Nodes Dot Sem-Dot Logc Depth Brent-Kung Kogge-Stone Han-Carlson Ladner-Fscher Sklansky Proposed

22 114 Table 4.4 Structural Comparson of 32-bt Parallel Prefx Adders Adder Type Number of Computaton Nodes Dot Sem-Dot Logc Depth Brent-Kung Kogge-Stone Han-Carlson Ladner-Fscher Sklansky Proposed Table 4.5 Structural Comparson of 64-bt Parallel Prefx Adders Adder Type Number of Computaton Nodes Dot Sem-Dot Logc Depth Brent-Kung Kogge-Stone Han-Carlson Ladner-Fscher Sklansky Proposed From the Tables 4.2 to 4.5, t s nferred that the number of dot computaton nodes n the proposed archtectures for varous word lengths s mnmal compared to other exstng archtectures. The logc depth has ncreased slghtly to accomadate the reducton n computaton nodes.

23 Smulaton Results of Parallel Prefx Adders usng Scheme I Tables 4.6 to 4.13 lst out the performance comparson of varous 8-bt, 16-bt, 32-bt and 64-bt PPAs n Scheme I. Table 4.6 Performance comparson of 8-bt Parallel Prefx Adders n Scheme I usng 180 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed Table 4.7 Performance comparson of 8-bt Parallel Prefx Adders n Scheme I usng 130 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed The proposed 8-bt PPA n Scheme I, attans a power savng of 7.49% and 9.75% n 180 nm and 130 nm technologes respectvely when

24 116 compared wth Brent-Kung adder. Ths s due to the fact that a large number of nverters are elmnated n the proposed archtecture. The results show that the proposed 8-bt PPA can acheve about 27% to 30% reducton n powerdelay product when compared wth Kogge-Stone adder. Ths s due to the fact that the total number of dot computaton nodes have reduced by about 35.29%. Table 4.8 Performance Comparson of 16-bt Parallel Prefx Adders n Scheme I usng 180 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed Table 4.9 Performance Comparson of 16-bt Parallel Prefx Adders n Scheme I usng 130 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed

25 117 The proposed 16-bt PPA n Scheme I, offers about 2.66% power savngs when compared wth Ladner-Fscher adder n 180 nm technology. Further the proposed 16-bt PPA, acheves about 35% to 40% mprovement n speed when compared to Han-Carlson adder. Ths beneft s attaned because the Proposed PPA employs four computaton nodes, whch cause mprovement n crtcal path delay. Table 4.10 Performance Comparson of 32-bt Parallel Prefx Adders n Scheme I usng 180 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed Table 4.11 Performance Comparson of 32-bt Parallel Prefx Adders n Scheme I usng 130 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed

26 118 The proposed 32-bt PPA n Scheme I has reduced the crtcal path delay by about 6.59% and 2.98% n 180 nm and 130 nm technologes when compared wth Ladner-Fscher adder. There s a reducton of 5.92% and 11.62% n power-delay product for the proposed 32-bt PPA compared to Sklansky adder n 180 nm and 130 nm technologes respectvely. Ths mert s acheved due to reducton n the maxmum fan-out of the computaton nodes for the proposed PPA. Table 4.12 Performance Comparson of 64-bt Parallel Prefx Adders n Scheme I usng 180 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed Table 4.13 Performance Comparson of 64-bt Parallel Prefx Adders n Scheme I usng 130 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed

27 119 Tables 4.12 and 4.13 ndcate that there s a reducton of 58.7% of power and 56.25% of power n the proposed 64-bt PPA compared to Kogge- Stone adder for 180 nm and 130 nm technologes respectvely. Ths drastc mprovement n power has occurred for the proposed PPA because of 83% reducton n dot computaton hardware. Also results reveal that the proposed 64-bt PPA offers 3.1% and 3.4% reducton n crtcal path delay when compared wth Ladner-Fscher adder Smulaton Results of Parallel Prefx Adders usng Scheme II Tables 4.14 to 4.21 lst out the performance comparson of varous 8-bt, 16-bt, 32-bt and 64-bt PPAs n Scheme II. Table 4.14 Performance Comparson of 8-bt Parallel Prefx Adders n Scheme II usng 180 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed

28 120 Table 4.15 Performance Comparson of 8-bt Parallel Prefx Adders n Scheme II usng 130 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed From Tables 4.14 and 4.15 t s nferred that the proposed 8-bt PPA n Scheme II, acheves 17.7% and 19.2% mprovement n crtcal path delay compared to Han-Carlson adder for 180 nm and 130 nm technologes. Ths beneft s due to alternate cascadng of odd and even ndces computaton cells n the proposed PPA whch elmnate the nverters n the path. Table 4.16 Performance Comparson of 16-bt Parallel Prefx Adders n Scheme II usng 180 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed

29 121 Table 4.17 Performance Comparson of 16-bt Parallel Prefx Adders n Scheme II usng 130 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed Comparng the results of the proposed 16-bt PPA n Scheme II wth Ladner-Fscher adder, about 3.4% and 8.83% power savngs can be acheved for 180 nm and 130 nm technologes respectvely. Also the crtcal path delay for the proposed 16-bt PPA s reduced by 9.8% and 10.81% compared to Han-Carlson adder for 180 nm and 130 nm technologes. Table 4.18 Performance Comparson of 32-bt Parallel Prefx Adders n Scheme II usng 180 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed

30 122 Table 4.19 Performance Comparson of 32-bt Parallel Prefx Adders n Scheme II usng 130 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed Tables 4.18 and 4.19 reveal that, the proposed 32-bt PPA n Scheme II offers a beneft of 1.41% and 6.71% power reducton and 15.5% and 11.45% mprovement n speed over Brent-Kung adder for 180 nm and 130 nm technologes respectvely. The logc depth has ncreased by one for the proposed PPA compared to Brent-Kung structure. It s stll possble to reap a beneft n speed for the proposed PPA due to the presence of four dfferent computatonal cells. Further the power savngs s due to 11% reducton n dot computaton hardware. Table 4.20 Performance Comparson of 64-bt Parallel Prefx Adders n Scheme II usng 180 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed

31 123 Table 4.21 Performance Comparson of 64-bt Parallel Prefx Adders n Scheme II usng 130 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed The crcut latency for the proposed 64-bt PPA n Scheme II has mproved by 8.1% and 5.82% over Ladner-Fscher adder for 180 nm and 130 nm technologes respectvely. Further, nearly 45% to 49% mprovement n power-delay product can be acheved for the proposed 64-bt PPA compared to Kogge-Stone adder. The dot computaton hardware has reduced by 83% nearly, hence t provdes a sgnfcant amount of power reducton and a drastc mprovement n power-delay product Smulaton Results of Parallel Prefx Adders usng Scheme III Tables 4.22 to 4.29 lst out the performance comparson of varous 8-bt, 16-bt, 32-bt and 64-bt PPAs n Scheme III.

32 124 Table 4.22 Performance Comparson of 8-bt Parallel Prefx Adders n Scheme III usng 180 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed Table 4.23 Performance Comparson of 8-bt Parallel Prefx Adders n Scheme III usng 130 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed The crtcal path delay for the proposed 8-bt PPA n Scheme III has reduced by 9.37% and 5.26% compared to Han-Carlson adder for 180 nm and 130 nm technologes respectvely. The proposed PPA elmnates several nverters along the crtcal path to acheve mprovement n speed.

33 125 Table 4.24 Performance Comparson of 16-bt Parallel Prefx Adders n Scheme III usng 180 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed Table 4.25 Performance Comparson of 16-bt Parallel Prefx Adders n Scheme III usng 130 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed The crcut latency of the proposed 16-bt PPA n Scheme III has mproved by about 20% n comparson wth Ladner-Fscher adder. The power-delay product for the proposed 16-bt PPA n comparson wth Brent Kung adder, reveal that there s an mprovement of 12.25% and 23.70% for 180 nm and 130 nm technologes respectvely. The delay for the proposed PPA has mproved because the logc depth has reduced by one compared to Brent-Kung structure and a small amount n power reducton s due to elmnaton of nverters, due to alternate cascadng of computaton cells. Hence power-delay product has mproved compared to Brent-Kung structure.

34 126 Table 4.26 Performance Comparson of 32-bt Parallel Prefx Adders n Scheme III usng 180 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed Table 4.27 Performance Comparson of 32-bt Parallel Prefx Adders n Scheme III usng 130 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed The Proposed 32-bt PPA n Scheme III offers 16.79% and 22.85% power savngs n comparson wth Sklansky adder for 180 nm and 130 nm technologes respectvely. Ths sgnfcant power savngs s due to 30.3% reducton n dot computaton hardware for the proposed PPA compared to Sklansky adder. Further n Sklansky adder, the maxmum fan-out ncreases drastcally along the man dagonal. Ths ntroduces latency n the Sklansky adder. Proposed PPA offers a controlled maxmum fan-out of 5.

35 127 Table 4.28 Performance Comparson of 64-bt Parallel Prefx Adders n Scheme III usng 180 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed Table 4.29 Performance Comparson of 64-bt Parallel Prefx Adders n Scheme III usng 130 nm Technology - Brent-Kung Kogge-Stone Han-Carlson Sklansky Ladner-Fscher Proposed The propagaton delay s reduced by 9.52% and 21.58% for the proposed 64-bt adder n Scheme III relatve to Brent-Kung adder for 180 nm and 130 nm technologes respectvely. Comparson of the proposed 64-bt adder wth Han-Carlson structure, reveal that there s 28.66% and 21.37% reducton n power-delay product for 180 nm and 130 nm technologes. The beneft n power reducton for the proposed PPA s due to elmnaton of nverters along the path and reducton n dot computaton hardware. In the power comparson and power-delay product comparson bar charts shown below, BK represents Brent-Kung adder, KS represents Kogge-Stone adder, HC represents Han-Carlson adder, SK represents Sklansky adder and LF represents Ladner-Fscher adder.

36 128 Fgures 4.10 and 4.11 show the power comparson of varous 32-bt PPA structures n Scheme I, Scheme II and Scheme III respectvely for 180 nm and 130 nm technologes respectvely. Fgure 4.10 Comparson of the 32-bt Parallel Prefx Adders n Three Schemes for 180 nm Technology Fgure 4.11 Comparson of the 32-bt Parallel Prefx Adders n Three Schemes for 130 nm Technology

37 129 Fgures 4.12 and 4.13 show the power-delay product comparson of varous 32-bt PPA structures n Scheme I, Scheme II and Scheme III respectvely for 180 nm and 130 nm technologes respectvely. Fgure Comparson of the 32-bt Parallel Prefx Adders n three Schemes for 180 nm Technology Fgure Comparson of the 32-bt Parallel Prefx Adders n three Schemes for 130 nm Technology

38 130 Fgures 4.14 and 4.15 show the power comparson of varous 64-bt PPA structures n Scheme I, Scheme II and Scheme III respectvely for 180 nm and 130 nm technologes respectvely. Fgure 4.14 Comparson of the 64-bt Parallel Prefx Adders n Three Schemes for 180 nm Technology Fgure 4.15 Comparson of the 64-bt Parallel Prefx Adders n Three Schemes for 130 nm Technology

39 131 Fgures 4.16 and 4.17 show the power-delay product comparson of varous 64-bt PPA structures n Scheme I, Scheme II and Scheme III respectvely for 180 nm and 130 nm technologes respectvely. Fgure Comparson of the 64-bt Parallel Prefx Adders n Three Schemes for 180 nm Technology Fgure Comparson of the 64-bt Parallel Prefx Adders n Three Schemes for 130 nm Technology

40 132 The delay and the power-delay product are mnmal n Scheme I. Ths s because the actvty factor for propagate sgnal beng at logc 1 and at logc 0 s 50% n the Pre-processng Stage. In the prefx computaton stage, Scheme I employs computaton of group generate and group propagate as opposed to computaton of group generate and group kll bar for Scheme II and Scheme III. It s nferred that the power consumpton s mnmal n Scheme III for all the PPA structures. Ths s because kll bar sgnal n the preprocessng remans at logc 1 for 75% and at logc 0 for 25%. Further n Scheme III, Propagate sgnal s derved usng generate and kll sgnals of the ndvdual operand bts. Ths accounts for reducton n the number of transstors count, whch leads to further reduced power dsspaton. Crtcal path delay n Scheme III s hgher snce propagate sgnal n pre-processng stage s derved from kll and generate sgnals usng a NOR gate. The amount of power savng gradually ncreases for the proposed archtectures when the sze of the prefx adder grows. It s also observed that the power-delay product of the proposed archtecture s mnmal when compared to other PPAs. Table 4.30 Comparson of the Proposed 64-bt Parallel Prefx Adders wth Prevous Works Technology PPA / Supply Voltage (mw) Zhanpeng Jn et al (2005) 180 nm / 2.5 V Yan Sun et al (2006) 180 nm / 1.8 V Proposed Scheme I 180 nm / 1.8 V Proposed Scheme II 180 nm / 1.8 V Proposed Scheme III 180 nm / 1.8 V

41 CONCLUSION Novel hybrd PPA archtectures for 8-bt, 16-bt, 32-bt and 64-bts s proposed that offers mnmal power dsspaton and least power-delay product. The archtectures are realzed usng three Schemes. Scheme I provdes least delay and least power-delay product for all the PPA archtectures. Scheme II offers moderate power and delay for all the PPA archtectures. Scheme III provdes least power dsspaton n all the PPA archtectures. The proposed PPA n Scheme I acheves 3% to 7% power savngs and 15% to 35% mprovement n speed compared wth Brent Kung adder whch has nearly same logc depth and number of computaton nodes. The proposed PPA archtecture n Scheme I attans 30% to 45% power savngs at the expense of 5% to 10% delay penalty compared to Kogge-Stone adder whch has maxmum computaton nodes. The proposed PPA n Scheme II acheves 3% to 15% power savngs and 15% to 28% mprovement n performance when compared to Brent Kung adder. The proposed PPA archtecture n Scheme II attans 35% to 52% power savngs at the expense of 10% to 27% delay penalty compared to Kogge-Stone adder. The Proposed PPA n Scheme III offer 6% to 8% power savngs and 10% to 25% mprovement n crtcal path delay compared to a Brent-Kung adder. The proposed PPA archtecture when compared to Kogge-Stone adder n Scheme III offers 45% to 55% power reducton at the expense of 17% to 25% delay penalty.