System Level Design Technologies and System Level Design Languages

Transcription

1 System Level Design Technologies and System Level Design Languages SLD Study Group EDA-TC, JEITA

2 Problems to Be Solved 1. Functional Design Ambiguity of specification Change of system specification Slow simulation speed 2. Architecture Design No methodology for verification Low accuracy of estimation Designers Requirements 3. Implementation No effective design tool from High Level to RTL design flow mismatch between implementation and specification 4. Design database, Co-simulation difficulty of IP customization Lack of performance of co-simulation tools for SW design JEITA 2001 All rights reserved 2

3 Solutions 1. Functional Design For Ambiguity handling of the specification ambiguity of specification Change of system specification Slow simulation speed Methodology to define functional specification Executable SLD language 2. Architecture Design For earlier estimation of cost, performance, 2. Architecture etc. Design No methodology for Fast verification exploration method of finding Low optimum accuracy architecture of estimation Estimation model and design database 3. Implementation For No easy effective link to design implementation tool from H.L.D. phase to RTL design flow mismatch between implementation Interface synthesis and specification of HW/SW Equivalency check Designers Requirements 4. Design database, Co-simulation 4. Design database, Co-simulation For easiness of IP use, high speed cosimulation difficulty of IP customization Lack of performance of co-simulation tools for SW design Standardized I/F of IP, IP synthesis, Highly abstracted HW model JEITA 2001 All rights reserved 3

4 System Level Design Technologies Research Target EDA Technology Roadmap Toward 2002 EIAJ/EDA-TC/EDA Vision Study Group 1998 Universities/Research Centers POLIS OCAPI-xl IpChinook Vendors CoCentric N2C VCC Hardware-Software Co-Design of Embedded Systems, The POLIS Approach Kluwer Academic Publishers(1997) JEITA 2001 All rights reserved 4

5 Roadmap of EDA Technologies Items [System Level Design] Standardization of system model Standardization of system level design language(sldl) Simulation of SLD Language Performance estimation in system level design (application soft, compiler, performance estimation of HW, optimization High speed prototyping Formal verification (Specification - System HW/SW partition System level library (IP core, middle ware, etc. Decision support of system level test strategy Tradeoff of analog/digital [Architecture Design] Standardization of architecture model Standardization of architecture description language Estimation in architecture level area, delay, power,.. Decision of RTL constraint area, timing, power, budgeting of floor plan Formal verification System - Architecture Validation/Simulation Architecture synthesis Co-synthesis Decision support of architecture level test strategy test method/area/length of test DFT in architecture level :trial use In the prediction, almost all technologies are in the trial phase in 2000!! How in the real world? :preceding use :practical use Cited from EIAJ/EDA Technology Roadmap Toward 2002 JEITA 2001 All rights reserved 5

6 Design Tools (1) by Universities and Research Centers POLIS (UCB, U.S.A.) Co-design Environment for embedded system based on the CPU and DSP Supporting functional design to prototyping Architecture exploration by mapping behavior to architecture Accurate and high-level performance estimation using a fuzzy instruction set Esterel HDL SDL LOTOS) Functional level Mapping level Architecture Level System Specification Capture Behavior Verify Behavior Verify Performance Capture Architecture Verify Architecture Map Behavior to Architecture Refine HW/SW Architecture Link to Architecture Verification Link to HW / SW Implementation CPU/DSP RTOS Bus, Memory HW OCAPI-xl (IMEC, Belgium) OCAPI-xl System User Code Model C/C++ OCAPI-xl System Model VHDL/ Verilog User Code (C/C++) Decomposition and Analysis Integration and Mapping OCAPI-xl Models Code Generation C/C++ Performance Measures VC Models C++ model which can describe and uniformly Optimal block partition using a performance analysis System Link Automatic generation of VHDL / Verilog-HDL / C Single program model Multi-process model IpChinook (U of Washington, U.S.A.) Based on IP-based/Reused-Design methodology Automatic generation of control and I/F between functional blocks Lots of communication protocol libraries Support of,, Behavioral Description Control Composition Data Composition & Timing Constraints Control Synthesis Communication & Interface Synthesis Real-time Scheduling Output Schematic & Code Allocation Target Description Heterogeneous Distributed Architecture Simulation JEITA 2001 All rights reserved 6

7 Design Tools (2) by Vendors CoCentric (Synopsys) CoCentric System Studio SW Design System Design Datapath Control a.out Float Fixed-pointed Support HW side and co-verification of SOC Design Conversion from float to fix-pointed HW Synthesis from behavior Verilog,VHDL) Supporting SystemC CoCentric Fixed-Point Designer HW Design RTL Gate CoCentric System Compiler N2C (CoWare) Supporting functional level to implementation System Definition in Untimed, BCASH, BCA abstraction levels by original C-based language (CoWareC) Communication refinement Interface synthesis between HW and SW Supporting SystemC (in future) Functional Specification/verivication Function Software Optimization Communication HW/SW Partition Interface Synthesis HW/SW Co-verification Final Verification System definition by function and communication Detailed HW Design Timing verification conversion Synthesis UnTimed Model BCASH Model BCA Model HDL Model C/C++ SDL SPW HDL [OMI] MatLab Pattern VCC(Cadence) System Specification System Function Simulation Communication Refinement HW Assembly Architecture Mapping Design Estimation Simulation Architecture exploration by mapping function to architecture Performance estimation using a fuzzy instruction set Supporting IP reuse Architecture Generation SW Assembly Communication synthesis Interface to implementation CPU/DSP RTOS Bus, Memory HW JEITA 2001 All rights reserved 7

8 Summary of EDA Trend May be solved in near future? Function Verification Architecture Mapping Performance Estimation Interface Synthesis HW/SW Co-Verification Unsolved Problems Function Partition High Speed Estimation Estimation of Area, Cost, and Power Standardized Description of system specification, constraints etc. JEITA 2001 All rights reserved 8

9 System LSI Multi-function/ High performance Requirement of system level optimization Large/Complex Heterogeneous components High IP Utilization CPU ROM RAM IP IP New New IP Multi-product, Small-lot Production System LSI Short TAT JEITA 2001 All rights reserved 9

10 Conventional Design Flow System Specification Constraints Function Ambiguity of specification causes misunderstanding Inaccuracy of estimation causes re-spin Interface to Implementation HW/SW Co-Design JEITA 2001 All rights reserved 10

11 Proposed Design Flow System Specification Constraints Function Determination Function func2() func1() main() : : Veri. Function Definition Profiling Architecture Determination Design Space Generation FB1 FB4 FB2 FB5 FB3 Partitioned Function Definition CPU CPU CPU MEM HW HW HW HW HW HW Candidates of architecture Design Space Exploration Architecture Mapping Est. Interface to Implementation HW/SW Co-Design JEITA 2001 All rights reserved 11

12 Proposed Design Flow System Specification Test Description Test Bench Expected Value Test Spec. Architecture Determination Function Determination Function Function Verification Definition Design Space Generation Equivalence Checking Estimation Constraints Block Partitioning Design Space Exploration Function Profiling Architecture Generation Architecture Mapping Interface to Implementation HW/SW Co-Design Document DB Algorithm IP Function Block IP Architecture IP Estimation DB SW IP Bus I/F IP HW IP Design Database JEITA 2001 All rights reserved 12

13 Design Space Generation Block partitioning and architecture generation from function model Design Space Generation Block Partitioning func2() func1() main() : : Profiling Function Model Architecture Generation FB1 FB2 FB3 CPU MEM FB4 FB5 HW HW JEITA 2001 All rights reserved 13

14 Profiling Analyze function models statically/dynamically and extract information for block partitioning and architecture generation Class Number of Variable Access Amount of Data Transfer Amount of Calculation Statistical Analysis Information Number of read/write Access position Read-write distance Number of (bits)*(number of exec.) of read/write Amount of parameters Execution count of lines Execution count of blocks Execution count of functions Type and count of arithmetic/control instructions Usage (in design space generation) Choice of algorithm Decision of block candidates Selection of memory/register Decision of partitioning units Decision of HW/SW partitioning Selection of comm. protocol Decision of partitioning units Performance estimation on HW/SW Choice of processor Refinement of instruction set JEITA 2001 All rights reserved 14

15 Design Space Exploration Mapping each functional block to a component and select the optimum architecture which satisfies constraints Architecture Mapping FB1 FB2 FB3 CPU MEM FB4 FB5 HW HW Transaction Process Model Architecture Model represents only system the processing by functional cost blocks for estimation and communications between them ExampleProcessing time process cost process capability per units From transaction model From architecture model JEITA 2001 All rights reserved 15

16 Transaction Model and Accuracy Tradeoff of transaction model Coarse (Fast) Static Analysis Precise (Slow) Dynamic Analysis Method Simple summation of average properties (design data) Considering algorithm (branch, loop) Instruction set Dynamic simulation (using constraints) Advantages and Disadvantages High speed/low accuracy Need DB of past data Impossible to critical analysis Middle speed/middle accuracy Estimation of average property/range Low speed/high accuracy Need detailed analysis of implementation JEITA 2001 All rights reserved 16

17 Slow simulation speed Test Description Test Bench Expected Value Test strategy of overall design flow Solution to Problems Test Spec. Architecture Determination Inaccuracy of estimation Ambiguity of specification System Specification Function Determination Function Function Verification Definition Design Lack of Space Generation architecture decision tool Equivalence Checking Estimation Insufficient performance of co-simulator in software development Constraints Block Partitioning Design Space Exploration Function Profiling Architecture Generation Architecture Mapping Interface to Implementation HW/SW Co-Design Handling of ambiguity Difficulty of IP customization Lack of design path to implementation Document DB Algorithm IP Function Block IP Architecture IP Estimation DB JEITA 2001 All rights reserved 17 SW IP Bus I/F IP HW IP Design Database

18 Technology Map of Tools Only the verification is supported by all tools No tool support Some tools support this phase but speed/accuracy of the estimation is insufficient No tool supports the test bench generation automated by the tool tool has supporting function tool does not have supporting function not covered by the tool JEITA 2001 All rights reserved 18

19 Investigation of System Level Design Languages Background Important role for system level design flow Standardization activities OSCI, STOC, Accellera Objectives Understand standardization activities SystemC, SpecC, UML, etc. Evaluation of the proposed design flow Feedback to standardization groups JEITA 2001 All rights reserved 19

20 Design Languages Level of Abstraction VHDL Verilog Superlog C C++ SDL Esterel Vspec Java VHDL+ OOVHDL SLDL UML SystemC/Cynlib Rosetta SpecC Year JEITA 2001 All rights reserved 20

21 SystemC Background Proposed based on the technologies of Synopsys Inc., CoWare Inc., Frontier Design Inc. (Sept 1999) Features Representation from system level to HW/SW by adding dedicated class libraries, and without enhancing C/C++ grammar Availability of standard C/C++ development environment Less readability of description Developed from HW design using C/C++ to system level Easy to move from HDL environment Trends Open SystemC Initiative (OSCI) promotes standardization More than 70 of EDA vendors, IP vendors, semiconductor companies join to OSCI (Apr 2000) JEITA 2001 All rights reserved 21

22 SpecC Background Developed by Prof. Gajski in UCI (1997) Features Unified description of HW/SW by enhancing ANSI-C grammar High readability Needs special tools and environment Clear design methodology which covers over system modeling to architecture determination Trends SpecC Technology Open Consortium (STOC) promotes the standardization System houses, embedded software tool vendors have strong interest JEITA 2001 All rights reserved 22

23 UML Background Developed as modeling language for complicated large system Started the standardization since 1996 by OMG *1 Unification of existing object-oriented modeling methods *2 Features Visual language with high modeling ability Visual and multi-viewed system modeling use case, class, component, layout, state chart, sequence, activity, collaboration Scheme for describing constraints Methodology of applying HW design is incomplete Trends Wide use in business software Started to use in embedded software trial phase for HW design 1 ObjectModeling Group *2 Booch Method, OMT Method, OOSE Method Class Diagram State Chart Diagram JEITA 2001 All rights reserved 23

24 Evaluation Results Language item System Specification Function Constraints Function Determination Function Definition Function Verification Architecture Determination Profiling Block Partition Equivalence Check Architecture Generation Architecture Mapping Estimation Interface to Implementation HW/SW Co-Design Test Bench Generation SystemC v2.0 not supported less readability available C++ env. only structure transaction model NG insufficient methodology support until RTL SpecC (v1.0) not supported clear methodology tool environment unified HW/SW desc. only structure transaction model NG insufficient methodology planned to support Accellera s RTL model UML v1.4 visual description constraint language only for SW only state chart not supported not supported only specification IP Design JEITA 2001 All rights reserved 24

25 Summary of System Level Design Languages SystemC Representation from system level to HW/SW by adding dedicated class libraries and without enhancing C/C++ grammar Need to clarify the methodology Strong support for implementation, but need to consider the architecture generation and the estimation SpecC Unified description of HW/SW by enhancing ANSI-C grammar A key to prevalence is to arrange special design environment to implementation Methodology for system modeling exists, but weak for the architecture generation and later stages UML Large ability of function/constraint description by visual modeling Need to consider design phases after architecture design Copyright JEITA, All rights reserved 25