LX4180. LMI: Local Memory Interface CI: Coprocessor Interface CEI: Custom Engine Interface LBC: Lexra Bus Controller

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1 System-on-Chip 32-bit Embedded Processor LX4180 Product Brief R3000-class RISC Processor Core: Executes MIPS I instruction set*. Offers designers a familiar programming environment and choice of third party development tools. Performance, Power and Price: Operates at 155 MHz, consumes 175 mw of power (less than 50 µw in standby mode), and occupies 2.75 mm 2 of silicon on a typical.25µm process. Instruction Compression: Reduces program size by up to 40%. On-chip programs require less memory, resulting in cost saving for System-On-Chip designs. Multiply-Accumulate (MAC) Engine: Completes one MAC instruction every cycle. Provides performance for signal processing applications such as software modems. EJTAG Debug: Implements complete EJTAG specification for full speed debug with real time instruction trace. Development Environment: Includes GNU C- based software development kit. Development Board and additional software tools provided by Embedded Products, Inc. Supported by Wind River Systems VxWorks RTOS and Tornado development environment. Architected for Integration: Simplified PCI-like system bus and standardized system level interfaces for easy integration into a wide range of applications. Supports ASIC Implementation Methodology: Fully synchronous design with single phase clocking. Can be implemented with commercial EDA tools no custom tools or circuit design required. Portability: Average port to a new process takes six weeks. Available as a fully synthesizable RTL core or as a SmoothCore, an optimized hard macro that has been ported to a specific foundry process. I-Cache I-RAM I-ROM Customer Coprocessors LX4180 CI (1-3) Custom Instruction Engines CEI MAC CPU Core Instruction Bus Data Bus LBC Address Data EJTAG D-Cache D-RAM D-ROM : Local Memory Interface CI: Coprocessor Interface CEI: Custom Engine Interface LBC: Lexra Bus Controller MIPS, MIPS I,, R3000, and any other MIPS common law marks are trademarks and/or registered trademarks of MIPS Technologies Inc. Lexra Inc. is not associated with MIPS Technologies Inc. in any way. *Unaligned load and store instructions are supported through software emulation only.

2 The System-On-Chip RISC Processor Microprocessor companies have traditionally focused on optimizing performance, power consumption, and price (die size). While these remain important for SOC designs, system level integration requirements become equally important. An SOC processor must have interfaces so that it can be adapted to different applications. It must support an implementation methodology consistent with ASIC design one that does not require custom tools or circuit design. An SOC processor must be easy to port to different silicon processes. Software and hardware development tools such as compilers, debuggers, and system development boards must be readily available. How well a processor meets these requirements will have a significant effect on the overall functionality, cost, and time-to-market for a product. With its first generation SOC RISC processor, the LX4080, Lexra introduced a new architecture optimized for SOC requirements and designed to take advantage of advances in deep submicron process technology and chip design methodology. The LX4180, Lexra s second generation SOC RISC processor, adds new features to deliver significant advantages for embedded applications. Applications for the LX4180 include data communication functions such as remote access control, packet processing and higher level protocol processing, high-end consumer products such as digital cameras and multifunction peripheral (MFP) devices, and disk drive controllers. The LX4180 CPU The LX4180 is a 32-bit R3000-class processor that executes all MIPS I instructions except for unaligned loads and stores, providing designers with a familiar programming environment and a choice of productionproven third party development tools. The LX4180 includes refinements to the CPU architecture for improved performance, power consumption, and die size, plus a set of new features to make the LX4180 an even better choice for embedded SOC applications. MIPS I Instruction Set Architecture (ISA) The LX4180 supports the MIPS I programming model. A three-port register file supplies the source operands and destination for each instruction. The second source operand can be either a register or a 16-bit immediate. Two source operands can be supplied and one destination can be updated per cycle. The LX4180 supports the R3000-class exception handling model, including both instruction-synchronous traps and hardware and software interrupts. Instructions are executed by a five-stage pipeline. All transactions internal to the LX4180 and at the interfaces occur on the positive edge of the processor clock. As a result, designs based on the LX4180 will achieve high clock speeds without requiring expensive Phase Locked Loop (PLL) technology. Lexra s proprietary register-based ALU executes ALU operations and generates memory addresses for 8-bit, 16- bit, and 32-bit register loads(stores) from(to) memory. Branches are based on comparisons between registers, rather than flags, and are therefore easy to relocate. Optional links following jump or branch instructions assist with subroutine programming. The LX4180 supports all 32-bit Coprocessor operations, including moves to and from the Coprocessor general registers and control registers, Coprocessor loads and stores, and branches based on the Coprocessor condition flags. All Coprocessor operations execute in a single cycle, without pipeline stalls. The MIPS unaligned load and store instructions are supported through software emulation. Since these instructions are seldom used in embedded applications, emulation provides the best price/performance tradeoff. Instruction Compression The LX4180 incorporates the extension to the MIPS I ISA, in which commonly-used 32-bit instructions are encoded in 16 bits. This technique reduces the overall size of the program by as much as 40%. In SOC designs, program memory is often on-chip. By reducing the amount of memory required to store the program, can reduce the size and therefore the cost of the chip. The following chart shows the relative compression factor for popular embedded processing instruction sets. The smaller the number, the greater the compression and the smaller the program. Thumb ColdFire1.5 X86 ARM 1 MIPS 0.5 PowerPC 0 Thumb Source: Microprocessor Report ColdFire X86 ARM MIPS PowerPC -2-

3 High performance Hardware Multiply-Accumulate (MAC) Engine The optional LX4180 MAC engine can complete one MAC instruction every cycle without stalling the CPU pipeline. This engine provides the performance necessary for Digital Signal Processing (DSP) applications such as software modems and image processing applications such as JPEG decoding. While each 16 x 16 multiply-accumulate operation requires three cycles, a new operation can be initiated in each cycle as a result of internal pipelining. DSP algorithms typically operate on 16-bit fixed-point data. The LX4180 MAC operates on two 16-bit operands to produce a 32-bit result, which can be stored to either the HI accumulator or the LO accumulator. The independent accumulators allow two different operations to be performed simultaneously without the extra cycles required to store accumulators to memory or move intermediate results to temporary registers. This results in faster, more efficient programs. The table below lists the instructions executed by the LX4180 MAC engine. Instruction MADH MADL MSBH MSBL MAZH MAZL MSZH MSZL MULT, MULTU DIV, DIVU Description Multiply-Add, write result to HI Multiply-Add, write result to LO Multiply-Subtract, write result to HI Multiply-Subtract, write result to LO Zero HI then multiply-add to HI Zero LO then multiply-add to LO Zero HI then multiply-subtract to HI Zero LO then multiply-subtract to LO 32-bit MIPS I Integer Multiply (signed, unsigned) 32-bit MIPS I Integer Divide (signed, unsigned) Balanced Performance, Power, and Price The LX4180 offers the right balance of performance, power consumption, and price (die size) for embedded SOC applications. With operating performance of up to 155 MHz, the LX4180 is ideally suited to data communications applications. The LX4180 dissipates 175 mw when operating at 155 MHz, making it competitive with the lowest power embedded RISC cores. Additionally, the LX4180 offers a power saving feature whereby the entire LX4180 can be shut down in an orderly manner during long periods of inactivity. In this standby mode, power consumption is less than 50µW. Both operating and standby power characteristics make the LX4180 ideal for SOC designs, in which high gate counts often cause heat dissipation problems. The LX4180 is available as either a highly-portable Register Transfer Level (RTL) core, or as a foundryoptimized SmoothCore. The table below summarizes the LX4180 operating characteristics for a SmoothCore on a typical.25µm process. The exact specifications will depend on the silicon process and implementation technology used, as well as the inclusion of options such as the MAC engine or EJTAG interface. Process Operating Performance.25mM MHz Die Size (entire CPU complex) 2.75 mm 2 Die Size (with 8K I-Cache, 8K D- cache) Dynamic Power Consumption Standby Power Consumption < 10 mm mw < 50 mw Voltage 2.5V Complete Development Environment The LX4180 leverages extensive MIPS third party tool availability to provide a complete development environment for designers. Software Development Tools The LX4180 is supported by the Tornado development environment from Wind River Systems, and by the Software Development Toolkit from Embedded Performance Inc. The LX4180 includes the Lexra Software Development Kit (LSDK), a GNU C-based tool set that supports software development in C, C++, and MIPS assembly language. The LSDK includes the GNU tools (compiler, assembler, linker, library archive utility, and debugger), the PMON debug monitor, and a runtime library. Source code for the GNU tools is provided to allow customization in support of designer enhancements to the LX4180. Operating Systems The LX4180 is supported by the VxWorks Real Time Operating System (RTOS) from Wind River Systems, and by PMON, the public domain MIPS kernel. Development Board Embedded Performance Inc. (EPI) provides the system development board for the -3-

4 LX4180, through its partnership with Lexra. Available directly from EPI, the LX4180 Development Board supports development of ASICs, software, and hardware based on the LX4180. The board is a standard PCI card, and includes an LX4180 test chip with instruction and data RAM and Lexra standard interfaces, a PCI controller, boot prom, and PCI and serial connectors to link the board to the debug system. A daughter card that includes an unprogrammed PLD/FPGA device connected to the LX4180 s system level interfaces supports prototyping of system hardware. See for more information. Extended JTAG (EJTAG) Debug The LX4180 includes an optional interface module that supports 100% of the EJTAG specification. The EJTAG interface brings processor status and internal register contents out to the pins of the SOC, allowing a commercial In-Circuit Emulator (ICE) probe attached to the pins to debug any EJTAG-based core. LX4180 users can configure the EJTAG interface for a maximum of 45 hardware breakpoints. The EJTAG module can be removed for production silicon, to save die area. EJTAG provides the following debug capabilities: Real-time PC trace Full speed debug Single step execution Direct access to memory Visibility to virtual addresses Multiprocessing support code support FPGA/PLD Support For rapid prototyping of LX4180-based ASICs, Lexra offers a fixed configuration of the LX4180 for PLD/FPGA devices. An Architecture for Integration For SOC designs, how well the processor adapts to the application and integrates with the rest of the design can become the dominant factor in overall project success. The processor must be able to work with different system clocks, interface to different peripherals, support specialized or custom instructions, and support different memory organizations. The LX4180 architecture includes a set of interfaces that make it easy to adapt the processor to different applications and add custom capabilities. These interfaces include the Local Memory Interface (), Lexra Bus Controller (LBC), Custom Engine Interface (CEI), and Coprocessor Interface (CI). The diagram below shows the LX4180, which includes the CPU core, optional MAC and EJTAG blocks, and the system level interfaces. The blocks outside the dotted line represent different application-specific functions that can be integrated with the LX4180. Custom Instruction Engines LX4180 CEI MAC CPU Core I-Cache Local Memory Interface () : Local Memory Interface CI: Coprocessor Interface CEI: Custom Engine Interface LBC: Lexra Bus Controller The LX4180 employs a Harvard Architecture, with separate instruction memory and data memory. The functions as the memory controller for the LX4180. The LX4180 s memory architecture offers two important advantages for SOC designs: Use of Standard Memory The is optimized to work with simple 32-bit synchronous RAM for both instruction and data memory. This type of memory is readily available from commercial third party library vendors and ASIC vendors no custom designed memories are required. Support for Different Memory Organizations The allows designers to implement instruction cache, data cache, and L2 cache. The can also be used to implement non-cache local memory organizations for applications such as digital signal processing. When used as a cache memory controller, the provides a two-way set-associative instruction cache interface and a write-through, direct mapped data cache interface. The includes the tag compare logic and cache replacement algorithm. The LX4180 supports cache sizes from 1K to 16K bytes. One of the instruction cache sets can be locked down as unswappable local memory. Direct memory size can range from 1K to 64K bytes. Instruction Bus Data Bus D-Cache I-RAM I-ROM D-RAM D-ROM Customer Coprocessors CI (1-3) EJTAG LBC Address Data -4-

5 Lexra Bus Controller (LBC) The LBC provides the interface between the LX4180 and system components such as DRAM and peripherals. The LBC offers the following advantages for SOC design: Simple Protocol The Lexra system bus is nonmultiplexed, non-pipelined, and non-parity checked, to provide the easiest bus protocol for design integration. Bus width can be configured from 8 to 128 bits. On the processor side, the LBC provides a write buffer of configurable depth to support the write-through cache, and control for byte and halfword transfers. On the peripheral side, the LBC is designed to easily interface to industry standard bus protocols such as PCI, USB, and IEEE Supports Synchronous or Asynchronous Operation The LBC can operate asynchronously at any speed up to the speed of the processor core, or it can run synchronous with the CPU for maximum system throughput. The LBC synchronizes the processor and system clock domains without use of a Phase-Locked Loop, eliminating a source of porting difficulty and risk. Custom Engine Interface (CEI) The LX4180 s CEI lets designers add hardware to support custom or proprietary instructions. This feature makes it easy to optimize the LX4180 for a particular application. For example, adding an instruction to find the first set bit in a data stream can improve the performance for disk controller applications. The CEI allows user-defined extensions to the MIPS ALU opcode set to be processed by a custom engine, in much the same way that standard MIPS ALU opcodes are processed by the LX4180 ALU. The CEI supplies the custom engine with the opcode and two 32-bit operands. One operand comes from the LX4180 register file, and the second operand is either from the register file, or is a 16-bit sign-extended immediate. The custom engine decodes the opcode, executes the instruction, and returns the result to the LX4180 CPU on the CEI s 32-bit result bus. The CEI provides a stall signal to support slower or multi-cycle operations. Coprocessor Interface (CI) The LX4180 CI lets designers add specialized coprocessors such as floating point units. Three CIs are included with the standard LX4180 configuration. The CI monitors instruction decode, and when a coprocessor instruction is recognized, moves the data to or from the indicated coprocessor. For branch instructions, the CI synchronizes a set of user-defined coprocessor condition flags and passes them to the LX4180 sequencer for testing. The CI provides a variable-width data bus, a 5-bit address, and independent read and write selects for coprocessor registers and control registers. The LX4180 supports single-cycle coprocessor access and transfer. Ease of Implementation for SOC The LX4180 takes advantage of advances in EDA tools, design methodology, and silicon technology to make implementation in silicon fast and predictable. Compatible with ASIC Design Methodology Lexra developed the LX4180 using the same ASIC tools and methodologies its customers use. As a result, the LX4180 can be integrated into an SOC ASIC without the custom tools or circuit design traditionally required for processors. For testability purposes, the LX4180 CPU core includes scan control signals. This allows a simple test interface to flexibly test the LX4180 with customer-supplied logic. The table below shows EDA tools currently supported for the LX4180. Design Flow Step Simulation Synthesis Static Timing DFT Place & Route Tools Supported Cadence Verilog-XL Synopsys VCS Synopsys Design Compiler Synopsys Motive SynopsysPrimeTime Synopsys TestGen Avant! Apollo Portable Traditionally, porting a processor to a new silicon process requires three to six months of effort, or longer. The LX4180 has been designed to provide fast and easy silicon process portability in an average of six weeks, without sacrificing high performance and small die size. The LX4180 is a 100% cell-based design that has been carefully tuned to avoid portability problems typically associated with register files and data paths, and with reset simulation. All transactions within the LX4180 and at its interfaces occur on the positive edge of the processor clock. Unlike most processors, two-phase clocks are not used. As a result, the LX4180 does not require Phase Locked Loop (PLL) technology, a common source of portability problems. Available as RTL Core or SmoothCore Lexra provides two delivery options for the LX4180, to support -5-

6 two different customer development and business models: ASIC and COT (Customer Owned Tooling). For ASIC designers, the RTL core provides fully scantestable Verilog source code for the LX4180. It can be targeted with commercial EDA tools to any ASIC vendor s standard cell or gate array library. Depending upon the particular process, cell library, and design methodology used, the RTL core should achieve operating performance within the range of 100 to 125 MHz. The RTL core includes a software tool that allows designers to configure the LX4180 for the number of memory interfaces, inclusion or exclusion of options such as the MAC and EJTAG interface, and target speed and cell library. The configuration tool generates a reference Verilog simulation model for the LX4180, plus makefiles and scripts for each step of the design flow. The complete set of deliverables for the RTL core includes: Verilog RTL source code for the LX4180 LConfig configuration tool System level test bench Synthesis scripts Floorplanning guidelines About Lexra Lexra is a leading developer of RISC and DSP cores for the embedded market. Lexra is headquartered in Waltham, MA, with sales and support offices worldwide. More information can be found at Copyright 1998, 1999, Lexra Inc. SmoothCore is a trademark of Lexra Inc. All other trademarks are the property of their owners. For COT designers who manufacture at popular foundries such as IBM and UMC, the SmoothCore is quickest, lowest cost, and fastest performance choice. The SmoothCore is an optimized hard macro that has been implemented and verified on a specific foundry process. All datapath, register file, and interface optimizations have been performed to ensure the smallest die size and fastest performance possible. The SmoothCore includes the following deliverables: GDS II layout database DRC/LVS result log file Encrypted Verilog RTL and gate level simulation models Post-layout SDF timing files for target process Behavior model for synthesis and static timing analysis Scan-based test pattern that achieves 99.5% fault coverage System level test bench -6-