Logic Synthesis. Logic Synthesis. Gate-Level Optimization. Logic Synthesis Flow. Logic Synthesis. = Translation+ Optimization+ Mapping

Transcription

1 Logic Synthesis Logic Synthesis = Translation+ Optimization+ Mapping Logic Synthesis 2 Gate-Level Optimization Logic Synthesis Flow 3 4

2 Design Compiler Procedure Logic Synthesis Input/Output 5 6 Design Environment Beware that the default settings are not realistic conditions. Input drive is not infinite Capacitive loading is usually not zero Consider process, temperature and voltage (PVT) variations. The operating environment affects the components selected from the target library and timing through your design. The real world environment your define describe the conditions that the circuit will operate within. 7 Describing Design Environment 8

3 Operating Condition Operating condition model scales components delay and directs the optimizer to simulate variations in process, temperature and voltage. 9 Design Constraints Constraints are goals that the synthesizer uses for optimizing a design into a target technology library. Design rule constraints: technology-specific restriction: maximum transition maximum fanout maximum capacitance Optimization constraints: design goals and requirements: maximum delay/minimum delay maximum area maximum power 10 Constraint-Driven Technology Dependent 11 12

4 Design Compiler Tutorial (1/5) compile_dc define_design_lib WORK -path /home/users/guest/vlsi/syn/work analyze -f VHDL /home/users/guest/vlsi/syn/fsm.vhd elaborate FSM current_design FSM link uniquify current_design FSM create_clock -period 10 Clock set_input_delay -clock Clock 1 SlowRAM set_output_delay -clock Clock 1 {Read Write} Design Compiler Tutorial (2/5) compile -ungroup_all -map_effort medium compile -incremental_mapping -map_effort medium check_design report_constraint -all_violators write -f verilog -output FSM.v write_sdc FSM.sdc write_sdf -version 2.1 FSM.sdf write -hier -output FSM.db report_timing > timing.rep report_cell > cell.rep report_power > power.rep quit Design Compiler Tutorial (3/5) Design Compiler Tutorial (4/5) Log in to your ECEL account. Create a design folder, we use /VLSI/SYN in the following example. Upload your VHDL/Verilog codes and the script (compile_dc) into your design folder. In the Linux command window, type the following > mkdir WORK > source settings > dc_shell f compile_dc

5 Design Compiler Tutorial (5/5) Check your.v netlist file. Below is the netlist synthesized from the FSM example. Place and Route P&R Flow Design & Timing Setup Floorplanning Timing Setup Timing-Driven: The P&R tool optimizes the logic gates, places and routes them to meet all timing constraints. Timing Constraints == Speed Goals Placement CTS Routing Design for Manufacturing 19 20

6 Floorplan Floorplanning must take into account blocks of varying function, size, and shape. Must Floorplan the Chip before P&R Main considerations: Space Allocation Signal Routing Power Supply Routing Clock Distribution Pad-Limited Design Core-Limited Design 23 24

7 Placement Standard cells are placed in placement rows. Placement rows are commonly abutted to reduce core area. Clock Tree Synthesis (CTS) Clock Distribution Tree: Clocks are generally distributed via wiring trees. Use multiple drivers to distribute driver requirements. Reduce clock skew and clock latency. Clock Tree Synthesis (CTS): After Placement CTS creates or synthesizes a buffered and balanced clock tree network. After Routing CTO further optimizes the clock tree Before CTS Effects of CTS 27 28

8 Routing Critical Path Create physical connections based on logical connectivity -- Connect signal pins by routing metal interconnects Routed paths must meet timing, clock skew, max cap/trans requirements Metal routes must meet physical DRC requirements 29 Standard Cell Library Standard Cells A standard cell library is a collection of low level logic functions such as AND, OR, INV, flip-flops, latches and buffers. These cells are realized as fixed height, variable width full custom cells. The key aspect with these libraries is that they are of a fixed height, which enables them to be placed in rows, easing the process of automated digital layout. The cells are typically optimized full custom layouts, which minimize delays and area. 31 INV NAND NOR DFF A standard cell library must contain at least the 4 cells above to be able to implement any function. 32

9 Standard Cells IO_PAD GND_PAD VDD_PAD FILL NAND3 Additionally, you can expand the standard cell library to include additional cells like I/O Pads, FILL, and multiple-input gates (e.g. a 3-input NAND gate). 33 Main Components Layout Abstract (Cadence LEF format ): Simple representations of the standard cells abstracts only include information that is pertinent to the place-and-route tools, e.g. metal and via layers. Cadence Abstract Generator Timing Abstract (Synopsys Liberty format): Provides functional definitions, timing, power and noise information for each cell. Synopsys SignalStorm 34 Additional Components Full Layout SPICE Model Verilog / VHDL Models Parasitic Extraction Models DRC Rule Decks Physical Implementation Gate-level Netlist NAND2X1 U1138 (.A(n746),.B(n747),.Y(n748) ); NAND2X1 U1139 (.A(n501),.B(n782),.Y(n749) ); NOR2X1 U1140 (.A(n746),.B(n715),.Y(n743) ); Physical Implementation 35 Standard Cell Library create_clock period 10 set_input_delay max 1.2 set_output_delay max 2.5 set_load Timing Constraint P&R d Layout 36

10 Physical Verification DRC: Design Rule Check Verifies if the design violates any fabrication rules, associated with the target process technology (metal width/space, antenna ratio, etc) ERC: Electrical Rule Check Verifies that there are no short or open circuits with power and ground as well as resistors/capacitors/transistors with floating nodes (part of LVS) LVS: Layout VS Schematic Check Verifies that the final physical design matches the logical (schematic) version in terms of correct connectivity and number of electrical devices. 37 Encounter Tutorial (1/3) encounter.conf # Specify the name of your toplevel module set my_toplevel FSM encounter.tcl # Create Initial Floorplan floorplan -r Encounter Tutorial (2/3) Create a design folder, we use /VLSI/PAR in the following example. Upload the following files into your design folder (1) [*.map]: gds2_encounter.map gds2_icfb.map gds2_seultra.map (2) [*.conf]: encounter.conf pathmill.conf (3) [*.v]: (your netlist from synthesis).v osu025_stdcells.v (4) [script]: encounter.tcl osucells_enc2icfb In the SunOS command window, type the following > source /cds/settings soc23 > encounter init encounter.tcl Encounter Tutorial (3/3) After P&R d successfully, you will have final.gds2 and final.v files.