EE 595. Part IV Basic Elements in VHDL. EE 595 EDA / ASIC Design Lab

Transcription

1 EE 595 Part IV Basic Elements in VHDL

2 Identifiers An identifier can be any length, in other words, as many characters as desired An identifier case insensitive, meaning that there no difference between uppercase and lowercase letters. (For example XOR2_OP2 and XOr2_Op denote the same identifier.) The allowed characters are a-z (lowercase letters), A-Z (uppercase letters), 0-9 (numerals), and _ (underscore). The first character a letter and the last character must not be underscore. No adjacent underscore are allowed.

3 Identifiers (cont d) The identifiers dcussed in the previous slide are called basic identifiers and their construction rules can, at times, be overly restrictive. For example digital system data books often designate a part name with leading numerals, such as 74HC00. Digital system data books also often designate active-0 signal state with a leading slash, such as /ALARM, or a trailing dash, such as ALARM-. These sample names are not legal VHDL names. The inability to express these names in VHDL impedes describing Exting designs in VHDL and often leads to cumbersome and awkward. Hence VHDL-93 provides an enhanced set of rules constructing identifiers that include both the basic identifiers and more general identifiers, called exted identifiers.

4 Exted Identifiers Rules of constructing exted identifiers in VHDL-93 are given An exted identifier can be any length, in other words, as many characters as desired. An exted identifier must be delimited by leading and trailing backslashes, \(for example, \2XOR_OP\). The allowed characters are any graphic character. Graphic characters include all the characters allowed for VHDL-93 basic identifiers plus special characters such as dash -, asterk *, A circumflex A, and e umlaut e. Within the enclosing backslashes, graphic characters can appear in any order, except that a backslash used as part of an exted identifier must be denoted by two adjacent backslashes. (For example, XOR\2 denoted by \XOR\\2\). An exted identifier case sensitive, meaning that there a difference between uppercase and lowercase letters. (For example, \XOR2_OP\ and \XOr2_Op\ denote different identifiers.)

5 Exted Identifier (cont d) An exted identifier different from any keyword or basic identifier. (Thus, \entity\ a legal exted identifier because it different entity. Also, the exted identifier \XOR2_OP\ and the basic identifier XOR2_Op do not denote same name.

6 Data Objects There are four types of objects in VHDL Constants Variables Signals Files The scope of an object as follows Objects declared in a package are available to all VHDL descriptions that use that package Objects declared in an entity are available to all architectures associated with that entity Objects declared in an architecture are available to all statements in that architecture Objects declared in a process are available only within that process

7 Data Objects (cont d) Signal - Values scheduled in the future, only means to communicate between processes. It Global, it uses up simulator time. Constants - Value fixed during initialization and can only be manipulated by a debugger. It names a specific value. Variables - Value assigned immediately when the line executed and valid within processes and subprograms. (Local storage or wires) Note Names are not case sensitive, but must not be reserved words.

8 Data Objects Constants Name assigned to a specific value of a type Allow for easy update and readability Declaration of constant may omit value so that the value assignment may be deferred Facilitates reconfiguration Declaration syntax constant CONSTANT_NAME TYPE_NAME [= [= VALUE]; Declaration examples constant PI PI real real = = 3.14; 3.14; constant SPEED integer; constant VEC3 VEC3 Bit_Vector (0 (0 TO TO 3) 3) = = 1101 ;

9 Data Objects Variables Provide convenient mechanm for local storage E.g. loop counters, intermediate values, etc. Scope process in which they are declared VHDL 93 provides for global variables, to be dcussed in the Advanced Concepts in VHDL module All variable assignments take place immediately No delta or user specified delay incurred Declaration syntax variable VARIABLE_NAME TYPE_NAME [= [= VALUE]; Declaration examples variable OPCODE Bit_Vector(3 DOWNTO 0) 0) = ="0000"; variable FREQ FREQ integer;

10 Data Objects Variables (cont d) Can be scalar or array and can be constrained and initialized variable ABC ABC Bit; Bit; variable DEF DEF integer range range 0 to to 9 = = 3; 3; Local Data inside a process or (subprogram) Assigned immediately Variable assignments do not use any simulated time Right hand side must match the type of the left hand Side type Right hand side can be an expression using operators...

11 Data Objects Signals Ports are signals that communicate with modules Architecture signals are only vible internally Global signals are stored in packages Signals can be scalar or array and can be initialized Example signal ABC Bit Bit = = 0 ; Signals are declared in entity or architecture and assigned with <= Assignment executes in simulated time (scheduled) Example ABC ABC <= <= 1 1 after after5 ns; ns;

12 Data Objects Signals (cont d) Used for communication between VHDL components Real, physical signals in system often mapped to VHDL signals ALL VHDL signal assignments require either delta cycle or userspecified delay before new value assumed Declaration syntax signal signal SIGNAL_NAME TYPE_NAME [= [= VALUE]; Declaration and assignment examples signal BRDY BRDY Bit; Bit; BRDY BRDY <= <= 0 0 after after 5ns, 5ns, 1 1 after after 10ns; 10ns;

13 Data Objects Signals (cont d) library library IEEE; IEEE; use use IEEE.STD_LOGIC_1164.all; IEEE.STD_LOGIC_1164.all; package package SIGDECL SIGDECL signal signal VCC VCC std_logic std_logic = = 1 ; 1 ; signal signal GROUND GROUND std_logic std_logic = = 0 ; 0 ; subtype subtype BUS_TYPE BUS_TYPE Bit_vector Bit_vector (0 (0 TO TO 7) 7) SIGDECL; SIGDECL; Global signal (in package) Global signal (in entity) architecture architecture DATAFLOW DATAFLOW of of BOARD_DESIGN BOARD_DESIGN signal signal INT_BUSBUS_TYPE; INT_BUSBUS_TYPE; use use Work.SIGDECL.all; Work.SIGDECL.all; entity entity BOARD_DESIGN BOARD_DESIGN port port (DATA_IN (DATA_IN in in BUS_TYPE; BUS_TYPE; DATA_OUT DATA_OUT out out BUS_TYPE); BUS_TYPE); signal signal SYS_CLK SYS_CLK STD_LOGIC STD_LOGIC = = 1 ; 1 ; BOARD_DESIGN; BOARD_DESIGN; Local Signal (in Architecture)

14 Data Objects Signals Versus Variables Th example highlights the difference between signals and variables architecture TEST1 TEST1of of MUX MUX signal signal X Bit Bit = ='1'; '1'; signal signal Y Bit Bit = ='0'; '0'; process (IN_SIG) X <= <= IN_SIG IN_SIG XOR XOR Y; Y; y <= <= IN_SIG IN_SIG XOR XOR X; X; process; TEST1; architecture TEST2 TEST2 of of MUX MUX signal signaly Bit Bit = ='0'; '0'; process (IN_SIG) variable X Bit Bit = ='1'; '1'; X = = IN_SIG IN_SIG XOR XOR Y; Y; Y <= <= IN_SIG IN_SIG XOR XOR X; X; process; TEST2; Assuming 1 -> 0 transition on in_sig, what are the resulting values for y in both cases?

15 Data Objects Signals Versus Variables (cont d) A key difference between variables and signals the assignment delay A 0 ->1 Time A B C OUT_1 OUT_2 architecture architecture SIG_EX SIG_EX of of TEST TEST signal signal A, A, B, B, C, C, OUT_1, OUT_1, OUT_2 OUT_2 Bit; Bit; process process (A, (A, B, B, C, C, OUT_1, OUT_1, OUT_2) OUT_2) OUT_1 OUT_1 <= <= A NAND NAND B; B; OUT_2 OUT_2 <= <= OUT_1 OUT_1 XOR XOR C; C; process; process; SIG_EX; SIG_EX; d d Holds prev. value Holds prev. value

16 Data Objects Signals Versus Variables (cont d) A 0 ->1 Time A B C OUT_3 OUT_ d architecture architecture VAR_EX VAR_EX of of TEST TEST signal signal A,B,C,OUT_4 A,B,C,OUT_4 Bit; Bit; process process (A, (A, B, B, C) C) variable variable OUT_3 OUT_3 Bit; Bit; OUT_3 OUT_3 = = A NAND NAND B; B; OUT_4 OUT_4 <= <= OUT_3 OUT_3 XOR XOR C; C; process; process; VAR_EX; VAR_EX; Immediate Change Schedule Change

17 Data Objects Signals Versus Variables (cont d) Signal Assignment Variable Assignment Signal Values are Scheduled Variable Values are not Scheduled Can have delay Values updated without delay Signal updated only when all processes are susped (waiting). Variables updated immediately within the process (while the process executing)

18 Data Objects Files Files provide a way for a VHDL design to communicate with the host environment File declarations make a file available for use to a design Files can be opened for reading and writing In VHDL87, files are opened and closed when their associated objects come into and out of scope In VHDL93 explicit FILE_OPEN() and FILE_CLOSE() procedures were added The package STANDARD defines basic file IO routines for VHDL types The package TEXTIO defines more powerful routines handling IO of text files

19 Data Types All declarations in VHDL, i.e. ports, signals, and variables must specify their corresponding type or subtype before being used. Types Access Composite Scalar Array Record Integer Real Enumerated Physical

20 Data Types (cont d) VHDL a rich language with many different data types.the most common data types are bit a 1-bit value representing a wire. (Note IEEE standard 1164 defines a 9-valued replacement for bit called std_logic). bit_vector an array of bits. (Replaced by std_logic_vector in IEEE 1164) boolean a True/False value. integer a signed integer value, typically implemented as a 32-bit data type. real a floating point value. enumerated used to create custom data types. record used to app multiple data types as a collection. array can be used to create single or multiple dimension arrays. access similar to pointers in C or Pascal file used to read and write dk files. Useful for simulation physical used to represent values such as time, voltage, etc.. using symbolic units of measure (such as ns or ma )

21 Data Types Character Literals A single ASCII character in single quotes or an identifier for a non printing character a A cr esc Character string an array of characters in double quotes hold time out of range

22 Data Types Bit Literals Bit can only be 0 1 Vors often ext VHDL defined types with other values Bit_Vector an array of Bits defined in double quotes Example Base precedes sequence Binary B, default if no base specified Octal O Hexadecimal X Example X 7E

23 Data Types Bit Type Extensions Problems with type BIT resolved with the use of Multi-Valued Logic (MVL) Until early 1992, there was no standard Nine state system defined and agreed by IEEE (Standard IEEE 1164) Vors usually ext the data types for simulation (MVL7, IEEE.std_logic_1164, MVL9) Z high impedance for three state driver Also Uninitialized, X - unknown, Strong 0 and 1, Weak L and H, Don t Care, etc. Examples type BIT3 ( 0, 1, Z ); type VALUE4 ( X, 0, 1, Z );

24 Data Types Standard Logic type type STD_ULOGIC STD_ULOGIC ( ( U U uninitialized uninitialized X X forcing forcing to to unknown unknown 0 0 forcing forcing to to forcing forcing to to 1 1 Z Z high high impedance impedance (Three (Three State) State) W W weak weak unknown unknown L L weak weak 0 0 H H weak weak don t don t care care ); ); std_ulogic std_ulogic std_ulogic_vector std_ulogic_vector std_logic std_logic std_logic_vector std_logic_vector Defined in Package Std_Logic_1164 Std_Logic has same values as Std_ulogic? A B Z

25 Data Types Rules to use std_logic and std_ulogic signal signala,b, Z signal signalres_z std_ulogic; std_logic; Z <= <= A; A; RES_Z <= <= A; A; A Z A RES_Z A B? Z A B? RES_Z Z <= <= A; A; Z <= <= B; B; RES_Z <= <= A; A; RES_Z <= <= B; B; Cannot assign std_logic_vector to std_ulogic_vector

26 Data Type std_logic Properties std_ulogic std_ulogic_vector std_logic std_logic_vector Std_ulogic benefits Gives Gives errors errors when when accidentally have have two two drivers drivers Std_logic benefits Other Other standards based based on on it it Gate Gate Level Level Simulation Mathematical Functions Synthes tools tools only only output outputnetlts in in one one data data type type Required so so tri-state tri-state busses busses work work Generally no no simulation speed speed overhead std_logic best when used for RTL

27 Data Type bit_vector VHDL has package standard type declarations including bit_vector which an array of bits (unconstrained) Assigned examples to C of type bit_vector of 4-Bits C = 1010 ; C = S & T & M & V; C = ( 1, 0, 1, 0 ); C = 3; Constant bit_vector 4 1-bit signals concatenated 4 Bit Aggregate Invalid

28 Data Type Boolean Literals Boolean pre-defined to be False, True Relational Operators (=, <=, >=, /=) produce a Boolean result Boolean values can be tested in if statements and assigned A Boolean not a Bit and has no pre-defined relationship to a Bit A user conversion routine could define a Bit/Boolean relationship.

29 Data Type Built-in and Pre-defined Types A few types are built-in the language/compiler Most types pre-declared in the package standard Bit, Boolean, Character, Bit_Vector, string, Line, Text Example of type declaration from package type Boolean (False, True); User needs to declare types default initial value Real array Integer array Special types Constants, signals and variables must be of a previously declared type

30 Data Type Scalar Types Integer Minimum range for any implementation as defined by standard - 2,147,483,647 to 2,147,483,647 Example assignments to a variable of type integer architecture architecture TEST_INT TEST_INT of of test test process process (X) (X) variable variable A A integer; integer; A = = 1; 1; OK OK A = = -1; -1; OK OK A = = 1.0; 1.0; illegal illegal process; process; TEST_INT; TEST_INT;

31 Data Type Scalar Types (cont d) Integer Represent Integer values with fixed point Operators such as +, -, * can be used Minimum range specified by standard -2, 147, 483, 647 to +2, 147, 483, 647 Example Users can specify a particular range of values (constraint)

32 Data Type Scalar Types (cont d) Real Minimum range for any implementation as defined by standard -1.0E38 Example assignments to a variable of type real architecture architecture TEST_REAL TEST_REAL of of TEST TEST process process (X) (X) variable variable A A real; real; A = = 1.3; 1.3; OK OK A = = -7.5; -7.5; OK OK A = = 1; 1; illegal illegal A = = 1.7E13; 1.7E13; OK OK A = = ns; ns; illegal illegal process; process; TEST_REAL; TEST_REAL;

33 Data Type Scalar Types (cont d) Real Literals Represent Floating Point values Format + or - number.number [E + or - number] Example decimal point required illegal integer value value E E

34 Data Type Range Constraints Simulator checks for valid type and range on assignment Range constraint specifies a restricted range Examples integer range 0 to to9 0 to to9 (Integer type type implicit because of of literals) real realrange to to1.1 integer range (no (no constraint) Used to qualify the inted usage of data

35 Data Type Slice of an Array A subscript array reference can be used on either side of a signal or variables assignment statement Example port( port( A A in in Bit_Vector(0 Bit_Vector(0 TO TO 4); 4); Direction Direction of of Declaration Declaration C C out out Bit_Vector(8 Bit_Vector(8 DOWNTO DOWNTO 1)); 1)); and and Slice Slice must must be be same same C(6 C(6 DOWNTO DOWNTO 3) 3) <= <= A(0 A(0 TO TO 3); 3); OK OK C(5 C(5 DOWNTO DOWNTO 0) 0) <= <= A(3 A(3 DOWNTO DOWNTO 0) 0) ILLEGAL ILLEGAL Note Size of array on left and right must be equal

36 Data Type Array Assignment signal signalz_bus std_logic_vector(3 DOWNTO 0); 0); signal signalc_bus std_logic_vector(0 TO TO 3); 3); Z_BUS Z_BUS <= <= C_BUS; Z_BUS(3) Z_BUS(2) Z_BUS(1) Z_BUS(0) C_BUS(0) C_BUS(1) C_BUS(2) C_BUS(3) Elements are assigned by position, not element number Be constent in defining the direction of your arrays..

37 Data Type Array Example architecture architecture process process variable variable DATA DATA Bit_Vector(0 Bit_Vector(0 TO TO 31); 31); variable variable START START integer integer range range 0 0 TO TO 24; 24; variable variable DATA_OUT DATA_OUT Bit_Vector Bit_Vector (0 (0 TO TO 7) 7) for for i i in in 0 0 to to 7 7 loop loop DATA_OUT(i) DATA_OUT(i) = = DATA(i DATA(i + + START); START); loop; loop; process; process; Array Array Access Access

38 Data Type Array Example architecture architecture EXAMPLE EXAMPLE of of ARRAY ARRAY process(a) process(a) type type BIT4 BIT4 ARRAY(0 ARRAY(0 TO TO 3) 3) of of Bit; Bit; type type BIT8 BIT8 ARRAY ARRAY (0 (0 TO TO 7) 7) of of Bit; Bit; variable variable Q8 Q8 Bit8; Bit8; variable variable Q4A, Q4A, Q4B Q4B Bit4; Bit4; Q4A Q4A = = ( 1, ( 1, 1, 1, 1 ); 1, 1, 1 ); aggregate aggregate assignment assignment Q4B Q4B = = ; ; aggregate aggregate assignment assignment Q8 Q8 = = ( 0, 1,others ( 0, 1,others => => 0 ); 0 ); aggregate aggregate assignment assignment Q8 Q8 = = (others (others => => 0 ); 0 ); aggregate aggregate assignment assignment Q8(2) Q8(2) = = 1 ; 1 ; assignment assignment to to a a slice slice Q8(5 Q8(5 TO TO 7) 7) = = 111 ; 111 ; assignment assignment to to a a slice slice Q8 Q8 = = & ; ; concatenation concatenation process; process; EXAMPLE; EXAMPLE;

39 Data Type Scalar Types type typebinary (( ON, ON, OFF OFF ); ); some some statements architecture TEST_ENUM of oftest process (X) (X) variable A A BINARY; A = = ON; ON; OK more more statements A = = OFF; OFF; OK more more statements process; TEST_ENUM;

40 Data Type Scalar Types (cont d) Physical Require associated units Range must be specified Example of physical type declaration type typeresistance range range0 TO TO UNITS UNITS OHM; OHM; ohm KOHM KOHM = OHM; OHM; MOHM MOHM = KOHM; KOHM; UNITS; i.e. i.e. 1 KOHM KOHM i.e. i.e. 1 MOHM MOHM Time the only physical type predefined in VHDL standard

41 Data Type Scalar Types (cont d) Defined in package standard type TIME range 0 to INTEGER HIGH UNITS fs; femtosecond ps = 1000 fs; picosecond ns = 1000 ps; nanosecond us = 1000 ns; microsecond ms = 1000 us; millecond sec = 1000 ms; second min = 60 sec; minute hr = 60 min; hour UNITS;

42 Data Type Enumerated Types Defines legal values through an enumerated lt of Character Literals x Identifiers STATE_IDLE Example type typeinstruction (ADD, (ADD, SUB, SUB, LDA, LDA, LDB, LDB, STA, STA, STB, STB, XFR); XFR); type typevalue ( X, ( X, 0, 0, 1, 1, Z ); Z ); Uses symbolic codes instead of numeric values Provides for more abstract representation in source design Simulator systems require more values than 0, 1 user defines lt of possible values

43 Data Type Enumerated Type Example architecture architecturebehave of ofmp type typeinstruction (ADD, (ADD, LDA, LDA, LDB); LDB); a lt lt of of identifiers identifiers process process variable variableinst INSTRUCTION; INSTRUCTION; variable variablea, A, B B integer; integer; case caseinst when whenlda => => A = = DATA; DATA; load accumulator accumulator A when whenldb => => B = = DATA; DATA; load accumulator accumulator B when whenadd => => A = = A + B; B; add two two accumulators accumulators case;......

44 Data Types Composite Types Array Array group of elements of same type elements can be scalar or composite type multi-dimensional arrays allowed useful for modeling RAMs, ROMs, Busses used for lookup tables object(s) accessed by index

45 Data Types Composite Types Array (cont d) Array Used to group elements of the same type into a single VHDL object Range may be unconstrained in declaration Range would then be constrained when array used Example declaration for one-dimensional array (vector) type typedata_bus ARRAY (0 (0 to to 31) 31) of ofbit; 0...element indices array values... 1 variable variable X X DATA_BUS; DATA_BUS; variable variable Y Y Bit Bit Y = = X(12); X(12); Y gets gets value value of of element element at at index index 12 12

46 Data Types Composite Types Array (cont d) Example one-dimensional array using downto (DOWNTO keyword must be used if leftmost index greater than rightmost index type type REGISTER ARRAY (15 (15 DOWNTO 0) 0) of of bit; bit; variable X X REGISTER; variable Y Y bit bit 15...element indices array values... Y = = X(4); X(4); Y gets gets value value of of element at at index index 4

47 Data Types Composite Types Records Record group of different type objects element can be scalar or composite types useful for modeling data packets, instructions object(s) accessed by name

48 Data Types Composite Types Records (cont d) Records Used to group elements of possibly different types into a single VHDL object Elements are indexed via field names Examples of record declaration and usage type type BINARY BINARY ( ( ON, ON, OFF OFF ); ); type type SWITCH_INFO SWITCH_INFO record record STATUS STATUS BINARY; BINARY; IDNUMBER IDNUMBER integer; integer; RECORD; RECORD; variable variable SWITCH SWITCH SWITCH_INFO; SWITCH_INFO; SWITCH.STATUS SWITCH.STATUS = = ON; ON; SWITCH.IDNUMBER SWITCH.IDNUMBER = = 30; 30; status status of of the the switch switch e.g. e.g. number number of of the the switch switch

49 Data Types Composite Types Record Example type typedelay_entry record FALL TIME; RISE TIME; RECORD; variable DELAY_TIME DELAY_ENTRY; DELAY_TIME.FALL = = 10NS DELAY_TIME.RISE = = 12NS;

50 Data Types Subtypes Subtype Allows for user defined constraints on a data type e.g. a subtype based on an unconstrained VHDL type May include entire range of base type Assignments that are out of the subtype range are illegal Range violation detected at run time rather than compile time because only base type checked at compile time Subtype declaration syntax subtype NAME NAME BASE_TYPE range range <user <user range>; Subtype example subtype FIRST_TEN integer range range 0 TO TO 9; 9;

51 Data Types Subtypes (cont d) Subset of a base type May contain 1 or all elements of the base type Allows assignments of elements between base type and subtype that are within the range of the subtype The IEEE resolved type std_logic a subtype of the resolved base std_ulogic Adds constraints to increase usefulness of range checking and minimize number of options in CASE statements

52 Data Types Subtypes (cont d) A new subtype can be created by constraining an exting type Example range constraint subtype DIGIT DIGIT integer range range 0 TO TO 9; 9; type typeinstruction (ADD, (ADD, SUB, SUB, MUL, MUL, DIV, DIV, LDA, LDA, STA, STA, OUTA, OUTA, XFR); XFR); subtype ARITHMETIC INSTRUCTION range rangeadd TO TO DIV; DIV; subtype BYTE BYTE Bit_Vector(1 TO TO 8); 8); creating an an array array subtype Simulators perform range and type checking during assignments More convenient for frequently used data types (no repeated constraints) Provides for more object oriented design and better documentation

53 Data Types Summary All declarations of VHDL ports, signals, and variables must include their associated type or subtype Three forms of VHDL data types are Access pointers for dynamic storage allocation Scalar includes Integer, Real, Enumerated, and Physical Composite includes Array, and Record A set of built-in data types are defined in VHDL standard User can also define own data types and subtypes

54 Attributes Attributes provide information about certain items in VHDL, e.g Types, subtypes, procedures, functions, signals, variables, constants, entities, architectures, configurations, packages, components General form of attribute use NAME'ATTRIBUTE_IDENTIFIER read as as tick tick VHDL has several predefined, e.g X'EVENT TRUE when there an event on signal X X'LAST_VALUE returns the previous value of signal X Y'HIGH returns the highest value in the range of Y X'STABLE(t) TRUE when no event has occurred on signal X in the past t time

55 Attributes Regter Example (cont d) The following example shows how attributes can be used to make an 8- bit regter Specifications Triggers on ring clock edge Latches only on enable high Has a data setup time of x_setup Has propagation delay of prop_delay entity entity 8_BIT_REG 8_BIT_REG generic generic (X_SETUP, (X_SETUP, PROP_DELAY PROP_DELAY TIME); TIME); port(enable, port(enable, CLK CLK in in QSIM_STATE; QSIM_STATE; A in in QSIM_STATE_VECTOR QSIM_STATE_VECTOR (7 (7 DOWNTO DOWNTO 0); 0); B out out QSIM_STATE_VECTOR QSIM_STATE_VECTOR (7 (7 DOWNTO DOWNTO 0)); 0)); 8_BIT_REG; 8_BIT_REG; qsim_state type being used - includes logic values 0, 1, X, and Z

56 Attributes Regter Example (cont d) The following architecture a first attempt at the regter The use of 'STABLE to used to detect setup violations in the data input architecture architecture FIRST_ATTEMPT FIRST_ATTEMPT of of 8_BIT_REG 8_BIT_REG process process (CLK) (CLK) if if (ENABLE (ENABLE = = '1') '1') and and A'STABLE(X_SETUP) A'STABLE(X_SETUP) and and (CLK (CLK = = '1') '1') then then B <= <= A after after DELAY; DELAY; if; if; process; process; FIRST_ATTEMPT; FIRST_ATTEMPT; What happens if a does not satfy its setup time requirement of x_setup?

57 Attributes Regter Example (cont d) The following architecture a second and more robust attempt The use of 'LAST_VALUE ensures the clock ring from a value of 0 architecture architecture BEHAVIOR BEHAVIOR of of 8_BIT_REG 8_BIT_REG process process (CLK) (CLK) if if (ENABLE (ENABLE = = '1') '1') and and A'STABLE(X_SETUP) A'STABLE(X_SETUP) and and (CLK (CLK = = '1') '1') and and (CLK'LASTVALUE (CLK'LASTVALUE = = '0') '0') then then B <= <= A after after DELAY; DELAY; if; if; process; process; BEHAVIOR; BEHAVIOR; A THEN clause could be added to define the behavior when the requirements are not satfied

58 Operators Operators can be chained to form complex expressions, e.g. Can use parentheses for readability and to control the association of operators and operands Defined precedence levels in decreasing order Mcellaneous operators **, abs, not Multiplication operators *, /, mod, rem Sign operator +, - Addition operators +, -, & Shift operators sll, srl, sla, sra, rol, ror Relational operators =, /=, <, <=, >, >= Logical operators AND, OR, NAND, NOR, XOR, XNOR RES RES <= <= A and andnot(b) not(b) or ornot(a) and andb; B;

59 Logical Operators Operators and or xor xnor nand nand nor not Definition conjunction djunction exclusive djunction complement exclusive djunction complement conjunction complement conjunction complement djunction complement. VHDL-93 The predefined logic operator xnor provided only in VHDL-93.

60 Logical Operators (cont d) There are a few rules for evaluating VHDL logic operators that unfortunately do not align exactly with switching algebra theory, so it important to note them. The and, or, nand and nor logic operators are called short-circuit operators because the right operand not evaluated if the value of the left operand not evaluated if the value of the left operand determines the result of the logic operator. For example, consider the following signals assignment statement. TEST_SIG <= <= OPR_A and and OPR_B;

61 Operators Examples The concatenation operator & variable variable SHIFTED, SHIFTED, SHIFTIN SHIFTIN Bit_Vector Bit_Vector (0 (0 TO TO 3); 3); SHIFTED SHIFTED = = SHIFTIN(1 SHIFTIN(1 TO TO 3) 3) & '0'; '0'; SHIFTIN SHIFTED The exponentiation operator ** x = = 5**5 5**5 5^5 OK OK y = = 0.5**3 0.5**3 0.5^3 OK OK x = = 4**0.5 4**0.5 4^0.5 Illegal Illegal y = = 0.5**(-2) 0.5^(-2) OK OK

62 Operators Examples The addition operator + Logical Operators entity entity ADD ADD port port ( ( B,C B,C in in Bit; Bit; Z Z out out Bit); Bit); ADD; ADD; architecture architecture RTL RTL of of ADD ADD RTL; RTL; Z Z <= <= A + B; B; library library IEEE; IEEE; use use IEEE.Std_Logic_1164.all; IEEE.Std_Logic_1164.all; entity entity MVLS MVLS port port (A, (A, B,C B,C in in Std_Logic; Std_Logic; Z Z out out Std_Logic); Std_Logic); ADD; ADD; architecture architecture LOGIC LOGIC of of MVLS MVLS Z Z <= <= A AND AND NOT NOT (B (B OR OR C); C); RTL; RTL;

63 Operators Examples Relational Operators > greater greater than than /= /= inequality inequality >= >= greater greater than than or or equal equal to to if A = B then Z<= 1 ; <= <= less less than than or or equal equal to to = equality equality < less less than than

64 Operators Questions Which statements are correct in VHDL? architecture architecturequiz of of OPERATORS OPERATORS signal signal BOOL BOOL boolean; boolean; signal signal A_INT, A_INT, B_INT, B_INT, Z_INT Z_INT integer integerrange range 0 TO TO 15; 15; signal signal Z_BIT Z_BIT Std_Logic; Std_Logic; signal signal A_VEC, A_VEC, B_VEC, B_VEC, Z_VEC Z_VEC Std_Logic_Vector Std_Logic_Vector (3 (3 DOWNTO DOWNTO 0); 0); Z_BIT Z_BIT <= <= A_INT A_INT = B_INT; B_INT; BOOL BOOL <= <= A_INT A_INT > B_VEC; B_VEC; Z_VEC Z_VEC <= <= A_VEC A_VEC & B_VEC; B_VEC; Z_VEC Z_VEC <= <= A_VEC(1 A_VEC(1 TO TO 0) 0) & A_VEC(1 A_VEC(1 DOWNTO DOWNTO 0); 0); Z_VEC Z_VEC <= <= A_VEC(1 A_VEC(1 DOWNTO DOWNTO 0) 0) & B_VEC(1 B_VEC(1 DOWNTO DOWNTO0); 0); ; ;

65 Summary VHDL a worldwide standard for the description and modeling of digital hardware VHDL gives the designer many different ways to describe hardware Familiar programming tools are available for complex and simple problems Sequential and concurrent modes of execution meet a large variety of design needs Packages and libraries support design management and component reuse