Introduction to Microcomputer Systems Addressing modes

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1 Dept. of Computer Science and Engineering Introduction to Microcomputer Systems Overview Addressing mode Source form Abbreviation Description Inherent INST (no externally supplied operands) INH Immediate INST #opr8i or INST #opr16i IMM Operands (if any) are in CPU registers Operand is included in instruction steam; 8-bit or 16- bit size implemented by context Direct INST opr8a DIR Operand in the lower 8-bits of an adress in tghe range $ $00FF Extended INST opr16a EXT Operand is a 16-bit address Relative (5-bit offset) (predecrement) (preincrement) INST rel8 or INST rel16 REL Effective address is the value in PC plus an 8-bit or 16-bit relative offset value INST oprx5,xysp IDX Effective adress is the value in X, Y, SP or PC plus a 5- bit signed constant value INST oprx3,-xys IDX Effective adress is the value in X, Y or SP autodecremented by 1 to 8 INST oprx3,+xys IDX Effective adress is the value in X, Y or SP autoincremented by 1 to 8 CHALMERS UNIVERSITY OF TECHNOLOGY Campus Lindholmen Sida 1 Dept. Of Computer Science and Engineering Visiting address: Hörselgången 11, house Jupiter 4:th floor P.O.Box 8873 SE Göteborg

2 Addressing mode Source form Abbreviation Description (postdecrement) INST oprx3,xys- IDX Effective adress is the value in X, Y or SP. The value is postdecremented by 1 to 8 (postincrement) (accumulator offset) (9-bit offset) (16-bit offset) - indirect (16-bit offset) - indirect (D accumulator offset) INST oprx3,xys+ IDX Effective adress is the value in X, Y or SP. The value is postincremented by 1 to 8 INST abd,xysp IDX Effective adress is the value in X, Y, SP or PC plus thye value in A, B or D INST oprx9,xysp IDX1 Effective adress is the value in X, Y, SP or PC plus a 9- bit signed constant value INST opr16,xysp IDX2 Effective adress is the value in X, Y, SP or PC plus a 16- bit constant value INST [oprx16,xysp] [IDX2] The value in X, Y, SP or PC plus a 16-bit constant offset points to the effective address INST [D,sysp] [D,IDX] The value in X, Y, SP or PC plus the value in D points to the effective address Inherent addressing mode The instructions have no operand or all operands are in the internal registers. The CPU does not need to access any memory locations NOP INX; ;this instruction has no operand ;operand is in CPU register Immediate addressing mode The operands are included in the instruction stream. The pound symbol (#) is used to indicate an immediate addressing mode LDAA #$55 LDX #2034 Direct addressing mode The addressing mode is sometimes called zero-page addressing because it uses a 8-bit address to access addresses in the range $0000 to $00FF LDAA $55 ;load accumulator A from address $0055 page 2

3 STX $AC ;store the value in index register X in address $AC and $AD (since the value in index register X is 16 bits Extended addressing mode In this addressing mode the full 16-bit address of the memory location is used LDAA $1055 ;load accumulator A from address $1055 STX $25AC ;store the value in index register X in address $25AC and $25AD (since the value in index register X is 16 bits Relative addressing mode This mode is used only by branch instructions. Short and long conditional branch instructions use relative addressing mode exclusively, but branching versions of bit manipulation instructions use multiple addressing modes, including relative mode. Short branch instruction contain a signed 8-bit offset (branch step). Long branch instructions contain a signed 16-bit offset (long branch step) BEQ label ;branch to the program line marked by label if zero flag is set, continue with the next instruction otherwise addressing modes There are a number of indexed addressing modes that can be split into the following groups. addressing modes with fixed offset The effective address is the value in the X, Y, SP or PC register plus a 5-, 9- or 16-bit signed constant value contained in the instruction. The instruction does not change the value in the index register. The only difference between the variants is the total size of the opcode for the instruction. The 5-bit version give a range of -16 to +15 from the value in the base index register. The 9-bit version give a range of -256 to +255 from the value in the base index register. The 16-bit version give access to any address in the 64-Kbyte address space. Since the address bus and the offset are both 16 bits it does not matter if the offset value is considered to be signed or unsigned LDAA 0,X STAB -3,Y LDX $20,X ;load accumulator A from the address contained in X ;store accumulator B in the address contained in X minus 3 addresses ;load index register X from the address contained in index register X plus 64 ($20) addresses and from the next consecutive address ((X)+$20):(X)+$20+1) page 3

4 16-bit constant indirect indexed addressing The addressing mode adds a 16-bit instruction-supplied offset to the address in the base index register to form the address of a memory location that contains a pointer to the memory location affected by the instruction. The instruction itself does not point to the address of the memory location to be acted on, but rather to the location of a pointer to the address to be acted on. The square brackets distinguish this addressing mode from 16-bit constant offset indexing LDAA [10,X] ;the instruction first adds the value 10 to the value in X and then a pointer to the memory location to be acted on is fetched memory location pointed at by this sum addressing modes pre-/post decrement/increment In this addressing mode the index register can be automatically decremented or incremented before or after the indexing takes place. The pre-decrement and pre-increment versions adjust the value of the index register before accessing the memory location affected by the instruction. The index register retains the changed value after the instruction executes. Post-decrement and post-increment versions of the addressing mode use the initial value in the index register to access the memory location affected by the instruction, then change the value of the index register. The index register can be decremented or incremented by any integer value in the ranges -8 through -1 or 1 through 8 LDAA 1,-X STX 3,SP+ ;decrement the value in X by one then load accumulator A from the new address in X ;store the value in X at the address pointed at by the stack pointer, and the next address since X is 16 bits, then increase the value of the stack pointer SP by 3 Accumulator offset indexed addressing In this addressing mode the effective address is the sum of the value in the base index register and the unsigned offset in one of the accumulators. The value in the index register itself is not changed. The index register can be X, Y, SP or PC and the accumulator can be either of the 8-bit accumulators (A or B) or the 16-bit D accumulator LDAA B,X ;load accumulator A from the new address formed by the sum of the value in index register X and the value in accumulator B Accumulator D indirect indexed addressing In this addressing mode the value in the D accumulator is added to the value in the base index register to form the address of a memory location that contains a pointer to the mem- page 4

5 ory location affected by the instruction. The instruction operand does not point to the address of the memory location to be acted on, but rather to the location of a pointer to the address to be acted on. The square brackets distinguish this addressing mode from 16-bit constant offset indexing JMP [D,X] ;jump to the address that is stored at the memory location pointed at by the sum of the value in D and the value in X page 5

N bit is set if result of operation in negative (MSB = 1) Z bit is set if result of operation is zero (All bits = 0)

N bit is set if result of operation in negative (MSB = 1) Z bit is set if result of operation is zero (All bits = 0) Addition and Subtraction of Hexadecimal Numbers. Setting the C (Carry), V (Overflow), N (Negative) and Z (Zero) bits How the C, V, N and Z bits of the CCR are changed Condition Code Register Bits N, Z,