News from the edge. Image source:

Transcription

1 News from the edge Extreme Ultraviolet (EUV) lithography is almost ready for prime time: the jump from the current 193 nm to 13.5 nm wavelength is planned for It will allow shrinking to a 5 nm feature length (7 nm seems feasible with the existing 193 nm wavelength). Read EUV Lithography to Save Moore s Law! (link on our webpage). Image source:

2 QUIZ Ch.4: How did you implement the microop. AC 1 in the lab problem? (There is no such operation defined for MARIE s ALU) 2

3 QUIZ Ch.4: Can you rewrite the microcode to avoid the undefined microop.? Hint: The only register in which we can increment is PC. 3

4 The moral of this exercise: changes are easy to make when the Control Unit is microprogrammed: We simply replace the microinstructions in the Control Store! PC X PC PC + 1 4

5 Note: In lab 10 we shall use JnS to write functions in our own programs, and the simulator will show that AC does change to the new address while JnS is executed! This simply means that the microinstruction AC 1 is in the microcode, although Table 4.9 does not list it. 5

6 A Closer Look at Chapter 5 Instruction Set Architectures

7 5.2 Instruction Formats Instructions are differentiated by the following: Number of bits per instruction. Use of a stack or use of only registers. Number of explicit operands per instruction. Operand location. Types of operations. Type and size of operands. 7

8 5.2 Instruction Formats Instruction set architectures (ISAs) are measured according to: Main memory space occupied by a program. Instruction complexity. Instruction length (in bits). Total number of instructions in the instruction set. 8

9 9 5.2 Instruction Formats Decisions we need to make when designing an ISA: Instruction length (short, long, or variable) Number of operands. Number of addressable registers. Memory organization (byte- or word addressable) Addressing modes. Choose any or all: inherent, immediate, direct, indirect or indexed Endianness

10 A.k.a. byte ordering Endianness If we have a two-byte integer, the integer may be stored in memory so that the least significant byte is followed by the most significant byte or vice versa. In little endian machines, the least significant byte comes first, i.e. it is followed by the most significant byte. Big endian machines, the most significant byte comes first (at the lower address). 10

11 Endianness Example: the hexadecimal number Memory maps are always shown low to high, from left to right or from top to bottom (0000 FFFF) Please note that the order of the bits inside the byte does not change! 11

12 QUIZ Endianness Represent the hexadecimal number ABCD2345 in big- and little-endian formats 12

13 QUIZ Endianness Represent the hexadecimal number ABCD2345 in big- and little-endian formats 13

14 Endianness pros and cons Big endian (e.g. IBM System/360, Motorola): Is more natural for human reading. The sign of the number can be determined by examining the first byte (at address offset 0). Strings and integers are stored in the same order. Network protocols are all big endian. Little endian (e.g. Intel, Atmel AVR32): Makes it easier to place values on non-word boundaries. Reducing the address size or the size of integer data does not require any arithmetic. Example 14

15 Exercise 1/333 word word boundary word 15

16 16 Exercise 1/333

17 Exercise 1/333 c. If an application needs to extend the representation size of integers from 32 to 64 bits (0x1234 0x ), which endianness is more appropriate? Big endian Little endian 17

18 Exercise 1/333 c. If an application needs to extend the representation size of integers from 32 to 64 bits (0x1234 0x ), which endianness is more appropriate? Big endian Little endian In the little endian representation, the existing bits don t need to be moved about in memory; in big endian they do! 18

19 Exercise 1/333 d. If an application needs to reduce the representation size of addresses from 64 to 32 bits, which endianness is more appropriate? Big endian Little endian 19

20 Exercise 1/333 d. If an application needs to reduce the representation size of addresses from 64 to 32 bits, which endianness is more appropriate? Big endian Little endian Here it s less clear-cut: little endian is at least as good, but, if we decide to leave the right side of big endian in place, they re equal! 20

21 Food for thought: Why is it easier to place values on non-word boundaries in little endian machines? word word boundary word 21

22 5.2.3 Storage options inside the CPU How will the CPU store data? - There are three choices: 1. stack architecture 2. accumulator architecture 3. general purpose register architecture. In choosing one over the others, the tradeoffs are simplicity (i.e. cost) of hardware design against execution speed and ease of use/programming. 22

23 stack architecture instructions and operands are implicitly taken from the stack. A stack can be accessed only at the top (not randomly). accumulator architecture one operand of a binary operation is implicitly in the accumulator. The other operand is in memory lots of bus traffic. general purpose register (GPR) architecture both/all operands can be in registers Faster than accumulator architecture. Efficient implementation for compilers. Longer instructions (Why?) longer fetch and decode times 23

24 GPR architecture Is used in most of today s CPUs. There are two/three sub-types: Memory-memory two or three operands may be in memory (but some may also be in registers). Register-memory at least one operand must be in a register. Load-store all operands must be loaded from memory before ALU operations are performed. This is the pure GPR architecture! Not used anymore in modern CPUs we ll explore a bit in the lab. 24

25 GPR architecture The registers are implemented in a small memory, internal to the CPU, called the register file: CPU Main Memory 25 Circuit diagram example

26 Not in text The registers in a GPR loadstore CPU are implemented in a small memory, called the register file 26 Image source:

27 In the GPR architecture, the number of operands and the number of available registers have a direct effect on instruction length. Example: In a GPR ISA, instructions can have up to 3 operands, which can be placed in one of 32 general-purpose registers in the register file. What is the minimum instruction length? 27

28 5.2.4 Nr. of operands and instr. length Instruction length can be: Fixed Space is wasted for the instr. w/fewer operands Fast and easy to decode (less hardware!) Easy to pipeline to gain speed Variable More efficient use of memory More complex decoding Pipelining more difficult 28

29 5.2.4 Nr. of operands and instr. length Instruction length can be: Fixed Space is wasted for the instr. w/fewer operands Fast and easy to decode (less hardware!) Easy to pipeline to gain speed Variable More efficient use of memory More complex decoding Pipelining more difficult Which one is used in the MARIE ISA? 29

30 Common compromise in real-life computers: instructions of 2 or 3 sizes Why do instr. have different lengths? Because of different # of operands: OPCODE only (zero operands) OPCODE + 1 operand OPCODE + 2 operands OPCODE + 3 operands Give examples from the MARIE ISA! 30

31 Nr. of operands and instr. length - stack architecture - In a stack ISA, instructions have zero explicit operands; each operand is taken implicitly from the top of the stack (pop), or placed on the top (push). 31

32 Appendix A.2.3 STACKS Stack = LIFO (Last-In-First-Out) list 32

33 Appendix A.2.3 STACKS Application: retracing one s steps 33

34 Appendix A.2.3 STACKS Application: reversing a string of characters Unicode: X = 0x0058, Y =????, Z =???? 34

35 Appendix A.2.3 STACKS Application: reversing a string of characters (Unicode: X = 0x0058, Y = 0x0059, Z = 0x002A) 35

36 QUIZ: What is the endianness of this architecture? 36

37 Stacks normally have 3 variables associated with them: Stack Pointer (SP) Max Stack Size Crt. Stack Size

38 Two schools of thought about the Stack Pointer: SP points to the top element on the stack SP points to the first free element above the stack Why not here? B/c each stack element has 2 Bytes! Appendix A.2.3. uses the first convention.

39 Stack-based architectures p.300 of text Stack machines use one - and zero-operand instr.: LOAD and STORE one operand: the memory address Other instructions use operand(s) from the stack implicitly zero operands: PUSH and POP operations involve only the stack s top element. Unary instr. (e.g. INCR) use the item at the top of the stack Binary instructions (e.g. ADD, MULT) use the top two 39 items on the stack.

40 Stack-based architectures Stack architectures require us to think about arithmetic expressions a little differently. We are accustomed to writing expressions using infix notation, such as: Z = X + Y Stack arithmetic requires that we use postfix notation: Z = X Y + A third option is prefix notation: Z = + X Y This is also called Polish notation, in honor of its Polish inventor, Jan Lukasiewicz ( ). RPN 40

41 QUIZ: prefix/postfix Convert the expression 3 42 to: Prefix notation: Postfix notation: 41

42 QUIZ: prefix/postfix multiple operations do it in steps! Convert the expression (3 + 4) 42 to: Prefix notation: Postfix notation: 42

43 QUIZ: prefix/postfix multiple operations do it in steps! Convert the infix expression (3 + 4) 42 to: Prefix notation: (+ 3 4) 42 = Postfix notation: (3 4 +) 42 = Conclusion: prefix and postfix notations do not require parentheses! 43

44 To do for next time: Read pp (Ch.5) and (A.2.3) Solve or resolve all examples in text and notes! 44

45 QUIZ Endianness The decimal number 257 has to be stored on 3 bytes (unusual!) in memory, starting at address 10FF. Show the addresses and the final content of the 3 bytes in big- and little-endian formats, in hex: 45

46 QUIZ: CPU architectures What are the 3 main CPU architectures? Briefly describe each. 46

47 QUIZ: CPU architectures What are the 3 main CPU architectures? Briefly describe each. 1. stack architecture operands are in an internal CPU stack 2. accumulator architecture one operand in AC, another in main memory 3. general purpose register (GPR) architecture all operands in internal register file 47

48 QUIZ: CPU architectures What are the 2/3 flavors of GPR architecture? Briefly describe each. 48

49 QUIZ: CPU architectures What are the 2/3 flavors of GPR architecture? Briefly describe each. Register-memory (and memory-memory, if you insist ) Load-store (a.k.a. pure ) 49

50 QUIZ: Prefix/postfix Which pairs are synonymous? (draw arrows) Postfix notation Polish notation (PN) Prefix notation Reverse Polish notation (RPN) 50

51 QUIZ: Prefix/postfix Which pairs are synonymous? (draw arrows) Postfix notation Polish notation (PN) Prefix notation Reverse Polish notation (RPN) 51

52 Stacks, postfix Same is true for prefix (PN), but we ll concentrate on postfix (RPN) The principal advantage of postfix notation is that parentheses are not necessary. Example: the infix expression, Z = (X Y) + (W U), becomes in postfix notation:???????????????? Hint: Do it in steps, starting inside the parentheses! 52

53 Stacks, postfix Same is true for prefix (PN), but we ll concentrate on postfix (RPN) The principal advantage of postfix notation is that parentheses are not necessary. Example: the infix expression, Z = (X Y) + (W U), becomes in postfix notation: Z = X Y W U + Hint: Do it in steps, starting inside the parentheses! 53

54 Example 5.3 Stacks, postfix Convert the infix expression (2+3) - 6/3 to postfix: 54

55 Example 5.3 Stacks, postfix Convert the infix expression (2+3) - 6/3 to postfix: / 3 The sum in parentheses takes precedence; we replace the term with

56 Example 5.3 Stacks, postfix Convert the infix expression (2+3) - 6/3 to postfix: / The division operator takes next precedence; we replace 6/3 with 6 3 /. 56

57 Example 5.3 Stacks, postfix Convert the infix expression (2+3) - 6/3 to postfix: / - The quotient 6/3 is subtracted from the sum of 2 + 3, so we move the - operator to the end. 57

58 Implementation We now have the postfix expression / - and we need to evaluate it. Idea: use a stack! Scanning the expression from left to right, push operands onto the stack, until an operator is found /

59 Pop the two operands and carry out the operation indicated by the operator. Push the result back on the stack / - 59

60 / - Push operands until another operator is found

61 / - Carry out the operation and push the result

62 Finding another operator, carry out the operation and push the result. The answer is at the top of the stack / - 62

63 Finding another operator, carry out the operation and push the result. The answer is at the top of the stack / - 63 Check: (2+3) - 6/3 = 3

64 QUIZ: Evaluating postfix expressions Use the stack-based algorithm to convert to evaluate this postfix expression. Show the stack at each step! / 64

65 Example 5.7 (p.303): How to evaluate an infix expression using different instruction formats With a three-address ISA (e.g. mainframes), the infix expression, Z = X Y + W U might be implemented like this: MULT R1,X,Y MULT R2,W,U ADD Z,R1,R2 This can be a memory address or the address of a register in a register file 65 Destination address is first operand.

66 In a two-address ISA, (e.g.,intel, Motorola), the infix expression, Z = X Y + W U might be implemented like this: LOAD R1,X MULT R1,Y LOAD R2,W MULT R2,U 66 How to evaluate an infix expression using different instruction formats ADD R1,R2 STORE Z,R1 Note: Two-address ISAs usually require one operand to be a register.

67 67 Extra-credit

68 How to evaluate an infix expression using different instruction formats In a one-address ISA (e.g. MARIE) the infix expression, Z = X Y + W U might be implemented like this: LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z 68

69 How to evaluate an infix expression using different instruction formats In a zero-address (stack) ISA (e.g. Unisys/Burroughs B and A series, Chuck Moore s Forth processors), the postfix expression, Z = X Y W U + might be implemented like this: 69 PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD POP Z Taking X from memory and placing it on the stack Taking Z from the stack and writing is back to memory

70 Recap Z = X Y W U + two-address one-address three-address zero-address (stack) MULT R1,X,Y MULT R2,W,U ADD Z,R1,R2 LOAD R1,X MULT R1,Y LOAD R2,W MULT R2,U ADD R1,R2 STORE Z,R1 LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD POP Z Convention: First operand is the destination (C-style!)

71 Which program runs faster? Z = X Y W U + three-address two-address one-address zero-address (stack) MULT R1,X,Y MULT R2,W,U ADD Z,R1,R2 71 LOAD R1,X MULT R1,Y LOAD R2,W MULT R2,U ADD R1,R2 STORE Z,R1 LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD POP Z

72 5.2.5 Expanding opcodes B/c each operand needs an address inside the instruction, instr. length is affected by the number of operands supported by the ISA. Real-life ISAs have instr. w/different nr. of operands, e.g. Operations that require no operands (HALT) Operations that require 1, 2, or 3 operands (LOAD,ADD) Conclusion: waste of space when fixed-length opcodes are used. One way to recover some of this space is to use expanding opcodes. 72

73 Expanding opcodes example A system has 16 registers and 4K of memory. We need: 4 bits for opcode 4 bits to access any of the registers 12 bits to access any memory address. We want to have 16-bit instructions three choices: 73

74 Expanding opcodes example If we allow the length of the opcode to vary, we can create a more flexible instruction set: Escape opcodes 74

75 Expanding opcodes Can we know in advance if a solution is possible? Example: Given 8-bit instructions, is it possible to allow the following to be encoded? 3 instructions with two 3-bit operands. 2 instructions with one 4-bit operand. 4 instructions with one 3-bit operand. We need: = 192 instr. for the 3-bit operands = 32 instr. for the 4-bit operands = 32 instr. for the 3-bit operands. Total: 256 instr. = 2 8 YES!

76 76 We then design the instr. format using expanding opcodes:

77 QUIZ: Problem 17.a If possible, design the instr. format by assigning the opcodes in sequential order. 77

78 QUIZ: Problem 15.a

79 5.3 Instruction types Instructions fall into several broad categories: 79 Data movement Arithmetic Boolean Bit manipulation I/O Control transfer Special purpose Can you think of examples for each of these? NOP Cache management Nibble/Byte conversion (e.g. BCD) Etc.

80 5.4 Addressing Addressing modes specify: where an operand is located: In the instruction itself (a constant) In a register In a memory location. what is the data type of that operand: Integers (short/long) FP (single/double/quad) Strings Boolean (True/False) Pointers (memory addresses) 80

81 5.4 Addressing The actual location of an operand is its effective address (EA). Determining where the operand is means determining its EA. 81

82 Addressing modes Inherent: the EA of the data is implicit Example: the Motorola 68HC12 MCU has the following instructions that use inherent addressing: PSHA INCA DECA 82

83 Addressing modes Immediate: the data is part of the instruction. Direct: the address of the data is given in the instruction. Register: the data is located in a register. Indirect: the address of the address of the data is in the instruction. Register indirect: a register stores the address of the data 83 continued

84 Addressing modes Base+offset Indexed addressing uses a register (implicitly or explicitly) as an offset, which is added to the address in the operand to determine the effective address of the data. Register holds the offset. Based addressing is similar except that a base register is used instead of an index register, i.e. the register holds the base instead of the offset. 84

85 Addressing modes Stack addressing: the operand is on top of the stack. There are many variations to these addressing modes including: Indirect-indexed. Self-relative (e.g. JUMP) Auto increment/decrement 85

86 86 Principal addressing modes

87 Addressing examples These are the values loaded into the accumulator for each addressing mode. 87

88 handout Which of the principal addressing modes are missing? Provide the extra information needed, and find the value loaded in AC for each of them! 88

89 To do for next time: Read sections 5.2.5, 5.3, 5.4 Understand all examples we covered in class today. Solve Examples 5.8, 5.9 in notebook Solve Exercise 17/309 in notebook (all 7 addressing modes!) 89 EOL 2

90 QUIZ: Problem 12.b Convert to postfix (reverse Polish ): W X + W (U V +Z) 90

91 QUIZ: Problem 13.b Use the stack-based algorithm to convert to infix and evaluate. Show the stack at each step:

92 92 QUIZ: Exercise 21

93 93 QUIZ: Exercise 21

94 5.5 Instruction Pipelining Today s CPUs divide the fetch-decode(-get)-execute cycle into even smaller steps. These smaller steps can often be executed in parallel to increase throughput. Such parallel execution is called instruction pipelining. Instruction pipelining provides for instruction level parallelism (ILP) 94

95 Instruction Pipelining Example Suppose a fetch-execute cycle is implemented by the following sequence of steps: S1. Fetch instruction. S4. Get operands. S2. Decode opcode. S5. Execute instruction. S3. Calculate EA (effective S6. Store result. addresses) of operands. 95

96 If each stage takes 10ns, calculate the time needed to execute these 4 instructions: Without pipelining With pipelining twithout pipelining What is the speedup? t with pipelining 96

97 If each stage takes 10ns, calculate the time needed to execute these 4 instructions: Without pipelining 6x4x10 ns = 240 ns With pipelining [6 + (4-1) ]x10 ns = 90 ns First instr. goes through the pipeline twithout pipelining speedup = (6x4)/(6+4-1) = t with pipelining Each cycle, one of the remaining instr. leaves the pipeline Note that the 10ns simplifies it all comes down to counting the cycles. 97

98 Pipelining speedup formula t p = time per stage. The first task (instruction) requires k t p time to complete in a k-stage pipeline. The remaining (n - 1) tasks emerge from the pipeline one per cycle. Time to complete the remaining tasks is (n - 1)t p. Total for n tasks with a k-stage pipeline: (k t p ) + (n - 1)t p = (k + n - 1)t p 98

99 Pipelining speedup formula t n is the time needed for a task in the non-pipelined CPU (ideally equal to kt p ) t n = kt p If n is large (n approaches infinity), then n/(k + n - 1) approaches 1, which results in a theoretical speedup: because k-1 is negligible compared to n

100 100 Exercise 24

101 101 Exercise 24

102 Limitations of Pipelining The previous speedup equations do not account for a number of real-life limitations, e.g.: Can one instruction fetch its opcode (from memory) while another instruction is getting data (from memory)? Harvard architecture? Separate instruction and data paths from memory (needs double-ported memory!) Operand cache? Instruction cache? The longer the pipeline, the more complex the hardware to control it, so we have kt p > t n (not equal) 102

103 Limitations of Pipelining We assumed that the pipeline can be kept filled at all times. Pipeline conflicts (hazards) arise that cause the pipeline to stall, or to be flushed: Resource (a.k.a. structural) conflicts (e.g. one intr. is storing a result to memory, while another is getting an operand from memory) Data dependencies (a.k.a. data conflicts) (e.g. instr. N+1 needs the result of instr. N as an operand) Control conflicts due to conditional branching (see next slide) 103

104 Conditional branching example for a 4-stage pipeline When the last stage of branch is completed, the address of the next instruction is ready in the PC 104 Pipeline is flushed, since I4, I5 and I6 are not going to be executed. Instead, I8, I9, and I10 start filling up the pipeline.

105 Conditional branching example for a 4-stage pipeline 105 There is a gap of 4 clock cycles, during which no instruction leaves the pipeline! This is called a stall or bubble.

106 Techniques used to mitigate branch conflicts: Branch prediction Taking both paths (needs additional hardware!) IA-64: predicate bits Delayed branch (compiler inserts out-of-order instructions) 106

107 Not in our text Static branch prediction Always take the branch or Always don t take it Source: U.Washington, CSEP548: Computer Architecture

108 Remember this program from Ch.4? It adds the 5 integers contained in the array Addr, and stores the result in Sum How many mispredictions will occur during the execution of this code from Ch.4?

109 Not in our text How many mispredictions will occur if the CPU Always take the branch Always doesn t take it Static branch prediction How many mispredictions will occur during the execution of this code from Ch.4?

110 Not in our text One-bit branch prediction The FSM starts in this state. Source: U.Washington, CSEP548: Computer Architecture

111 Not in our text One-bit branch prediction How many mispredictions? The FSM starts in this state. How many mispredictions will occur during the execution of this code from Ch.4?

112 Not in our text Two-bit branch prediction strong taken weak taken weak not taken strong not taken Source: U.Washington, CSEP548: Computer Architecture

113 Not in our text How many mispredictions? Two-bit branch prediction How many mispredictions will occur during the execution of this code from Ch.4?

114 In today s CPUs, executing typical programs, misprediction rate ranges between 1% to 18%. 114

115 To read more about branch prediction: Ch.6 of Computer Organization and Design: The Hardware/Software Interface, 4th ed. by Patterson and Hennessy. 115

116 Conclusions on the limitations of pipelining Problems (a.k.a. hazards): Resource conflicts Data conflicts Control conflicts (due to conditional branching) Measures can be taken at the software level as well as at the hardware level to reduce the effects of these hazards, but they cannot be totally eliminated. 116

117 Read and take notes FYI (not required for exam): 5.6 Real-World Examples of ISAs Intel MIPS JVM (stack-based ISA!) ARM The following slides are given just for reference 117

118 5.6 Real-World Examples of Pipelining in ISAs First pipelined computer: IBM 7030 (Stretch) Intel introduced pipelining to their processor line with its Pentium chip. The first Pentium had two 5-stage pipelines in the integer CPU and one 6-stage pipeline in the FPU. Each subsequent Pentium processor had a longer pipeline than its predecessor: The "Prescott" Pentium 4 cores had a 39-stage pipeline, the longest in mainstream consumer computing. [Source] 118

119 Real-World Examples of Pipelining The Itanium (IA-64) has a 10-stage pipeline. The Sandy Bridge/Ivy Bridge microarchitectures have 14-stage pipelines (16-19 according to this source). Xelerated X10 network processor (NPU) has a 200- stage pipeline! 119

120 Intel addressing modes Intel processors support a wide array of addressing modes. The original 8086 provided 17 ways to address memory, most of them variants on the methods presented in this chapter. Owing to their need for backward compatibility, the Pentium chips also support these 17 addressing modes. The Itanium (64 bit!), having a RISC core, supports only one: register indirect addressing (with optional post increment). 120

121 5.6.2 MIPS MIPS was initially an acronym for Microprocessor Without Interlocked Pipeline Stages. The architecture is RISC, little endian and wordaddressable. Like Intel, the pipeline size of the MIPS processors has grown: The R2000 and R3000 have five-stage pipelines.; the R4000 and R4400 have 8-stage pipelines. 121

122 Not in our text The MIPS ISA has fixed-length instructions, with up to 3 addresses. Source:

123 MIPS The R10000 has three pipelines: A 5-stage pipeline for integer instructions, a 7-stage for floating-point instructions, and a 6-stage for LOAD/STORE instructions. In all MIPS ISAs, only the LOAD and STORE instructions can access memory. The ISA itself uses only base addressing mode, but the assembler has macro-instructions to accommodate immediate, register, direct, indirect register, base, or indexed addressing modes. 123

124 5.6.3 JVM ISA The Java programming language is an interpreted language that runs in a software machine called the Java Virtual Machine (JVM). A JVM is written in a native language for a wide array of processors, including MIPS and Intel. Like a real machine, the JVM has an ISA all of its own, called bytecode. This ISA was designed to be compatible with the architecture of any machine on which the JVM is running. 124

125 JVM ISA

126 5.6.3 JVM ISA Java bytecode is a stack-based language. Most instructions are zero address instructions. The JVM has four registers that provide access to five regions of main memory. All references to memory are offsets from these registers. Java uses no pointers or absolute memory references. Java was designed for platform interoperability, not performance! 126

127 5.6.4 ARM You may not have heard of ARM but most likely use an ARM processor every day. It is the most widely used 32-bit instruction architecture: 95%+ of smartphones, 80%+ of digital cameras 40%+ of all digital television sets Founded in 1990, by Apple and others, ARM (Advanced RISC Machine) is now a British firm, ARM Holdings. ARM Holdings does not manufacture these processors; it sells licenses to manufacturers. 127

128 ARM ARM is a load/store architecture : all data processing must be performed on values in registers, not in memory. It uses fixed-length, three-operand instructions and simple addressing modes ARM processors have a minimum of a three-stage pipeline (consisting of fetch, decode, and execute); Newer ARM processors have deeper pipelines (more stages). Some ARM8 implementations have 13-stage integer pipelines. 128

129 ARM ARM has 37 total registers but their visibility depends on the processor mode. ARM allows multiple register transfers. It can simultaneously load or store any subset of the16 general-purpose registers from/to sequential memory addresses. Control flow instructions include unconditional and conditional branching and procedure calls Most ARM instructions execute in a single cycle, provided there are no pipeline hazards or memory accesses. 129

130 Homework for Chapter 5 Due Thu, Nov. 17 2, 4, 10, 11, 14, 16, 17, 22,

131 Chapter 5 Conclusion ISAs are distinguished according to their bits per instruction, number of operands per instruction, operand location and types and sizes of operands. Endianness as another major architectural consideration. CPU can store store data based on 1. A stack architecture 2. An accumulator architecture 3. A general purpose register architecture. 131

132 Chapter 5 Conclusion Instructions can be fixed length or variable length. To enrich the instruction set for a fixed length instruction set, expanding opcodes can be used. The addressing mode of an ISA is also another important factor. We looked at: Immediate Direct Register Register Indirect Indirect Indexed Based Stack 132

133 Chapter 5 Conclusion A k-stage pipeline can theoretically produce execution speedup of k as compared to a nonpipelined machine. Pipeline hazards such as resource conflicts and conditional branching prevents this speedup from being achieved in practice. The Intel, MIPS, and JVM architectures provide good examples of the concepts presented in this chapter. 133