Grading: 3 pts each part. If answer is correct but uses more instructions, 1 pt off. Wrong answer 3pts off.
|
|
- Clement Neal
- 6 years ago
- Views:
Transcription
1 Department of Electrical and Computer Engineering University of Wisconsin Madison ECE 552 Introductions to Computer Architecture Homework #2 (Suggested Solution) 1. (10 points) MIPS and C program translations Translate the following C statements into MIPS assembly code, using a minimum number of MIPS assembly instructions. (a) (4 points) Assume that the variables a, b, c and d are assigned to registers $s0, $s1, $s2, and $s4 respectively. i) a = b a ii) c = d + ( c 5) i) add $s0, $s0, $s1 # a = a + b sub $s0, $0, $s0 # a = 0 (a + b) ii) addi $2, $s2, 5 # c = c + 5 sub $s2, $s3, $s2 # c = d (c+5), Grading: Each part 2 pts. If answer is correct but need more than 2 instr., 1 pt off. If answer is wrong, 2 pts off. In the last line, $s4 instead of $s3 will also receive full mark. (b) (6 points) Assume the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4 respectively, and the base address of the arrays A and B are in registers $s6, and $s7 respectively. i) f = g A[4]; ii) B[8] = A[i j]; (assume i j is in the range of indices of array A) (i) lw $s0, 16($s6) # load A[4] to $s0 add $s0, $s0, $s1 # add g to A[4] sub $s0, $0, $s0 # 0 (g + A[4]) (ii) sub $t0, $s3, $s4 # t0 = i j sll $t0, $t0, 2 add $t0, $t0, $s6 # t0 = addr of A[i-j] lw $t1, 0($t0) # t1 = A[i-j] sw $t1, 32($s7) # B[8] = A[i-j] Grading: 3 pts each part. If answer is correct but uses more instructions, 1 pt off. Wrong answer 3pts off. 2. (10 points) MIPS Assembly code to C code conversion Assume that initially variables a, b, c, d, and e are assigned to registers $s0, $s1, $s2, $s3, and $s4 respectively. The values of a, b, c, d, and e are all multiples of 4 (can be divided evenly by 4) and greater than 0. Assume that the base addresses of arrays P and Q are in registers $s6 and $s7 respectively. 1
2 (a) (4 points) For the MIPS assembly instructions below, what are the corresponding C statements. Sll $s2, $s4, 1 Add $s0, $s2, $s3 Add $s0, $s0, $s1 The corresponding C statement is a = b + d + 2*e. Sll $s2, $s4, 1 # c = 2*e Add $s0, $s2, $s3 # a = c + d = 2e + d Add $s0, $s0, $s1 # a = a + b = b + d + 2e Grading: each mistake 1 pt off until all 4 pts are taken. If only the answer is given and the answer is wrong, all 4 pts are off. Answer alone but correct gets full marks. (b) (6 points) For the MIPS assembly instructions below, what is the corresponding C statement? Assume part (b) is independent of part (a) add $t0, $s6, $s0 add $t1, $s7, $s1 lw $s0, 0($t0) addi $t2, $t0, 4 lw $t0, 0($t2) add $t0, $t0, $s0 sw $t0, 0($t1) Q[b/4] = P[a/4] + P[a/4 + 1]. add $t0, $s6, $s0 # Base addr of P + a/4 add $t1, $s7, $s1 # Base addr of Q + b/4 lw $s0, 0($t0) # a = P[a/4] addi $t2, $t0, 4 # Base addr of P + a/4 + 4/4 lw $t0, 0($t2) # t0 = P[a/4 + 1] add $t0, $t0, $s0 # t0 = P[a/4] + P[a/4+1] sw $t0, 0($t1) # save t0 to Q[b/4] Grading: the divided by 4 (/4) in the indices is very important. If the index expression is wrong, the all answer is considered wrong and all 6 pts are off. 3. (15 points) Assume that an array is stored in a memory of a MIPS processor as follows: Addr Data (a) (5 points, CC) Write a C code to sort the data from lowest to highest, placing the lowest value in the smallest memory location shown in the table above. Assume the data shown represents the C variable called A r r a y which is an array type int, and that the first number in the array shown is the first element in the array. Assume the memory is byte addressable, and each word consists of 4 bytes. temp = Array[0]; % temp = 4 temp2 = Array[1]; % temp2 = 5 Array[0] = Array[4]; % M[20] = 1 Array[1] = Array[3]; % M[24] = 2 Array[3] = temp; % M[32] = 4 2
3 Array[4] = temp2; % M[36] = 5 Grading: there may be other valid solutions. If answer is reasonable, full mark will be given. (b) (5 points, CC) For the memory address list in the table above, write a MIPS code to sort the data from lowest to highest, placing the lowest value in the smallest memory location. Use a minimum number of MIPS instructions. Assume the base address of C variable A r r a y is stored in register $s6. lw $t0, 0($s6) # t0 Array[0] = M[20] = 4 lw $t1, 4($s6) # t1 Array[1] = M[24] = 5 lw $t2, 16($s6) # t2 Array[4] = M[36] = 1 sw $t2, 0($s6) # M[20] = Array[0] t2 = 1 lw $t2, 12($s6) # t2 M[32] = Array[3] = 2 sw $t2, 4($s6) # M[24] = Array[1] [t2] = 2 sw $t0, 12($s6) # M[32] = Array[3] [t0] = 4 sw $t1, 16($s6) # M[36] = Array[4] [t1] = 5 Grading: completion credits. If answer is reasonable, full mark will be given. (c) (5 points) Consider the hexadecimal number 0 ABCDEF12. i) Translate this number into decimal and ii) show how the data would be arranged in memory starting from address 0 in a little-endian machine and a big-endian machine. i) the corresponding decimal number is and (ii) the memory map is as follows: Addr Data (little endian) 12 EF CD AB Data (big endian) AB CD EF 12 Grading: (i) 2 pts, answers only. (ii) 1.5 pt each. All parts must be correct. Answers only. Address is 0, 8, 16, 24 if it is assumed bits. 0, 1, 2, 3 are the actual address in a byte addressable memory. Both will be given credits. 4. (20 points) MIPS Instructions Sets (a) (12 points) Translate the assembly program into Hexadecimal machine code. Then represent the binary representation in corresponding R, I, or J format according to the respective field partitions: R: Opcode rs rt rd Shamt funct I: Opcode rs rt immediate J: Opcode address If a field in the instruction is unused, it s value is assumed to be 0. Unless specified, numbers are in decimal number representation 3
4 Assembly instruction j ten nor $t2, $s2, $s3 sw $t2, 4($s0) j ten Opcode Address 0x08030D nor $t2, $s2, $s3 Opcode rs rt rd Shamt Funct 0x sw $t8, 28($s7) Opcode rs rt Immediate 0xAEF8FFF Grading: 4 pts each. For each instr. each mistake costs 1 pt. until all 4 pts off. (b) (8 points) Assume at clock cycle t, the content of PC = 0xD The content of the program memory pointed by PC is MEM[PC] = 0x080009C4. In a single cycle MIPS Datapath, what is the content of PC in Hex format at clock cycle t + 1? 0x080009C4 = Opcode = 2 H jump instruction. The remaining 26 bits are offset = Next, PC+4{31:28} = 0xD {31:28} = 0xD. Thus the new PC content is {PC+4{31:28}, offset, 2b 00} = 0xD (20 points) Grading: jump instruction 3 pts, jump address 5 pts. (a) (5 points) Write a (shortest) sequence of regular MIPS instructions to realize a new pseudo-instruction push $s0. This instruction will save the content of $s0 into the stack. addi $sp, $sp, 4 sw $sp, $s0 Grading: if the answer is correct but has more than 2 instr., deduct 1 pt for each extra instr until all 5 pts are off. If the answer is wrong, all 5 pts are off. (b) (5 points) Suppose the contents of registers $s0 and $s1 are: [$s0] = 0xFFFFFFFF, and [$s1] = 0x What are values in registers $t0 and $t1 after these two instructions: slt $t0, $s0, $s1 # signed comparison sltu $t1, $s0, $s1 # unsigned comparison For signed comparison, [$s0] = 1 < [$s1] = +1. Since 1 < 1, $t0 = 1. For unsigned comparison, [$s0] = > [$s1] = +1. Thus $t1 = 0. Grading: $t0: 2 pts, $t1: 3 pts 4
5 (c) (5 points) Assume that initially [$t0] = 0x What is the value of $t0 after execution of the following two MIPS assembly instructions? ori $t0, $t0, 0x0002 lui $t0, 0xAB10 [$t0] = 0xAB Note that the lui instruction automatically filled 0x0000 to the lower 16 bits of the target register, wiping out the 0x0002 value in [$t0] after the ori instruction. Grading: Answer only. (d) (5 points) if the current content of PC is 0x (hex), what is the highest PC value a single MIPS jump instruction may realize (give the answer in hex format)? The jump address is first 4 bits of PC concatenated with 26 bits from the instruction and followed by two 0s since it is a word boundary. Thus, the highest PC address a single MIPS jump instruction may jump to will be 0x x0FFFFFFC = 0x0FFFFFFC. Grading: Answers only. 6. (10 points) consider the following MIPS assembly code and answer the following questions. LOOP: addi $s2, $s2, 2 Subi $t1, $t1, 1 bne $t1, $0, LOOP (a) (5 points) Assume the contents of registers $t1, and $s2 are 10 and 0 initially prior to the execution of above loop. What is the value $s2 after completion of the loop? The loop will be executed 10 times. During each iteration of the loop, $s2 will be incremented by 2. Hence the end value of $s2 is 20. Grading: executing loop 10 times (2 pts). End value of $s2: 3 pts (b) (5 points) Assume the integers I, and A respectively are assigned with registers $t2 and $s2, and that I = 10 and A = 0. Write a C code routine corresponding to above MIPS assembly code. do { A += 2; I = I 1; } while (I > 0) Grading: receive full mark if correct. 7. (15 points) Let the latencies of each major block for the logic blocks shown in Fig in the textbook be as follows: I-Mem Add Mux ALU Regs D-Mem Sign-Extend Shift-Left ps 70 ps 20 ps 90 ps 90 ps 250 ps 15 ps 10 ps While answering the following parts, briefly explain the way the answers are derived. (a) (5 points) What is the clock cycle time if the only types of instructions that need to be supported are ALU instructions (ADD, AND, etc)? 5
6 The longest-latency path for ALU operations is through I-Mem, Regs, Mux (to select ALU operand), ALU, and Mux (to select value for register write). Note that the only other path of interest is the PC-increment path through Add (PC + 4) and Mux, which is much shorter. So for the I-Mem, Regs, Mux, ALU, Mux path we have: 200ps + 90ps + 20ps + 90ps + 20ps = 420ps. Grading: Answer only. (b) (5 points) What is the clock cycle time if the only instruction needed to be supported is the load word (LW) instruction? The longest-latency path for LW is through I-Mem, Regs, Mux (to select ALU input), ALU, D-Dem, and Mux (to select what is written to register). The only other interesting paths are the PC-increment path (which is much shorter) and the path through Sign-extend unit in address computation instead of through Registers. However, Regs has a longer latency than Sign-extend, so for I-Mem, Regs, ALU, D-Mem, and Mux path we have: 200ps + 90ps + 90ps + 250ps + 20ps = 650ps. Grading: Answer only. For part (b) if answer is 670ps, full mark will also be given. (c) (5 points) What is the clock cycle time if the instructions needed to be supported are ADD, BEQ, LW, and SW instructions? The answer is 650ps which is the same as in part (b) because the LW instruction has the longest critical path. The longest path for SW is shorter by one Mux latency (no write to register), and the longest path for ADD or BNE is shorter by one D-Mem latency. Grading: Answer only. 6
Chapter 2A Instructions: Language of the Computer
Chapter 2A Instructions: Language of the Computer Copyright 2009 Elsevier, Inc. All rights reserved. Instruction Set The repertoire of instructions of a computer Different computers have different instruction
More informationUnsigned Binary Integers
Unsigned Binary Integers Given an n-bit number x x n 1 n 2 1 0 n 12 xn 22 x12 x02 Range: 0 to +2 n 1 Example 2.4 Signed and Unsigned Numbers 0000 0000 0000 0000 0000 0000 0000 1011 2 = 0 + + 1 2 3 + 0
More informationUnsigned Binary Integers
Unsigned Binary Integers Given an n-bit number x x n 1 n 2 1 0 n 12 xn 22 x12 x02 Range: 0 to +2 n 1 Example 2.4 Signed and Unsigned Numbers 0000 0000 0000 0000 0000 0000 0000 1011 2 = 0 + + 1 2 3 + 0
More informationCS3350B Computer Architecture MIPS Instruction Representation
CS3350B Computer Architecture MIPS Instruction Representation Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada
More informationLecture 4: MIPS Instruction Set
Lecture 4: MIPS Instruction Set No class on Tuesday Today s topic: MIPS instructions Code examples 1 Instruction Set Understanding the language of the hardware is key to understanding the hardware/software
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA
CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationComputer Architecture
CS3350B Computer Architecture Winter 2015 Lecture 4.2: MIPS ISA -- Instruction Representation Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted from lectures on Computer Organization and Design,
More informationCENG3420 Lecture 03 Review
CENG3420 Lecture 03 Review Bei Yu byu@cse.cuhk.edu.hk 2017 Spring 1 / 38 CISC vs. RISC Complex Instruction Set Computer (CISC) Lots of instructions of variable size, very memory optimal, typically less
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization
CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationInstructions: MIPS ISA. Chapter 2 Instructions: Language of the Computer 1
Instructions: MIPS ISA Chapter 2 Instructions: Language of the Computer 1 PH Chapter 2 Pt A Instructions: MIPS ISA Based on Text: Patterson Henessey Publisher: Morgan Kaufmann Edited by Y.K. Malaiya for
More informationLecture 5: Procedure Calls
Lecture 5: Procedure Calls Today s topics: Memory layout, numbers, control instructions Procedure calls 1 Memory Organization The space allocated on stack by a procedure is termed the activation record
More informationComputer Organization MIPS ISA
CPE 335 Computer Organization MIPS ISA Dr. Iyad Jafar Adapted from Dr. Gheith Abandah Slides http://www.abandah.com/gheith/courses/cpe335_s08/index.html CPE 232 MIPS ISA 1 (vonneumann) Processor Organization
More informationRui Wang, Assistant professor Dept. of Information and Communication Tongji University.
Instructions: ti Language of the Computer Rui Wang, Assistant professor Dept. of Information and Communication Tongji University it Email: ruiwang@tongji.edu.cn Computer Hierarchy Levels Language understood
More informationECE232: Hardware Organization and Design
ECE232: Hardware Organization and Design Lecture 14: One Cycle MIPs Datapath Adapted from Computer Organization and Design, Patterson & Hennessy, UCB R-Format Instructions Read two register operands Perform
More informationCSE 378 Midterm 2/12/10 Sample Solution
Question 1. (6 points) (a) Rewrite the instruction sub $v0,$t8,$a2 using absolute register numbers instead of symbolic names (i.e., if the instruction contained $at, you would rewrite that as $1.) sub
More informationCSEN 601: Computer System Architecture Summer 2014
CSEN 601: Computer System Architecture Summer 2014 Practice Assignment 5 Solutions Exercise 5-1: (Midterm Spring 2013) a. What are the values of the control signals (except ALUOp) for each of the following
More informationCSCI 402: Computer Architectures
CSCI 402: Computer Architectures Instructions: Language of the Computer (2) Fengguang Song Department of Computer & Information Science IUPUI Memory Operands Two tribes: Big Endian: Most-significant byte
More informationCOMPUTER ORGANIZATION AND DESIGN. The Hardware/Software Interface. Chapter 4. The Processor: A Based on P&H
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface Chapter 4 The Processor: A Based on P&H Introduction We will examine two MIPS implementations A simplified version A more realistic pipelined
More informationIntroduction to the MIPS. Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University
Introduction to the MIPS Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University Introduction to the MIPS The Microprocessor without Interlocked Pipeline Stages
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware 4.1 Introduction We will examine two MIPS implementations
More informationInstructions: Language of the Computer
CS359: Computer Architecture Instructions: Language of the Computer Yanyan Shen Department of Computer Science and Engineering 1 The Language a Computer Understands Word a computer understands: instruction
More informationCS31001 COMPUTER ORGANIZATION AND ARCHITECTURE. Debdeep Mukhopadhyay, CSE, IIT Kharagpur. Instructions and Addressing
CS31001 COMPUTER ORGANIZATION AND ARCHITECTURE Debdeep Mukhopadhyay, CSE, IIT Kharagpur Instructions and Addressing 1 ISA vs. Microarchitecture An ISA or Instruction Set Architecture describes the aspects
More informationCOMPSCI 313 S Computer Organization. 7 MIPS Instruction Set
COMPSCI 313 S2 2018 Computer Organization 7 MIPS Instruction Set Agenda & Reading MIPS instruction set MIPS I-format instructions MIPS R-format instructions 2 7.1 MIPS Instruction Set MIPS Instruction
More informationLecture 9: Disassembly
Lecture 9: Disassembly CSE 30: Computer Organization and Systems Programming Winter 2010 Rajesh Gupta / Ryan Kastner Dept. of Computer Science and Engineering University of California, San Diego Instruction
More informationCS 351 Exam 2 Mon. 11/2/2015
CS 351 Exam 2 Mon. 11/2/2015 Name: Rules and Hints The MIPS cheat sheet and datapath diagram are attached at the end of this exam for your reference. You may use one handwritten 8.5 11 cheat sheet (front
More informationThe Processor: Datapath and Control. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University
The Processor: Datapath and Control Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Introduction CPU performance factors Instruction count Determined
More informationMath 230 Assembly Programming (AKA Computer Organization) Spring 2008
Math 230 Assembly Programming (AKA Computer Organization) Spring 2008 MIPS Intro II Lect 10 Feb 15, 2008 Adapted from slides developed for: Mary J. Irwin PSU CSE331 Dave Patterson s UCB CS152 M230 L10.1
More informationChapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont )
Chapter 2 Computer Abstractions and Technology Lesson 4: MIPS (cont ) Logical Operations Instructions for bitwise manipulation Operation C Java MIPS Shift left >>> srl Bitwise
More informationMIPS Coding Continued
MIPS Coding Continued Exercise 1 Suppose we have three arrays, A, B, C, all of size 10. Now we want to set C[i] = min(a[i], B[i]) for all 0
More informationProcessor (I) - datapath & control. Hwansoo Han
Processor (I) - datapath & control Hwansoo Han Introduction CPU performance factors Instruction count - Determined by ISA and compiler CPI and Cycle time - Determined by CPU hardware We will examine two
More informationECE232: Hardware Organization and Design. Computer Organization - Previously covered
ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization
More informationMIPS R-format Instructions. Representing Instructions. Hexadecimal. R-format Example. MIPS I-format Example. MIPS I-format Instructions
Representing Instructions Instructions are encoded in binary Called machine code MIPS instructions Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register
More informationMIPS Assembly: More about Memory and Instructions CS 64: Computer Organization and Design Logic Lecture #7
MIPS Assembly: More about Memory and Instructions CS 64: Computer Organization and Design Logic Lecture #7 Ziad Matni Dept. of Computer Science, UCSB Lecture Outline Global variables and memory Arrays
More informationThe Processor (1) Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University
The Processor (1) Jinkyu Jeong (jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu)
More informationChapter 2. Instructions: Language of the Computer. HW#1: 1.3 all, 1.4 all, 1.6.1, , , , , and Due date: one week.
Chapter 2 Instructions: Language of the Computer HW#1: 1.3 all, 1.4 all, 1.6.1, 1.14.4, 1.14.5, 1.14.6, 1.15.1, and 1.15.4 Due date: one week. Practice: 1.5 all, 1.6 all, 1.10 all, 1.11 all, 1.14 all,
More informationComputer Science and Engineering 331. Midterm Examination #1. Fall Name: Solutions S.S.#:
Computer Science and Engineering 331 Midterm Examination #1 Fall 2000 Name: Solutions S.S.#: 1 41 2 13 3 18 4 28 Total 100 Instructions: This exam contains 4 questions. It is closed book and notes. Calculators
More informationELEC / Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2)
ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2) Victor P. Nelson, Professor & Asst. Chair Vishwani D. Agrawal, James J. Danaher Professor Department
More informationCS 61C: Great Ideas in Computer Architecture. MIPS Instruction Formats
CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats Instructor: Justin Hsia 6/27/2012 Summer 2012 Lecture #7 1 Review of Last Lecture New registers: $a0-$a3, $v0-$v1, $ra, $sp Also: $at,
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle
More informationECE232: Hardware Organization and Design
ECE232: Hardware Organization and Design Lecture 4: Logic Operations and Introduction to Conditionals Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Overview Previously examined
More informationECE/CS 552: Introduction to Computer Architecture ASSIGNMENT #1 Due Date: At the beginning of lecture, September 22 nd, 2010
ECE/CS 552: Introduction to Computer Architecture ASSIGNMENT #1 Due Date: At the beginning of lecture, September 22 nd, 2010 This homework is to be done individually. Total 9 Questions, 100 points 1. (8
More informationMIPS%Assembly% E155%
MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage $0 0 the constant value 0 $at 1 assembler temporary
More informationComputer Organization and Structure. Bing-Yu Chen National Taiwan University
Computer Organization and Structure Bing-Yu Chen National Taiwan University Instructions: Language of the Computer Operations and Operands of the Computer Hardware Signed and Unsigned Numbers Representing
More informationUniversity of California at Santa Barbara. ECE 154A Introduction to Computer Architecture. Quiz #1. October 30 th, Name (Last, First)
University of California at Santa Barbara ECE 154A Introduction to Computer Architecture Quiz #1 October 30 th, 2012 Name (Last, First) All grades will be posted on the website as a single spreadsheet
More informationLevels of Programming. Registers
Levels of Programming COSC 2021: Computer Organization Instructor: Dr. Amir Asif Department of Computer Science York University Handout # 3: MIPS Instruction Set I Topics: 1. Arithmetic Instructions 2.
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2009 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:
More informationThe Processor. Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut. CSE3666: Introduction to Computer Architecture
The Processor Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut CSE3666: Introduction to Computer Architecture Introduction CPU performance factors Instruction count
More information101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009
101 Assembly ENGR 3410 Computer Architecture Mark L. Chang Fall 2009 What is assembly? 79 Why are we learning assembly now? 80 Assembly Language Readings: Chapter 2 (2.1-2.6, 2.8, 2.9, 2.13, 2.15), Appendix
More informationChapter 4. The Processor Designing the datapath
Chapter 4 The Processor Designing the datapath Introduction CPU performance determined by Instruction Count Clock Cycles per Instruction (CPI) and Cycle time Determined by Instruction Set Architecure (ISA)
More informationReview of Last Lecture. CS 61C: Great Ideas in Computer Architecture. MIPS Instruction Representation II. Agenda. Dealing With Large Immediates
CS 61C: Great Ideas in Computer Architecture MIPS Instruction Representation II Guest Lecturer: Justin Hsia 2/11/2013 Spring 2013 Lecture #9 1 Review of Last Lecture Simplifying MIPS: Define instructions
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition The Processor - Introduction
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
More informationMips Code Examples Peter Rounce
Mips Code Examples Peter Rounce P.Rounce@cs.ucl.ac.uk Some C Examples Assignment : int j = 10 ; // space must be allocated to variable j Possibility 1: j is stored in a register, i.e. register $2 then
More informationChapter 4. Instruction Execution. Introduction. CPU Overview. Multiplexers. Chapter 4 The Processor 1. The Processor.
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor The Processor - Introduction
More informationCS 4200/5200 Computer Architecture I
CS 4200/5200 Computer Architecture I MIPS Instruction Set Architecture Dr. Xiaobo Zhou Department of Computer Science CS420/520 Lec3.1 UC. Colorado Springs Adapted from UCB97 & UCB03 Review: Organizational
More informationChapter 4. The Processor. Instruction count Determined by ISA and compiler. We will examine two MIPS implementations
Chapter 4 The Processor Part I Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations
More informationCS222: MIPS Instruction Set
CS222: MIPS Instruction Set Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati 1 Outline Previous Introduction to MIPS Instruction Set MIPS Arithmetic's Register Vs Memory, Registers
More informationComputer Organization and Structure
Computer Organization and Structure 1. Assuming the following repeating pattern (e.g., in a loop) of branch outcomes: Branch outcomes a. T, T, NT, T b. T, T, T, NT, NT Homework #4 Due: 2014/12/9 a. What
More informationCSCI 402: Computer Architectures. Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI.
CSCI 402: Computer Architectures Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI Recall Big endian, little endian Memory alignment Unsigned
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
More informationEEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture
EEM 486: Computer Architecture Lecture 2 MIPS Instruction Set Architecture EEM 486 Overview Instruction Representation Big idea: stored program consequences of stored program Instructions as numbers Instruction
More informationECE 473 Computer Architecture and Organization Project: Design of a Five Stage Pipelined MIPS-like Processor Project Team TWO Objectives
ECE 473 Computer Architecture and Organization Project: Design of a Five Stage Pipelined MIPS-like Processor Due: December 8, 2011 Instructor: Dr. Yifeng Zhu Project Team This is a team project. All teams
More informationAssembly Language Programming. CPSC 252 Computer Organization Ellen Walker, Hiram College
Assembly Language Programming CPSC 252 Computer Organization Ellen Walker, Hiram College Instruction Set Design Complex and powerful enough to enable any computation Simplicity of equipment MIPS Microprocessor
More informationReduced Instruction Set Computer (RISC)
Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the ISA. RISC Goals RISC: Simplify ISA Simplify CPU Design Better CPU Performance Motivated by simplifying
More informationCENG3420 L03: Instruction Set Architecture
CENG3420 L03: Instruction Set Architecture Bei Yu byu@cse.cuhk.edu.hk (Latest update: January 31, 2018) Spring 2018 1 / 49 Overview Introduction Arithmetic & Logical Instructions Data Transfer Instructions
More informationChapter 2. Instructions: Language of the Computer. Adapted by Paulo Lopes
Chapter 2 Instructions: Language of the Computer Adapted by Paulo Lopes Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects
More informationComputer Science 61C Spring Friedland and Weaver. Instruction Encoding
Instruction Encoding 1 Instruction Formats I-format: used for instructions with immediates, lw and sw (since offset counts as an immediate), and branches (beq and bne) since branches are "relative" to
More informationChapter 4. The Processor. Computer Architecture and IC Design Lab
Chapter 4 The Processor Introduction CPU performance factors CPI Clock Cycle Time Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS
More informationCS 2506 Computer Organization II
Instructions: Print your name in the space provided below. This examination is closed book and closed notes, aside from the permitted one-page formula sheet. No calculators or other computing devices may
More informationChapter 1. Computer Abstractions and Technology. Lesson 3: Understanding Performance
Chapter 1 Computer Abstractions and Technology Lesson 3: Understanding Performance Manufacturing ICs 1.7 Real Stuff: The AMD Opteron X4 Yield: proportion of working dies per wafer Chapter 1 Computer Abstractions
More informationReduced Instruction Set Computer (RISC)
Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the machine. Reduced number of cycles needed per instruction.
More informationBranch Addressing. Jump Addressing. Target Addressing Example. The University of Adelaide, School of Computer Science 28 September 2015
Branch Addressing Branch instructions specify Opcode, two registers, target address Most branch targets are near branch Forward or backward op rs rt constant or address 6 bits 5 bits 5 bits 16 bits PC-relative
More informationECE 30 Introduction to Computer Engineering
ECE 30 Introduction to Computer Engineering Study Problems, Set #3 Spring 2015 Use the MIPS assembly instructions listed below to solve the following problems. arithmetic add add sub subtract addi add
More informationCS 61c: Great Ideas in Computer Architecture
MIPS Instruction Formats July 2, 2014 Review New registers: $a0-$a3, $v0-$v1, $ra, $sp New instructions: slt, la, li, jal, jr Saved registers: $s0-$s7, $sp, $ra Volatile registers: $t0-$t9, $v0-$v1, $a0-$a3
More informationPatterson PII. Solutions
Patterson-1610874 978-0-12-407726-3 PII 2 Solutions Chapter 2 Solutions S-3 2.1 addi f, h, -5 (note, no subi) add f, f, g 2.2 f = g + h + i 2.3 sub $t0, $s3, $s4 add $t0, $s6, $t0 lw $t1, 16($t0) sw $t1,
More informationLecture 10: Simple Data Path
Lecture 10: Simple Data Path Course so far Performance comparisons Amdahl s law ISA function & principles What do bits mean? Computer math Today Take QUIZ 6 over P&H.1-, before 11:59pm today How do computers
More informationMIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support
Components of an ISA EE 357 Unit 11 MIPS ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible
More informationA Processor. Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3
A Processor Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 2.16-20, 4.1-3 Let s build a MIPS CPU but using Harvard architecture Basic Computer System Registers ALU
More informationProcessor design - MIPS
EASY Processor design - MIPS Q.1 What happens when a register is loaded? 1. The bits of the register are set to all ones. 2. The bit pattern in the register is copied to a location in memory. 3. A bit
More informationLecture Topics. Announcements. Today: Single-Cycle Processors (P&H ) Next: continued. Milestone #3 (due 2/9) Milestone #4 (due 2/23)
Lecture Topics Today: Single-Cycle Processors (P&H 4.1-4.4) Next: continued 1 Announcements Milestone #3 (due 2/9) Milestone #4 (due 2/23) Exam #1 (Wednesday, 2/15) 2 1 Exam #1 Wednesday, 2/15 (3:00-4:20
More informationProcessor. Han Wang CS3410, Spring 2012 Computer Science Cornell University. See P&H Chapter , 4.1 4
Processor Han Wang CS3410, Spring 2012 Computer Science Cornell University See P&H Chapter 2.16 20, 4.1 4 Announcements Project 1 Available Design Document due in one week. Final Design due in three weeks.
More informationECE260: Fundamentals of Computer Engineering
MIPS Instruction Set James Moscola Dept. of Engineering & Computer Science York College of Pennsylvania Based on Computer Organization and Design, 5th Edition by Patterson & Hennessy MIPS Registers MIPS
More informationCS61C - Machine Structures. Lecture 6 - Instruction Representation. September 15, 2000 David Patterson.
CS61C - Machine Structures Lecture 6 - Instruction Representation September 15, 2000 David Patterson http://www-inst.eecs.berkeley.edu/~cs61c/ 1 Review Instructions: add, addi, sub, lw, sw beq, bne, j
More informationCS61C Machine Structures. Lecture 13 - MIPS Instruction Representation I. 9/26/2007 John Wawrzynek. www-inst.eecs.berkeley.
CS61C Machine Structures Lecture 13 - MIPS Instruction Representation I 9/26/2007 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS 61C L13 MIPS Instruction Representation
More informationCS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats
CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats Instructors: Vladimir Stojanovic and Nicholas Weaver http://inst.eecs.berkeley.edu/~cs61c/sp16 1 Machine Interpretation Levels of Representation/Interpretation
More informationComputer Organization MIPS Architecture. Department of Computer Science Missouri University of Science & Technology
Computer Organization MIPS Architecture Department of Computer Science Missouri University of Science & Technology hurson@mst.edu Computer Organization Note, this unit will be covered in three lectures.
More informationECE331: Hardware Organization and Design
ECE331: Hardware Organization and Design Lecture 15: Midterm 1 Review Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Basics Midterm to cover Book Sections (inclusive) 1.1 1.5
More informationThe MIPS Instruction Set Architecture
The MIPS Set Architecture CPS 14 Lecture 5 Today s Lecture Admin HW #1 is due HW #2 assigned Outline Review A specific ISA, we ll use it throughout semester, very similar to the NiosII ISA (we will use
More informationLECTURE 5. Single-Cycle Datapath and Control
LECTURE 5 Single-Cycle Datapath and Control PROCESSORS In lecture 1, we reminded ourselves that the datapath and control are the two components that come together to be collectively known as the processor.
More informationThe MIPS Processor Datapath
The MIPS Processor Datapath Module Outline MIPS datapath implementation Register File, Instruction memory, Data memory Instruction interpretation and execution. Combinational control Assignment: Datapath
More informationLecture 2. Instructions: Language of the Computer (Chapter 2 of the textbook)
Lecture 2 Instructions: Language of the Computer (Chapter 2 of the textbook) Instructions: tell computers what to do Chapter 2 Instructions: Language of the Computer 2 Introduction Chapter 2.1 Chapter
More informationCS 2504 Intro Computer Organization Test 1
Instructions: Print your name in the space provided below. This examination is closed book and closed notes, aside from the permitted one-page formula sheet and the MIPS reference card. No calculators
More informationTopic Notes: MIPS Instruction Set Architecture
Computer Science 220 Assembly Language & Comp. Architecture Siena College Fall 2011 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture.
More information--------------------------------------------------------------------------------------------------------------------- 1. Objectives: Using the Logisim simulator Designing and testing a Pipelined 16-bit
More informationComputer Organization and Structure. Bing-Yu Chen National Taiwan University
Computer Organization and Structure Bing-Yu Chen National Taiwan University Instructions: Language of the Computer Operations and Operands of the Computer Hardware Signed and Unsigned Numbers Representing
More informationMachine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine
Machine Language Instructions Introduction Instructions Words of a language understood by machine Instruction set Vocabulary of the machine Current goal: to relate a high level language to instruction
More informationInstruction Set Architectures Part I: From C to MIPS. Readings:
Instruction Set Architectures Part I: From C to MIPS Readings: 2.1-2.14 1 Goals for this Class Understand how CPUs run programs How do we express the computation the CPU? How does the CPU execute it? How
More informationMIPS Datapath. MIPS Registers (and the conventions associated with them) MIPS Instruction Types
1 Lecture 08 Introduction to the MIPS ISA + Procedure Calls in MIPS Longer instructions = more bits to address registers MIPS Datapath 6 bit opcodes... 2 MIPS Instructions are 32 bits More ways to address
More informationCOMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. 5 th. Edition. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle
More information