A Visual Simulation Environment for MIPS Based on VHDL

Transcription

1 A Visual Simulation Environment for MIPS Based on VHDL ÁLVAREZ LLORENTE, J.M.*; PAVÓN PULIDO, N.*; BALLESTEROS RUBIO, J.** * Department of Electonic Engineering, Computer Science and Automatic. University of Huelva ** Department of Computer Science. University of Extremadura Key words : Abstract: VHDL, Hardware simulation, Graphics, Multimedia and Hypermedia in education, Evaluation of educational environments. An application to perform a visual simulation of a machine based on MIPS is presented in this paper. The advantage of this system in relation to conventional simulators is that the simulation engine is the result of a real simulation under a VHDL development environment, so that hardware description can be modified and simulated in several ways to probe and study its running. So, it is possible to join the versatility of a commercial VHDL development tool with the simple handling of a graphic environment. In addition, an assembler language has been defined to write simple applications in order to probe the simulated computer. 1. INTRODUCTION Nowadays, MIPS machine, described in [Pat95], is the most used system as reference in computer architecture teaching. There are many simulators to show how MIPS works, and it is very easy to find complete VHDL MIPS descriptions in the Internet. Our system uses a machine based on the MIPS segmented version with hazard control and a subset of reduced format instructions. The VHDL simulation of a MIPS machine allows to learn the real construction of a CPU. However, many existing tools designed to work with VHDL give as simulation result a very abstract and long time-state 1

2 2 A Visual Simulation Environment for MIPS Based on VHDL sequence, that students, who begin to know how a pipelined CPU works, hardly interpret. Our simulation system wants to offer a graphic interface to make easier the interpretation of the numeric results obtained using a conventional VHDL tool, concretely, the VSIM simulator distributed by Model Technology Inc., version 1.2. Because of limitations of the compiler version used [Mod91], a simplification from the structure of MIPS machine has been performed, reducing the number of instructions and the memory capacity. The result is described below. Simulation process with the new system, begins with the construction of the VHDL machine description [Ash96], where it is possible to make modifications to probe its operation (for example, changing a behaviour description for a structural one). This description is compiled with the Model Technology environment [Mod91]. The next step is creating a program to probe the designed CPU. An assembler language is defined for this purpose. This assembler language allows to make simple programs using the instruction repertory, labels, variables, etc. An editor for source code, and an assembler program to translate the source code into a representation accepted by the VHDL description through a file, have been designed. Later, from the graphic environment, VSIM simulator is called. This simulator is used to show the state of the interesting signals, programming the desired time resolution, and performing a simulation, long enough to get a complete running of the program. Finally, it is necessary to analyse the results file, trying to identify the operations in each segmentation stage, the state and control signals, etc., through a group of binary and decimal numbers taken from the VHDL simulator. But this is very tedious and difficult. So, it is very useful to have a translation graphic environment: the graphic analyser. This tool allows to repeat the simulation, showing the results in a graphic scheme where all blocks and signals in the machine are represented. The activation of the control lines is represented with different colours and the data lines show its contents with a label. There are options to advance and go back in the running process, and perform an auto-animated running process. Thus, it is very easy to study how a program running is performed through the different segmentation stages. 2. GOALS The proposed goals for this system are mainly the following:

3 A Visual Simulation Environment for MIPS Based on VHDL 3 a) Provide a simple and intuitive graphic environment that shows the machine state and allows to advance and go back in the simulation running process. b) Provide a programming language to probe the performance of the machine with different programs in an easy and quick way. c) Use a real VHDL environment to describe the computer. Thus, it is possible to study this language with a real example, taking advantages of a graphic simulation and a suitable compiler. d) Perform a simulation at electric digital signal level. As initial simulation from the VHDL environment can be configured in order to show different groups of machine signals, it is possible to attend to isolate CPU components, as well as to study it in a global way. It is also possible to do both operations in the same simulation, showing or hiding signals for the simulation at different moments. e) Get an adaptable tool with regard to other VHDL simulators. 3. METHODOLOGY As we remarked above, three fundamental component have been designed to compose the application. The core of the simulator is the implementation of the behaviour of a reduced VHDL version of MIPS machine, that performs a real simulation in a file that contains information about times and states. This file is taken by application to show the results in a visual way. On the other hand, the application allows to create simple programs using an assembler language, compile and translate them to a MIPS machine code. Thus, the student can quickly familiarise with operation of a pipeline. The simulator allows to show the data and instructions memory contents. The list of machine code instructions obtained from the compilation process forms the program loaded in instruction memory. MIPS will run these instructions during simulation from VHDL environment. In this step, the file with the simulation data is generated. Later, the application translates this simulation file to make possible to graphically see how different components in the machine changes its state through the time, and to understand how information flows through segmentation stages. Each component of simulator is described below, in detail. 3.1 Reduced MIPS VHDL description A five stages segmented RISC architecture is used as pipeline. Each stage is separated from next by a segmentation register: IF Stage (Instruction

4 4 A Visual Simulation Environment for MIPS Based on VHDL Fetch), IF/ID Register, ID Stage (Instruction Decode), ID/EX Register, EX Stage (Execution), EX/MEM Register, MEM Stage (write in Memory), MEM/WB Register, WB Stage (Write Back). There is a register bank which consists of eight 16-bit registers, called R0 to R7. Instruction memory design uses 2 words in memory (16 bits) for each instruction. The suitable instruction memory size is 128 two-byte words: a words RAM. For data memory, also a RAM has been used. Thus, the memory can be completely addressed by address field of instruction format. Two instruction formats are given: register-register instructions (used in ALU operations), and memory instructions (load, store and jump operations). Register-register instructions use three 3-bit register addressing fields, two as source operand (RS, RT) and one as destination operand (RD). Besides, there is an operation field (CO) identifying instruction format (value 00 for register-register instructions), and an extended operation field (COX) identifying the specific register-register operation (Figure 1-A). There are five instructions: ADD, SUB, AND, OR and SLT, whose meaning is resumed below in Table 1. Instructions with memory addressing have got a single operation field (CO), two register fields (RS, RD), and an 8-bit address field (Figure 1-B). Following instructions are available: LW, SW and BEQ (see Table 1 below). A) B) CO RS RT RD COX CO RS RT ADDRESS Figure 1. Instruction format: A-register-register, B-memory Segmented CPUs have a higher efficiency, but two kinds of hazards are generated because of data dependency between consecutive instructions and jumping control. The first kind of hazards is solved by stalling the pipeline flow until the hazards disappears, and second one is solved by the assumption of the jump is not made. Thus, the resulting block scheme is shown in Figure 2. All the blocks have been described in VHDL at behaviour level. This description can be softly modified, for example, to probe different implementations of the elements defined at behaviour level (for example to probe a structural definition). The possible alterations are limited because the changes made are not shown in the graphic simulator without modify and recompile all the system (it has been developed in Borland Delphi 4 [Día99] language).

5 A Visual Simulation Environment for MIPS Based on VHDL 5 IF/ID ID/EX EX/MEM MEM/WB ADD M UX PC +2 instruction RAM 256 x bit register bank M UX ALU Data RAM 256 x 8 M UX + + Data Dependency Risk Detection Unit Control Risks Detection Unit Figure 2. Pipeline block scheme 3.2 Assembler language description In order to allow programming of the machine, a simple assembler language has been designed. An assembler program is made with a sequence of lines, where each line can be one of the following possibilities: A blank line, which is ignored. A comment. This kind of line begins with two dashes ( -- ), and fills the rest of line. The definition of a variable (DB or DW, the identifier, and an optional default value). The definition of a label (label name followed by a colon). An assembler instruction. The system is not case-sensitive and all the instructions and directives are considered reserved words: ADD, SUB, AND, OR, SLT, LW, SW, BEQ, DB, DW. A valid name for a label or a variable can be any combination of characters made with letters, numbers and underscores, different of any reserved word, any other variable or label. The set of valid instructions for assembler is shown in Table 1. Table 1. Set of assembler instructions Instruction Means Assembler format Performed operation ADD Addition ADD R1 R2 R3 R1 R2 + R3 SUB Substaction SUB R1 R2 R3 R1 R2 R3 AND Logic AND AND R1 R2 R3 R1 R2 R3 OR Logic OR OR R1 R2 R3 R1 R2 R3 SLT Set if Less Than SLT R1 R2 R3 If (R2<R3) R1 1 else R1 0 LW Load Word LW R1 VAR [R2] LW R1 [R2] R1 Memory [VAR + R2] R1 Memory [R2]

6 6 A Visual Simulation Environment for MIPS Based on VHDL Instruction Means Assembler format Performed operation SOFTWARE Store Word SW R1 VAR [R2] SW R1 [R2] Memory [VAR + R2] R1 Memory [R2] R1 BEQ Branch if Equal BEQ R1 R2 VAR If (R1=R2) PC = VAR The eight registers of the machine are addressed by the instructions that use this type of addressing by codes R0 to R7. Memory addressing is made through the use of variables. Variable definitions can be made at any place of assembler program, using reserved words (DB, DW) to specify the variable size. Variable definitions optionally accept an initial value. Label definitions involve the declaration of destination points to perform jumps with the conditional branch instruction (BEQ). Figure 3. Assembler editor window showing a program to perform a simple addition Programming is very easy as the system includes an editor with the most used options in popular Windows applications (cut, paste, find, etc.). Editor is the main window of the system and it is possible to access from it to the rest of the options through menu bars, tool bars and hot keys. Figure 3 shows the editor with an example of a simple program that performs the addition of two numbers. 3.3 Simulation graphic interface description Graphic analyser allows to make a visual study of the behaviour of the machine when a determinate group of instructions is presented. After writing the program using the assembler language, the necessary sequence of steps to analyse the behaviour is the following:

7 A Visual Simulation Environment for MIPS Based on VHDL 7 1. Assemble the program. 2. Simulate assembled program with VSIM (VHDL simulator from Model Technology [Mod91]). Here, we can decide if all signals must be simulated or not, how long the program is run, etc. 3. Finish VSIM and graphically analyse the simulation. Figure 4. Graphic simulation window When the assembled program has been simulated with VSIM, the result of this process can be repeated under our graphic analyser (Figure 4). Our tool allows to advance and go back in simulation time. The machine state is shown by different colours and labels in the lines that represent pipeline scheme: Binary control lines are coloured in red when they are enabled (logic 1), in black when they are disabled (logic 0), or in grey if the state is unknown (if such signal has not been traced for the VSIM simulation). Data lines show their states by a label with their decimal value, or a symbol? when their value is unknown (if such data line has not been traced for the VSIM simulation). Besides manually advancing and going back through time, the file can be simulated by automatic advance with a given speed (this is, the spent time between two state changes). The bottom-right corner of simulation screen

8 8 A Visual Simulation Environment for MIPS Based on VHDL contains a window with information about the names of the signals shown at the moment. VSIM simulation data are stored in a text file (listfile) that contains a list of signals and states. This file is interpreted by the graphic interface to show the machine states, and can be saved to be used later, so, it is possible to analyse stored files that contain information about previous real simulations made with VSIM. VHDL description takes, as data to fill simulated computer memory, two files, ram_mips.dt1 and ram_mips.dt2, corresponding to the last successful compilation of a assembled program. From the environment these files can be consulted. 4. CONCLUSIONS As conclusion, our simulation system gives a lot of advantages and reach all the proposed goals at the beginning of this paper. Visual environment allows to understand how a pipeline works, and it is possible to probe the behaviour of the system with different programs in a very quick and simple way because the system gives an assembler language to perform this task. Besides, the fact of using a real VDHL environment to make a computer description extends the possibilities of the system, as it is a powerful tool to study and understand this language through the simulation and design of real machines. Using the graphic simulator, the results obtained from a real VHDL simulation are easily interpreted. This kind of graphical simulation environments is an often demanded tool for its use in computer architecture teaching. However, it could be desirable that the simulation was not restricted to a short subset of the original MIPS machine, limitation due to the fact that VHDL development tool version used for the system construction does not allow to work with high volume of information. 5. FUTURE WORKS As limitations of the system are known, future works are centred in solving it, following three guidelines: Adapting the system to a modern VHDL environment that allows more possibilities to make simulations and more complexity in the description of segmented unit. Extending the machine to the original size an instruction repertory, as much for the VHDL description as for assembler language.

9 A Visual Simulation Environment for MIPS Based on VHDL 9 Generating an environment to define graphics extensions to the computer architecture without recompiling the system, in order to get the modifications made on the VHDL code accurately reflected on the graphic simulator. 6. REFERENCES Patterson, D.A., Hennessy J.L. (1995). Organización y Diseño de Computadores. McGraw Hill. Ashenden P.J., (1996). The Designers Guide to VHDL, Morgan Kaufmann Publisher. Model Technology Inc. (1991). V-System PC, User's Manual. Díaz, P., Plaza, A., García, F.J., Álvarez, J.M., Pavón, N. (1999). Manual Avanzado de Delphi 4. Anaya Multimedia. 7. AUTHORS ADDRESSES Jesús M. Álvarez Llorente (llorente@uhu.es). Universidad de Huelva, Escuela Politécnica Superior; Carretera Huelva-La Rábida, 21071, Palos de la Frontera (Huelva). Phone: ext Nieves Pavón Pulido (npavon@uhu.es). Universidad de Huelva, Escuela Politécnica Superior; Carretera Huelva-La Rábida, 21071, Palos de la Frontera (Huelva). Phone.: ext Julio Ballesteros Rubio (julioba@unex.es). Universidad de Extremadura, Escuela Politécnica; Ctra. de Trujillo s/n, 10071, Cáceres. Phone.: