Pipelined datapath Staging data. CS2504, Spring'2007 Dimitris Nikolopoulos

Transcription

1 Pipelined datapath Staging data b 55

2 Life of a load in the MIPS pipeline Note: both the instruction and the incremented PC value need to be forwarded in the next stage (in case the instruction is a beq) Note:works in the same way for stores. 56

3 Life of a load in the MIPS pipeline Note: ALU uses the sign-extended 16-bit immediate operand and reg1. Latches keep forwarding all register values and PC+4. 57

4 Life of a load in the MIPS pipeline Note: Latches keep forwarding all register values and PC+4. 58

5 Life of a store in the MIPS pipeline Note:Third stage differs from load in that the value of the second register needs to be forwarded to the MEM stage 59

6 Life of a store in the MIPS pipeline Note:MEM stage differs because memory is written. Write back stage differs because nothing is written to the register file. 60

7 Designing the pipeline All needed information needs to be forwarded through the pipeline registers, e.g. register 2 in the store instruction Each resource can be used in a single pipeline stage, or else we will have structural hazards. 61

8 Fixing the pipeline for load 62

9 Alternative pipeline representation 63

10 Pipeline control No write control needed in IF stage since PC is always written. Multilpexor needed to decide between branch target and PC+4 64

11 Pipeline control No control in ID/reg. read stage. Register write is asserted in writeback steage. 65

12 Pipeline control EX stage needs ALUSrc to decide whether operand comes from register file or is immediate.regdst signal decides which is the destination register (different field in R-instructions and instructions with < 3 reg. operand). Finally, ALUOp controls ALU operation 66

13 Pipeline control MEM stage controls branch, loads and stores. WB stage controls MemToReg to send memory or register value to register file. WB also sets RegWrite signal 67

14 Data Hazards A Bad Sequence sub $2,$1,$3 and $12,$2,$5 or $13,$6,$2 add $14,$2,$2 sw $15,100($2) 68

15 Data Hazards A Bad Sequence Only add and sw get the correct result. Backward lines are trouble! Data hazard can be resolved by forwarding from the EX stage of earlier instruction to the EX stage of later instruction. 69

16 Formally Detecting Hazards EX/MEM.RegisterRd = ID/EX.RegisterRs EX/MEM.RegisterRd = ID/EX.RegisterRt MEM/WB.RegisterRd = ID/EX.RegisterRs MEM/WB.RegisterRd = ID/EX.RegisterRt sub $2,$1,$3 and $12,$2,$5 MEM/WB.RegisterRd = ID/EX.RegisterRs = $2 70

17 Accurate Detection of Hazards Some instructions do not write back to registers. Therefore, we need forwards only if MEM/WB.RegisterRd 0. $0 pinned to zero, therefore we do not forward values destined to $0, i.e. EX/MEM.RegisterRd 0 71

18 Implementing Forwarding The trick is to use the pipeline registers (EX/MEM, MEM/WB) to hold the calculated values from the ALU and forward them to later instructions. To do that we need to take inputs in the ALU from EX/MEM, MEM/WB 72

19 Implementing Forwarding More potential inputs to the ALU, therefore we need a multiplexer. 73

20 Implementing Forwarding More potential inputs to the ALU, therefore we need a multiplexer. 74

21 Implementing Forwarding Logic: Forwarding possibly for R-instructions. Need to pass register numbers in the IF/ID and ID/EX stage and detect whether the source register of a later instruction has the same number as the Rd registers of an earlier instruction 75

22 Forwarding Logic if (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0) and (Ex/MEM.RegisterRd = ID/EXRegisterRs)) Forward A = 10 if (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0) and (Ex/MEM.RegisterRd = ID/EXRegisterRt)) Forward B = 10 76

23 Forwarding Logic if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA =01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB =01 77

24 Forwarding Logic No hazard in WB stage, because instruction can write to and read from register file in the same stage. One more complication: add $1, $1, $2 add $1, $1, $3 add $1, $1, $4 Forwarding simultaneously from the WB and the MEM stage. Need to obtain latest value of $1! 78

25 Corrected forwarding Logic if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) and (EX/MEM.RegisterRd ID/EX.RegisterRs) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA =01 79

26 Corrected forwarding logic 80