Experiment 18 Full Adder and Parallel Binary Adder

Transcription

1 Objectives Experiment 18 Full Adder and Parallel Binary Adder Upon completion of this laboratory exercise, you should be able to: Create and simulate a full adder in VHDL, assign pins to the design, and test it on a CPLD circuit board. Use a VHDL full adder as a component in an 8-bit parallel binary adder. Create a VHDL hierarchical design, including components for full adders and seven-segment decoders, without using the Quartus II Block Editor. Lab Reference Equipment Required Dueck, Robert K., Digital Design with CPLD Applications and VHDL, 2/e Experimental Notes o Chapter 7: Digital Arithmetic and Arithmetic Circuits 7.1 Digital Arithmetic 7.2 Representing Signed Binary Numbers 7.3 Signed Binary Arithmetic 7.6 Binary Adders and Subtractors o CPLD Trainer: The designs in this laboratory exercise are to be done entirely in VHDL, without using the Quartus II Block Editor for any portion of the design. Arithmetic Circuits Circuits for performing binary arithmetic are based on half adders, which add two bits and produce a sum and carry, and full adders, which also account for a carry added from a less significant bit. Full adders can be grouped together to make a parallel binary adder, with n full adders allowing two n-bit numbers to be added, generating an n-bit sum and a carry output. Procedure

2 Note: LEDs on the Altera DE-1 are active-high. This must be accounted for in all your designs. Full Adders 1. The logic diagram for a full adder is shown in Figure Use this diagram to write a VHDL file (I suggest you call the drive?:\qdesigns\labs\lab18\full_add\full_add.vhd. The? is replaced by the drive letter of your flash drive. Do not use the Quartus II Block Editor. 2. The VHDL file goes in the lab Figure 18.1 Full Adder Circuit 3. Save the full adder design file and use it to create a project in Quartus II. Compile the VDHL file. 4. Write a set of simulation criteria to verify the correctness of your design. Use the criteria to create a simulation for the full adder. Set the a input with a multiple of 1, the b input with a multiple of 2 and the c_in input with a multiple of 4. This will cover all the input conditions. 5. Simulate and verify the correct operation. The simulation result goes in the lab Parallel Adder 1. Create a new folder for an 4-bit parallel adder. Use the Quartus II New Project Wizard to make a project for the parallel adder. I suggest you use drive?:\qdesigns\labs\lab18\paradd The? is your flash drive letter. As you creat the new project, you will need to attach the full_add.vhd file to the new project. 2. Click on the icon and find your full_add file.

3 3. Then click on Add Figure 18.2: Find a file to add.

4 Figure 18.3: Add a file 4. The file and path will appear as shown in Figure 18.3 Then click OK 5. Create an 4-bit parallel adder in VHDL, using a GENERATE statement and the component full_add.vhd from the previous section. Do not use a block diagram file. I suggest a file name of paradd.vhd. The VHDL File goes in your lab 6. Permanently assign the carry input (C0) to a logic LOW. You can do this by declaring a signal, c, for the carry bits and assigning the element for c(0) to a value of 0. Use this element as the carry input to the first full adder.

5 Predicted Actual A B C_4 Σ 3, Σ 2, Σ 1, Σ 0 C_4 Σ 3, Σ 2, Σ 1, Σ Table 18.1 Results Table for an 4-Bit Parallel Adder 7. Assign pins to the 4-bit adder. Use the DE1 Pin Assignment Sheet found on Blackboard. 8. Compile the file and download the design for the 4-bit parallel adder to your CPLD board. Complete Table Table 18.1 goes in the results section of your