Introduction to Schematic Entry using Xilinx ISE and Digital Logic Simulation using ModelSim MXE
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1 Introduction to Schematic Entry using Xilinx ISE and Digital Logic Simulation using ModelSim MXE 1. Synopsis: This lab introduces Xilinx Schematic Editor to input a digital design and ModelSim to simulate the same. In this lab, you will implement a simple middle finder design. Given three 4-bit unsigned numbers, you compare them and output the middle number. 2. ISE WebPack and ModelSim MXE installation and testing: It is assumed that you finished installing the ISE WebPack and ModelSim MXE tools on your home PC (desktop/laptop) and also tested the installation with the test projects provided to you. Of particular interest to us is the ModelSim test project involving verilog source files for the middle finder design (middle_finder.v) and the test bench for the same (middle_finder_tb.v). 3. Lecture/Demo Video: Before coming to the lab session, you are required to watch the Introduction to Xilinx Schematic Editor video (posted on the class web site). It is a screen-capture of an entire session of Xilinx Schematic Editor starting from invoking the tool to schematic entry, test fixture creation and simulation, and finally downloading to the Nexys2 FPGA board. In this tutorial, a 1-bit full-adder was designed and then, using 4 such full adders, a 4-bit adder was designed. These were then simulated using the Modelsim MXE and finally implemented and downloaded to the Nexys2 board. Please enter the 4-bit adder design in a schematic and simulate it based on the video and the associated power-point file and the requirements stated below. Your schematics and symbols: Make your schematics look different from the schematics provided to you along with the tutorial. You can use different layout, pin labels, and symbol shapes to differentiate your work. Rename the adder4-bit folder provided to you as adder4bit_hide. Start your project and name it adder4bit. Copy the symbol file USC_CENG_border.sym from this folder to your adder4bit project folder. Your adder1bit.sch: First build a half-adder (ha.sch). Make a symbol for the half-adder (ha.sym). Using two of these half-adders and an OR gate (or2), build a full-adder (adder1bit.sch). Use the labels X, Y, Cin, S, Cout in place of the labels A, B, Ci, S, Co used in the tutorial. Create a test bench (adder1bit_tb.v) and simulate it. Then build a symbol for your full-adder (adder1bit.sch) with pin layout slightly different. Use bus labels X(3:0), Y(3:0) instead of A(3:0), B(3:0) in your adder4bit.sch. Create a test bench (adder4bit_tb.v) and simulate it. Show these schematic, symbol, and test bench files to your TA. Note: For this lab, the prelab is actually more important than the lab itself! ee201l_schematic_entry_middle_finder.fm [Revised: 9/3/08] 1/7
2 4. Prelab: (Use back of the page if you need additional space. Complete this before coming to the lab.) 4.1 Please install Xilinx ISE WebPack and ModelSim MXE on your home laptop / desktop. The step-by-step procedure to install the tools has been posted to the class web site. (5 pts) Installed / Did not install yet. 4.2 Please test your installation of Xilinx ISE WebPack and ModelSim MXE using test projects posted on the class web site. (5 pts) Tested / Did not test yet. 4.3 Watch the Introduction to Xilinx Schematic Editor lecture/demo video. (10 pts) Watched / Did not watch it yet. After having watched the lecture/demo video, answer the following Prelab questions: Q 4. 4: Two nets with same names (labels) but not physically connected to each other are logically connected to each other. (5 pts) True / False Q 4. 5: If there is a solid blue square dot at the junction crossing two wires, these wires are (connected/ not connected) to each other. A (hollow red square dot / solid blue square dot) indicates a dangling end of a wire. (5 pts) Q 4. 6: Mr. and Ms. Bruin made the schematics for a 1-bit adder. After saving the schematics, they set and wanted to run. What did they forget to do? (5 pts) Q 4. 7: Mr. and Ms. Bruin finally manage to get Modelsim to run but have no clue about how to verify their design from there. What do they need to do? (5 pts) Q 4. 8: How do you create a symbol? (5pts) Q 4. 9: How do you switch between sheets? (5 pts) For going to the next sheet: For going back to the previous sheet: Q 4. 10: What is the purpose of labelling an instance of a design (for example each of the four full adders in the 4-bit adders)? (5 pts) ee201l_schematic_entry_middle_finder.fm [Revised: 9/3/08] 2/7
3 5. Procedure: 5.1 Follow the guidelines given in the tutorial exercise (posted at the class web site) and implement and simulate the 4-bit adder covered in the tutorial. This is just to familiarize you with the Xilinx Schematic Editor and Modelsim. 5.2 Middle Finder design: Given three 4-bit unsigned numbers, compare them and find the middle number You need to enter your combinational logic design using Xilinx schematic entry and simulate it using a Verilog Test Fixture (test bench). Incidentally, this middle finder design was given to you in Verilog as a test program to test your ModelSim installation. 5.3 Incomplete schematic of the middle finder (to be entered by you and completed by you) is given on the next page. Design the need random logic to exercise control on the select lines (S1, S0) of the muxes based on the comparators inference (A_GT_B, B_GT_C, A_GT_C). Fill-in the following truth-table, writing X for don t care as many times as possible. You need to create your own schematic for a 4-bit wide 2-to-1 mux and then create a symbol using the symbol wizard. ee201l_schematic_entry_middle_finder.fm [Revised: 9/3/08] 3/7
4 5.4 ee201l_schematic_entry_middle_finder.fm [Revised: 9/3/08] 4/7
5 5.5 Use the following Verilog code segment as a pseudo code to guide your design. ee201l_schematic_entry_middle_finder.fm [Revised: 9/3/08] 5/7
6 5.6 Your test bench can be on the following lines. ee201l_schematic_entry_middle_finder.fm [Revised: 9/3/08] 6/7
7 6. Lab Report: Name: Lab Session: Date: TA s Signature: For TAs: Prelab (out of 65): Report (out of 85): Comments: Q 6. 1: Submit the completed truth table and K-Maps for producing S1 and S0. (15 pts) Q 6. 2: Print and attach the following items to your report. (a) the schematics (FourBit_2_to_1_mux.sch, middle_finder.sch), (20 pts) (b) the simulation waveform for the middle_finder. (5 pts) You can print the schematic like any other document using the File => Print method on windows. If you do not have a printer attached to your PC, you can create a pdf file of the schematic or waveform by File => Print method and choosing Adobe PDF as the printer in the print dialog box. Of course you need the Adobe PDF software installed on your PC. Q 6. 3: Are the following, valid simulation commands? Try them on the modelsim tool and answer.(5 pts) VSIM>run 20ns VSIM>run 20 VSIM>run 20 ns VSIM>run 20 cycles ee201l_schematic_entry_middle_finder.fm [Revised: 9/3/08] 7/7
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