Sub-programs in VHDL
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1 ECE381(CAD), Lecture 12: Sub-programs in VHDL Mehdi Modarressi Department of Electrical and Computer Engineering, University of Tehran Pictures and examples are taken from the slides of VHDL: Analysis & Modeling of Digital Systems and also from VHDL by Example
2 Introduction Procedures and functions in VHDL Differences between procedures and functions Readings: 1. VHDL: Analysis & Modeling of Digital Systems : Chapter 6.1 and VHDL by Example : Chapter 3 3. Designers Guide To VHDL : chapter 7 and 11 2
3 Introduction Procedures/Subroutines/Functions in SW programming languages The same functionality, in different places Use function call instead of repeating the code VHDL equivalence: Procedures and Functions 3
4 Subprograms The statements inside a subprogram are executed sequentially The same statements that exist in a process statement can be used in a subprogram Such as loops and WAIT statements When a function is called, it returns the value in zero time Declaration and call: First the subprogram is declared, then elsewhere it is called We can write a subprogram declaration in the declarative part of an architecture or the declarative part of a process 4
5 Functions Recall the comparator example: a_gt_band a_lt_bhave the same functionality but on different inputs 5
6 Functions Use function call instead of Boolean expressions to reuse the code 6
7 Functions Two typical applications of functions in VHDL: Conversion: convert different types Resolution: resolve the signal value from different values assigned by different drivers 7
8 Conversion functions A function to convert bit_vector to integer Functions have declarative and body parts to_integer(x) is an integer Can be used anywhere an integer is expected variable y: integer; variable x: bit_vector(0 to 7); y=to_integer(x)+5; 8
9 9
10 Resolution function Normally several sources cannot drive a signal Real circuits smoke! An error in VHDL 10
11 Resolution function Multiple drivers is possible only if a resolution exists Example in hardware is "open collector Pull_up provides resolution 11
12 Resolution function To allow multiple drivers for a signal, we must resolve the signal Get a function that takes different values and resolve the final signal value from them Resolution function Bit_Vector BIT := 1 ; Bit IS 12
13 Resolution function Define the resolution function for a signal 13! Qit is a 4-value data that is introduced in basic_utils package in VHDL, Analysis and modeling. book. It takes 0, 1, X, and Z
14 14
15 Resolution function Types and subtypes can also be resolved All signals from that subtype are resolved Example: std_logicis a resolved type In IEEE library, std_logic_1164 package 15
16 Std_logictype Similar to bit, but a 9-value type To model the signals more precisely First define std_ulogic: an unresolved type 16
17 Std_logictype Then define std_logic: a subtype of std_ulogicwhich is resolved Using a resolution function with the name resolved Part of std_logic package declaration: 17
18 std_logicresolution function To resolve the final value, when several drivers drive the signal at the same time An array containing several values is passed to the function and a single bit is returned 18
19 Procedures Like functions, but accept multiple inputs and outputs and inouts A procedure call is considered a statement of its own function usually exists as part of an expression.. y<=func(x); Proc(x);. The most usual case of using a procedure is when more than one value is returned Procedures have roughly the same syntax and rules as function 19
20 A procedure without parameters Procedure is declared in the declarative part of the process It has no input, just works on the global signals of the architecture 20
21 Procedures Procedure with input parameter Declaration: Call:... 21
22 Procedure-IN and OUT parameters Procedure declaration Procedure call 22
23 Procedure parameter list The parameter mode should be defined: IN, OUT, INOUT The rules of the entity ports are applied: e.g.: the statements in the procedure can use parameter values in the IN mode but cannot modify it Mode is an optional part If we leave it out, mode IN is assumed 23
24 Procedure parameter list In addition to mode, the class of parameters should be defined Parameters can have three classes: Variable, Signal, Constant If we don t specify the class, default classes will be used: Constant for IN parameters Variable for out parameters 24
25 Signal parameters A signal parameter can be of any of the modes in, out or inout The way that signal parameters work is somewhat different from constant and variable parameters Constant and variable IN parameters: the parameter value is sampled at the call time and the value is passed to the procedure Signal: Instead of passing the value of the signal, the signal object itself is passed to procedure Signal parameter: If the procedure executes a wait statement, the signal value may be different after the wait statement completes and the procedure resumes 25
26 Signal parameters The process packet_assemblercalls the procedure receive_packet After each wait, the current value of rx_data is read When the procedure reaches the wait statement, it is really the calling process that suspends 26
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Outline CPE 626. Advanced VLSI Design. Lecture 4: VHDL Recapitulation (Part 2) Signals. Variables. Constants. Variables vs.
CPE 626 Lecture 4: VHDL Recapitulation (Part 2) Aleksandar Milenkovic http://www.ece.uah.edu/~milenka http://www.ece.uah.edu/~milenka/cpe626-04f/ milenka@ece.uah.edu Assistant Professor Electrical and
1 ST SUMMER SCHOOL: VHDL BOOTCAMP PISA, JULY 2013
MARIE CURIE IAPP: FAST TRACKER FOR HADRON COLLIDER EXPERIMENTS 1 ST SUMMER SCHOOL: VHDL BOOTCAMP PISA, JULY 2013 Introduction to VHDL Calliope-Louisa Sotiropoulou PhD Candidate/Researcher Aristotle University
VHDL. Chapter 7. Behavioral Modeling. Outline. Behavioral Modeling. Process Statement
Chapter 7 VHDL VHDL - Flaxer Eli Ch 7-1 Process Statement Outline Signal Assignment Statement Variable Assignment Statement Wait Statement If-Then-Else Statement Case Statement Null Statement Loop Statement
Digital Systems Design
Digital Systems Design Review of Combinatorial Circuit Building Blocks: VHDL for Combinational Circuits Dr. D. J. Jackson Lecture 2-1 Introduction to VHDL Designer writes a logic circuit description in
C-Based Hardware Design
LECTURE 6 In this lecture we will introduce: The VHDL Language and its benefits. The VHDL entity Concurrent and Sequential constructs Structural design. Hierarchy Packages Various architectures Examples