CS 153 Design of Operating Systems Spring 18

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1 CS 153 Design of Operating Systems Spring 18 Lectre 10: Lock Implementation Instrctor: Chengy Song Slide contribtions from Nael Ab-Ghazaleh, Harsha Madhyvasta and Zhiyn Qian

2 Recap: Synchronization Race Condition can happen between threads with shared data Concrrent At least one write Synchronization is necessary to provide Safety, liveness, performance Mechanisms Bilding blocks: atomic read and write Alternation, lock CSE 153 Lectre 10 Synchronization (2) 2

3 Locks A lock is an object in memory providing two operations acqire(): before entering the release(): after leaving a Threads pair calls to acqire() and release() Between acqire()/release(), the thread holds the lock acqire() does not retrn ntil any previos holder releases What can happen if the calls are not paired? CSE 153 Lectre 10 Synchronization (2) 3

4 Using Locks withdraw (accont, amont) { acqire(lock); balance = get_balance(accont); balance = balance amont; pt_balance(accont, balance); release(lock); retrn balance; Critical Section acqire(lock); balance = get_balance(accont); balance = balance amont; acqire(lock); pt_balance(accont, balance); release(lock); balance = get_balance(accont); balance = balance amont; pt_balance(accont, balance); release(lock); Why is the retrn otside the? Is this ok? What happens when a third thread calls acqire? CSE 153 Lectre 10 Synchronization (2) 4

5 First try pthread_trylock(mtex) { if (mtex==0) { mtex= 1; retrn 1; else retrn 0; Thread 0, 1, //time to access critical region while(!pthread_trylock(mtex); // wait <critical region> pthread_nlock(mtex) Does this work? Assme reads/writes are atomic The lock itself is a critical region! Chicken and egg Compter scientist strggled with how to create software locks CSE 153 Lectre 10 Synchronization (2) 5

6 Second try int trn = 1; while (tre) { while (trn!= 1) ; trn = 2; otside of while (tre) { while (trn!= 2) ; trn = 1; otside of This is called alternation It satisfies mtex: If ble is in the, then trn == 1 and if yellow is in the then trn == 2 (trn == 1) (trn!= 2) Is there anything wrong with this soltion? CSE 153 Lectre 10 Synchronization (2) 6

7 Third try two variables Bool flag[2] while (flag[1]!= 0); flag[0] = 1; flag[0]=0; otside of while (flag[0]!= 0); flag[1] = 1; flag[1]=0; otside of We added two variables to try to break the race for the same variable Is there anything wrong with this soltion? CSE 153 Lectre 10 Synchronization (2) 7

8 Forth try set before yo check Bool flag[2] flag[0] = 1; while (flag[1]!= 0); flag[0]=0; otside of flag[1] = 1; while (flag[0]!= 0); flag[1]=0; otside of Is there anything wrong with this soltion? CSE 153 Lectre 10 Synchronization (2) 8

9 Fifth try doble check & back off Bool flag[2] flag[0] = 1; while (flag[1]!= 0) { flag[0]=0; flag[0] = 0; wait a short time; flag[0] = 1; otside of flag[1] = 1; while (flag[0]!= 0) { flag[1]=0; flag[1] = 0; wait a short time; flag[1] = 1; otside of CSE 153 Lectre 10 Synchronization (2) 9

10 Six try Dekker s Algorithm Bool flag[2]l Int trn = 1; flag[0] = 1; while (flag[1]!= 0) { //while if(trn == 2) { flag[0] = 0; while (trn == 2); flag[0] = 1; //if flag[0]=0; trn=2; otside of flag[1] = 1; while (flag[0]!= 0) { //while if(trn == 1) { flag[1] = 0; while (trn == 1); flag[1] = 1; //if flag[1]=0; trn=1; otside of CSE 153 Lectre 10 Synchronization (2) 10

11 Peterson's Algorithm int trn = 1; bool try1 = false, try2 = false; while (tre) { try1 = tre; trn = 2; while (try2 && trn!= 1) ; try1 = false; otside of while (tre) { try2 = tre; trn = 1; while (try1 && trn!= 2) ; try2 = false; otside of This satisfies all the reqirements Here's why... CSE 153 Lectre 10 Synchronization (2) 11

12 Peterson's Algorithm: analysis int trn = 1; bool try1 = false, try2 = false; while (tre) { { try1 (trn == 1 trn == 2) 1 try1 = tre; { try1 (trn == 1 trn == 2) 2 trn = 2; { try1 (trn == 1 trn == 2) 3 while (try2 && trn!= 1) ; { try1 (trn == 1 try2 (try2 (yellow at 6 or at 7)) 4 try1 = false; { try1 (trn == 1 trn == 2) otside of while (tre) { { try2 (trn == 1 trn == 2) 5 try2 = tre; { try2 (trn == 1 trn == 2) 6 trn = 1; { try2 (trn == 1 trn == 2) 7 while (try1 && trn!= 2) ; { try2 (trn == 2 try1 (try1 (ble at 2 or at 3)) 8 try2 = false; { try2 (trn == 1 trn == 2) otside of (ble at 4) try1 (trn == 1 try2 (try2 (yellow at 6 or at 7)) (yellow at 8) try2 (trn == 2 try1 (try1 (ble at 2 or at 3))... (trn == 1 trn == 2) CSE 153 Lectre 10 Synchronization (2) 12

13 Synchronization so far while (tre) { try1 = tre; trn = 2; while (try2 && trn!= 1) ; try1 = false; otside of Compiler transforms to try1 = false; trn = 2; while (tre) { while (try2 && trn!= 1) ; otside of We looked at how to bild software locks Difficlt Worse: it doesn t really work» Compilers don t think mlti-threaded» Hardware reorders memory ops: memory consistency models Lets get help from the hardware! CSE 153 Lectre 10 Synchronization (2) 13

14 Hardware to the resce Crx of the problem: We get interrpted between checking the lock and setting it to 1 Software locks reordered by compiler/hardware Possible soltions? Atomic instrctions: create a new assembly langage instrction that checks and sets a variable atomically» Cannot be interrpted!» How do we se them? Disable interrpts altogether (no one else can interrpt s) CSE 153 Lectre 10 Synchronization (2) 14

15 Atomic Instrction: Test-and-Set The semantics of test-and-set are: Record the old vale Set the vale to indicate available Retrn the old vale Hardware exectes it atomically! When execting test-and-set on flag bool test_and_set (bool *flag) { bool old = *flag; *flag = Tre; retrn old; One read One write while (lock->held); lock->held = 1; What is vale of flag afterwards if it was initially False? Tre? What is the retrn reslt if flag was initially False? Tre? CSE 153 Lectre 10 Synchronization (2) 15

Using Test-and-Set Here is or lock implementation with test-and-set: strct lock { int held = 0; void acqire (lock) { while (test-and-set(&lock->held)); void release (lock) { lock->held

16 Using Test-and-Set Here is or lock implementation with test-and-set: strct lock { int held = 0; void acqire (lock) { while (test-and-set(&lock->held)); void release (lock) { lock->held = 0; When will the while retrn? What is the vale of held? Does it satisfy critical region reqirements? (mtex, progress, bonded wait, performance?) CSE 153 Lectre 10 Synchronization (2) 16

17 Still a Spinlocks The problem with spinlocks is that they are wastefl Althogh still sefl in some cases; lets discss advantages and disadvantages If a thread is spinning on a lock, then the schedler thinks that this thread needs CPU and pts it on the ready qee If N threads are contending for the lock, the thread which holds the lock gets only 1/N th of the CPU CSE 153 Lectre 10 Synchronization (2) 17

18 Disabling Interrpts Another implementation of acqire/release is to disable interrpts: strct lock { void acqire (lock) { disable interrpts; void release (lock) { enable interrpts; Note that there is no state associated with the lock Can two threads disable interrpts simltaneosly? CSE 153 Lectre 10 Synchronization (2) 18

19 On Disabling Interrpts Disabling interrpts blocks notification of external events that cold trigger a context switch (e.g., timer) In a real system, this is only available to the kernel Why? Disabling interrpts is insfficient on a mltiprocessor Back to atomic instrctions Like spinlocks, only want to disable interrpts to implement higher-level synchronization primitives Don t want interrpts disabled between acqire and release CSE 153 Lectre 10 Synchronization (2) 19

20 Smmarize Where We Are Goal: Use mtal exclsion to protect s of code that access shared resorces Method: Use locks (spinlocks or disable interrpts) Problem: Critical sections can be long Spinlocks: Threads waiting to acqire lock spin in test-and-set loop Wastes CPU cycles Longer the CS, the longer the spin Greater the chance for lock holder to be interrpted Memory consistency model cases problems (ot of scope of this class) acqire(lock) Critical section release(lock) Disabling Interrpts: Shold not disable interrpts for long periods of time Can miss or delay important events (e.g., timer, I/O) CSE 153 Lectre 10 Synchronization (2) 20

21 Higher-Level Synchronization Spinlocks and disabling interrpts are sefl for short and simple s Can be wastefl otherwise These primitives are primitive don t do anything besides mtal exclsion Need higher-level synchronization primitives that: Block waiters Leave interrpts enabled within the All synchronization reqires atomicity So we ll se or atomic locks as primitives to implement them CSE 153 Lectre 10 Synchronization (2) 21

22 Implementing Locks: Block Waiters Block waiters, interrpts enabled in s strct lock { int held = 0; qee Q; void acqire (lock) { Disable interrpts; if (lock->held) { pt crrent thread on lock Q; block crrent thread; lock->held = 1; Enable interrpts; void release (lock) { Disable interrpts; if (Q) remove and nblock a waiting thread; else lock->held = 0; Enable interrpts; acqire(lock) Interrpts Disabled Critical section Interrpts Enabled release(lock) Interrpts Disabled CSE 153 Lectre 10 Synchronization (2) 22

23 Implementing Locks: Yield on Wait Instead of spinning, yield the CPU strct lock { int held = 0; void acqire (lock) { while (test-and-set(&lock->held)) { thread_yield(); void release (lock) { lock->held = 0; CSE 153 Lectre 10 Synchronization (2) 23

24 Advanced Topics Test-and-set with back-off (exponential works best) Ticket lock Wait qee Liveness reqirement Performance reqirement Array-based qee List-based qee» MCS, JM Mellor-Crmmey and ML Scott (2006 Edsger Dijkstra Prize) CSE 153 Lectre 10 Synchronization (2) 24

25 Next class Semaphores Preparation Read Modle 31 Little Book on Semaphores CSE 153 Lectre 10 Synchronization (2) 25

CS 153 Design of Operating Systems Spring 18

CS 153 Design of Operating Systems Spring 18 Lectre 11: Semaphores Instrctor: Chengy Song Slide contribtions from Nael Ab-Ghazaleh, Harsha Madhyvasta and Zhiyn Qian Last time Worked throgh software implementation