1048: Computer Organization

Transcription

1 48: Compter Organization Lectre 5 Datapath and Control Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-

2 Introdction In this lectre, we will try to implement simplified IPS which contain emory reference instrctions: lw, sw Control flow instrctions: beg, j Arithmetic-logical instrctions: add, sb, and, or, slt Design principles ake the common case fast Simplicity favors reglarity Two types of circits/fnction nits Combinational: elements that operate on vales Seqential: elements that contain state Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-2

3 Otline Part A: Designing a Single-Cycle Processor Part B: Designing a lticycle Processor Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-3

4 Part A Otline Designing a processor Bilding the path A single-cycle implementation Control for the single-cycle CPU Control of CPU operations controller ain controller Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-4

5 How to Design a Processor?. Analyze instrction set (path reqirements) The meaning of each instrction is given by the register transfers Datapath mst inclde storage element Datapath mst spport each register transfer 2. Select set of path components and establish clocking methodology 3. Assemble path meeting the reqirements 4. Analyze implementation of each instrction to determine setting of control points effecting register transfer 5. Assemble the control logic Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-5

6 Step : Analyze Instrction Set All IPS instrctions are bits long with 3 formats: R-type: op rs rt rd shamt fnct I-type: 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt immediate 6 bits 5 bits 5 bits 6 bits J-type: 3 26 op target address 6 bits 26 bits The different fields are: op: operation of the instrction rs, rt, rd: sorce and destination register shamt: shift amont fnct: selects variant of the op field address / immediate target address: target address of jmp 5A-6

7 Or Eample: A IPS Sbset R-Type: add rd, rs, rt sb rd, rs, rt and rd, rs, rt or rd, rs, rt slt rd, rs, rt Load/Store: lw rt,rs,imm6 sw rt,rs,imm6 Imm operand: 3 3 addi rt,rs,imm6 Branch: beq rs,rt,imm6 Jmp: j target op rs rt rd shamt fnct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 26 2 op rs rt immediate 6 bits 5 bits 5 bits 6 bits 26 2 Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A op address 6 bits 26 bits 6

8 Logical Register Transfers RTL gives the meaning of the instrctions All start by fetching the instrction, read registers, then se => simplicity and reglarity help E[ PC ] = op rs rt rd shamt fnct or = op rs rt Imm6 or = op Imm26 (added at the end) Inst Register transfers ADD R[rd] <- R[rs] + R[rt]; PC <- PC + 4 SUB R[rd] <- R[rs] - R[rt]; PC <- PC + 4 LOAD R[rt] <- E[ R[rs] + sign_et(imm6)]; PC <- PC + 4 STORE E[ R[rs] + sign_et(imm6) ] <-R[rt]; PC <- PC + 4 ADDI R[rt] <- R[rs] + sign_et(imm6)]; PC <- PC + 4 BEQ if (R[rs] == R[rt]) then PC <- PC sign_et(imm6)] else PC <- PC + 4 Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-8

9 Reqirements of Instrction Set After checking the register transfers, we can see that path needs the followings: emory store instrctions and Registers ( ) read RS read RT RT or RD PC Etender for zero- or sign-etension Add and sb register or etended immediate () Add 4 or etended immediate to PC Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-9

10 Otline Designing a processor Bilding the path A single-cycle implementation Control for the single-cycle CPU Control of CPU operations controller ain controller Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-

11 Step 2a: Datapath Components Basic bilding blocks of combinational logic elements : A B Adder Adder CarryIn A B Sm Carry control 4 Select A Y B Reslt UX UX 5A-

12 Conclding Remarks ake sre yo nderstand the abstractions!! Sometimes it is easy to think yo do, when yo don t Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-2

13 Step 2b: Datapath Components Storage elements: Register: Similar to the D Flip Flop, ecept N-bit inpt and otpt Enable inpt negated (): Data Ot will not change asserted (): Data Ot will become Data In Enable Data In N Data Ot N Clk 5A-3

14 Storage Element: Register File Consists of registers: Appendi B.8 Two -bit otpt bsses: bsa and bsb One -bit inpt bs: bsw Register is selected by: RA selects the register to pt on bsa () RB selects the register to pt on bsb () RW selects the register to be written via bsw () when Enable is Clock inpt (CLK) The CLK inpt is a factor ONLY dring write operation Dring read, behaves as a combinational circit Enable bsw Clk RW RA RB bit Registers bsa bsb Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-4

15 Storage Element: emory emory (idealized) Appendi B.8 One inpt bs: Data In One otpt bs: Data Ot Word is selected by: Address selects the word to pt on Data Ot Enable Address Data In DataOt Clk Enable = : address selects the memory word to be written via the Data In bs Clock inpt (CLK) The CLK inpt is a factor ONLY dring write operation Dring read operation, behaves as a combinational logic block: Address valid => Data Ot valid after access time No need for read control Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-5

16 Step 3a: Datapath Assembly Instrction fetch nit: common operations Fetch the instrction: mem[pc] Update the program conter: Seqential code: PC <- PC + 4 Branch and Jmp: PC <- Something else Add 4 PC address Instrction memory Instrction Fig A-6

17 Step 3b: Add and Sbtract R[rd] <- R[rs] op R[rt] 3 Two read ports and one write port op rs rt rd shamt fnct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits rs rt rd E: add rd, rs, rt Ra, Rb, Rw come from inst. s rs, rt, and rd fields and Reg: control logic after decode Instrction register register 2 Registers register 2 Reg 4 6 Zero reslt operation(fnct) Fig A-7

18 Step 3c: Store/Load Operations R[rt]<-em[R[rs]+SignEt[imm6]] E: lw rt,rs,imm op rs rt immediate 6 bits 5 bits 5 bits rd 6 bits 6 Instrction rs rt rt register register 2 Registers register Reg 2 43 operation Zero reslt Address em Data memory 6 Sign etend em Fig A-8

19 Datapath for emory and R-type (b+c), also for addi Instrction register register 2 Registers register Reg 2 Src 4 operation Zero reslt Address em Data memory emtoreg 6 Sign etend em Fig. 5. Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-9

20 Step 3d: Branch Operations beq rs, rt, imm6 mem[pc] Fetch inst. from memory Eqal <- R[rs] == R[rt] Calclate branch condition if (COND == ) Calclate net inst. address PC <- PC ( SignEt(imm6) 4 ) else PC <- PC op rs rt immediate 6 bits 5 bits 5 bits 6 bits Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-2

21 Datapath for Branch Operations beq rs, rt, imm6 PC + 4 from instrction path Only roting Shift left 2 Add Sm Branch target Instrction register register 2 Registers register Reg operation Zero To branch control logic 6 Sign etend Fig A-2

22 Otline Designing a processor Bilding the path A single-cycle implementation Control for the single-cycle CPU Control of CPU operations controller ain controller Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-22

23 A Single Cycle Datapath PCSrc 4 Add Reg Shift left 2 Add reslt PC address Instrction [3 ] Instrction memory Instrction [25 2] Instrction [2 6] Instrction [5 ] RegDst Instrction [5 ] register register 2 register 2 Registers 6 Sign etend Src control Zero reslt em Address Data memory em emtoreg Fig. 5.5 Instrction [5 ] Op Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-23

24 Data Flow dring addfig. 5. PCSrc 4 Add Shift left 2 Add reslt.. PC address Clocking Instrction Instrction memory register register 2 register Registers 2 Reg 6 Sign etend Src 4 3 operation Zero reslt Address em em Data memory emtoreg Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-24

25 Clocking ethodology Define when signals are read and written Assme edge-triggered (synchronos design): Vales in storage (state) elements pdated only on a clock edge => clock edge shold arrive only after inpt signals stable Any combinational circit mst have inpts from and otpts to storage elements Clock cycle: time for signals to propagate from one storage element, throgh combinational circit, to reach the second storage element A register can be read, its vale propagated throgh some combinational circit, new vale is written back to the same register, all in same cycle => no feedback within a single cycle Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-25

26 Register-Register Timing Clk PC Rs, Rt, Rd, Op, Fnc ctr Old Vale Clk-to-Q New Vale Old Vale Old Vale Instrction emory Access Time New Vale Delay throgh Control Logic New Vale RegWr Old Vale New Vale bsa, B bsw Old Vale Old Vale Register File Access Time New Vale Delay New Vale Clk PC Ideal Instrction emory RegWr bsw Clk Rd Rs Rt Rw Ra Rb -bit Registers bsa bsb ctr Register Occrs Here Reslt

27 The Critical Path Register file and ideal memory: Dring read, behave as combinational logic: Address valid => Otpt valid after access time Net Address Instrction Address Clk Ideal Instrction emory PC Rd 5 Clk Instrction Rs 5 Rt 5 Rw Ra Rb -bit Registers Imm 6 A B Critical Path (Load Operation) = PC s Clk-to-Q + Instrction memory s Access Time + Register file s Access Time + to Perform a -bit Add + Data emory Access Time + Setp Time for Register File + Clock Skew Data Address Data In Clk Ideal Data emory

28 Clk PC Rs, Rt, Rd, Op, Fnc ctr Old Vale Worst Case Timing (Load) Clk-to-Q New Vale Instrction emoey Access Time Old Vale New Vale Delay throgh Control Logic Old Vale New Vale EtOp Old Vale New Vale Src Old Vale New Vale emtoreg Old Vale New Vale RegWr Old Vale New Vale bsa bsb Old Vale Delay throgh Etender & Old Vale Register Occrs Register File Access Time New Vale New Vale Delay Address Old Vale New Vale Data emory Access Time bsw Old Vale New

29 Otline Designing a processor Bilding the path A single-cycle implementation Control for the single-cycle CPU Control of CPU operations controller ain controller Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-29

30 Control To select the operations to perform, read/write, etc To control the flow of ltipleor inpts Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-3

31 Step 4: Control Points and Signals Inst. emory Addr Instrction<3:> <2:25> Op Fnct Rt <:5> <:5> <6:2> <2:25> Rs Rd Imm6 Control PCsrc RegDst RegWr Src emwr emrd ctr emtoreg Eqal Datapath Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-3

32 Designing ain Control Some observations: opcode (Op[5-]) is always in bits 3-26 two registers to be read are always in rs (bits 25-2) and rt (bits 2-6) (for R-type, beq, sw) base register for lw and sw is always in rs (25-2) 6-bit offset for beq, lw, sw is always in 5- destination register is in one of two positions: lw: in bits 2-6 (rt) R-type: in bits 5- (rd) => need a mltiple to select the address for written register Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-

33 Datapath with and Control PCSrc 4 Add Reg Shift left 2 Add reslt PC address Instrction [3 ] Instrction memory Instrction [25 2] Instrction [2 6] Instrction [5 ] RegDst Instrction [5 ] register register 2 register 2 Registers 6 Sign etend Src control Zero reslt em Address Data memory em emtoreg Control point Instrction [5 ] Op Fig. 5.5 Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-33

34 Datapath with Control Unit 4 Add Instrction [3 26] Control RegDst Branch em emtoreg Op em Src Reg Shift left 2 Add reslt PCSrc PC address Instrction memory Instrction [3 ] Instrction [25 2] Instrction [2 6] Instrction [5 ] register register 2 Registers 2 register Zero reslt Address Data memory Fig. 5.7 Instrction [5 ] Instrction [5 ] 6 Sign etend control Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-34

35 Operation of Datapath: add op rs rt rd shamt fnct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add rd, rs, rt mem[pc]. Fetch the instrction PC+4 from memory R[rs], R[rt] R[rs] + R[rt] R[rd] <- PC <- PC+4 2. Instrction decode and read operands 3. Eecte the actal operation 4. back to target register Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-35

36 Instrction Fetch at Start of add. instrction <- mem[pc]; PC + 4 Fig Add Instrction [3 26] Control RegDst Branch em emtoreg Op em Src Reg Shift left 2 Add reslt PC address Instrction memory Instrction [3 ] Instrction [25 2] Instrction [2 6] Instrction [5 ] register register 2 Registers 2 register Zero reslt Address Data memory Instrction [5 ] 6 Sign etend control Instrction [5 ]

37 Instrction Decode of add 2. Fetch the two operands and decode instrction: Fig Add Instrction [3 26] Control RegDst Branch em emtoreg Op em Src Reg Shift left 2 Add reslt PC address Instrction memory Instrction [3 ] Instrction [25 2] Instrction [2 6] Instrction [5 ] register register 2 Registers 2 register Zero reslt Address Data memory Instrction [5 ] 6 Sign etend control Instrction [5 ]

38 Operation dring add 3. R[rs] + R[rt] Fig Add Instrction [3 26] Control RegDst Branch em emtoreg Op em Src Reg Shift left 2 Add reslt PC address Instrction memory Instrction [3 ] Instrction [25 2] Instrction [2 6] Instrction [5 ] register register 2 Registers 2 register Zero reslt Address Data memory Instrction [5 ] 6 Sign etend control Instrction [5 ]

39 Back at the End of add 4. R[rd] <- ; PC <- PC + 4 Fig Add Instrction [3 26] Control RegDst Branch em emtoreg Op em Src Reg Shift left 2 Add reslt PC address Instrction memory Instrction [3 ] Instrction [25 2] Instrction [2 6] Instrction [5 ] register register 2 Registers 2 register Zero reslt Address Data memory Instrction [5 ] 6 Sign etend control Instrction [5 ]

40 Datapath Operation for lw R[rt] <- emory {R[rs] + SignEt[imm6]} Fig Add Instrction [3 26] Control RegDst Branch em emtoreg Op em Src Reg Shift left 2 Add reslt PC address Instrction memory Instrction [3 ] Instrction [25 2] Instrction [2 6] Instrction [5 ] register register 2 Registers 2 register Zero reslt Address Data memory Instrction [5 ] 6 Sign etend control Instrction [5 ]

41 Datapath Operation for beq if (R[rs]-R[rt]==) then Zero<- else Zero<- Fig. 5.2 if (Zero==) then PC=PC+4+signEt[imm6]*4; else PC = PC Add Instrction [3 26] Control RegDst Branch em emtoreg Op em Src Reg Shift left 2 Add reslt PC address Instrction memory Instrction [3 ] Instrction [25 2] Instrction [2 6] Instrction [5 ] register register 2 Registers 2 register Zero reslt Address Data memory Instrction [5 ] 6 Sign etend control Instrction [5 ]

42 Conclding Remarks (/2) Control Signals (Fig. 5.6) inst Register Transfer ADD R[rd] <- R[rs] + R[rt]; PC <- PC + 4 src = RegB, ctr = add, RegDst = rd, RegWr, PCsrc = +4 SUB R[rd] <- R[rs] - R[rt]; PC <- PC + 4 src = RegB, ctr = sb, RegDst = rd, RegWr, PCsrc = +4 LOAD R[rt] <- E[ R[rs] + sign_et(imm6)]; PC <- PC + 4 src = Im, ctr = add, emtoreg, RegDst = rt, RegWr, PCsrc= +4 STORE E[ R[rs] + sign_et(imm6)] <- R[rs];PC <- PC + 4 src = Im, ctr = add, emwr, PCsrc = +4 BEQ if (R[rs]==R[rt]) then PC<-PC+sign_et(Imm6)] else PC<-PC+4 PCsrc = Branch address, ctr = sb Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-42

43 Conclding Remarks (2/2) RegDst: =>rt; =>rd Reg: =>write dest. reg. src: =>regb; =>immed PCsrc: =>PC<-PC+4; =>PC<-branch addr. em: =>read memory em: =>write memory emtoreg: =>write reg. from ; =>write reg. from memory PC 4 address Instrction memory Add Instrction [3 ] Instrction [3 26] Instrction [25 2] Instrction [2 6] Instrction [5 ] Instrction [5 ] RegDst Branch em emtoreg Control Op em Src Reg register register 2 Registers 2 register Instrction [5 ] 6 Sign etend Shift left 2 control Add reslt Zero reslt Address PCSrc Data memory Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-43

44 Otline Designing a processor Bilding the path A single-cycle implementation Control for the single-cycle CPU Control of CPU operations controller ain controller Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-44

45 Or Plan for the Controller Op code 6 ain Control 7 fnc 6 op 2 Control (Local) ctr 3 R-type op rs rt rd shamt fnct 6 op is 2-bit wide to represent: I-type reqiring the to perform: () add for load/store and () sb for beq R-type (), need to reference fnc field R-type lw sw beq jmp op (Symbolic) R-type Add Add Sbtract op<:> Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-45

46 Step 5a: Implement Control Recall: design in Chapter 3 and fnc lw sw beq R R R R R ctr Operation AND OR add sb set-on-less-than fnct<5:> Instrction Operation add sbtract and or set-on-less-than op fnc ctr bit<> bit<> bit<5> bit<4> bit<3> bit<2>bit<> bit<> Operation bit<3> bit<2> bit<> bit<> Add Add Sbtract Add Sbtract And Or Set on < Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-46

47 Logic Eqation for ctr op fnc ctr bit<> bit<> bit<5>bit<4> bit<3> bit<2>bit<>bit<> bit<3> bit<2>bit<> bit<> Fig. 5.3 Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-47

48 Logic Eqation for ctr2 op fnc bit<> bit<> bit<5> bit<4> bit<3> bit<2> bit<> bit<> ctr<2> Fig. 5.3 This makes fnc<3> a don t care ctr2 = op + op fnc2 fnc fnc Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-48

49 Logic Eqation for ctr op fnc bit<> bit<> bit<5> bit<4> bit<3> bit<2> bit<> bit<> ctr<> Fig. 5.3 don t care ctr = op + op fnc2 fnc Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-49

50 Logic Eqation for ctr op fnc bit<> bit<> bit<5> bit<4> bit<3> bit<2> bit<> bit<> ctr<> Fig. 5.3 ctr = op fnc3 fnc2 fnc fnc + op fnc3 fnc2 fnc fnc See Fig. 5.3 for complete trth table Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-5

51 The Resltant Control Block Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-5

52 Otline Designing a processor Bilding the path A single-cycle implementation Control for the single-cycle CPU Control of CPU operations controller ain controller Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-52

53 Step 5b: Implement ain Control Logic eqation for each control signal: Branch: if (OP == BEQ) then else src : if (OP == (R-type)) then regb else immed op: if (OP == (R-type)) then fnct elseif (OP == BEQ) then sb else add emwr: (OP == SW) emtoreg: (OP == LW) RegWr: if ((OP == SW) (OP == BEQ)) then else RegDst: if (OP == LW) then else Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-53

54 Trth Table of Control Signals See fnc We Don t Care :-) Appendi A op add sb lw sw beq RegDst Src emtoreg Reg em em Branch op Op code 6 op ain Control RegDst Src : op 2 fnc 6 Control (Local) Fig ctr 4

55 Trth Table for Reg Op code R-type lw sw beq Reg Reg = R-type + lw = op5 op4 op3 op2 op op (R-type) + op5 op4 op3 op2 op op (lw) op<5>.. op<5>.. op<5>.. op<5>.. op<5>.. <> <> <> <> op<> R-type lw sw beq jmp Reg Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-55

56 PLA Implementing ain Control Inpts Op5 Op4 Op3 Op2 Op Op R-format Iw sw beq Otpts RegDst Src emtoreg Reg em em Branch Op Fig. C.2.5 OpO 5A-56

57 Ptting it Altogether (+ jmp instrction) Fig Instrction [25 ] Shift Jmp address [3 ] left Add PC+4 [3 28] Instrction [3 26] Control RegDst Jmp Branch em emtoreg Op em Src Reg Shift left 2 Add reslt PC address Instrction [3 ] Instrction memory Instrction [25 2] Instrction [2 6] Instrction [5 ] register register 2 Registers 2 register Zero reslt Address Data memory Instrction [5 ] 6 Sign etend control Instrction [5 ] Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-57

58 Clk PC Rs, Rt, Rd, Op, Fnc ctr Old Vale Worst Case Timing (Load) Clk-to-Q New Vale Instrction emoey Access Time Old Vale New Vale Delay throgh Control Logic Old Vale New Vale EtOp Old Vale New Vale Src Old Vale New Vale emtoreg Old Vale New Vale RegWr Old Vale New Vale bsa bsb Old Vale Delay throgh Etender & Old Vale Register Occrs Register File Access Time New Vale New Vale Delay Address Old Vale New Vale Data emory Access Time bsw Old Vale New

59 Drawback of Single-Cycle Design Long cycle time: Cycle time mst be long enogh for the load instrction: PC s Clock -to-q + Instrction emory Access Time + Register File Access Time + Delay (address calclation) + Data emory Access Time + Register File Setp Time + Clock Skew Fied clock cycle time Cycle time for load is mch longer than needed for all other instrctions (Significant penalty, Worst case design!!) Variable clock cycle time? Hard to implement Asynchronos design style? Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-59

60 Smmary Single cycle path => CPI=, Clock cycle time long 5 steps to design a processor:. Analyze ISA => path reqirements 2. Select set of path components 3. Assemble path meeting the reqirements 4. Analyze implementation of each instrction to determine setting of control points 5. Assemble the control logic IPS makes control easier Instrctions same size Sorce registers always in same place Immediates same size, location Operations always on registers/immediates Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A-6