Hardware Design Tips. Outline

Transcription

1 Hardware Design Tips EE 36 University of Hawaii EE 36 Fall 23 University of Hawaii Otline Verilog: some sbleties Simlators Test Benching Implementing the IPS Actally a simplified 6 bit version EE 36 Fall 23 University of Hawaii 2

2 onday Overview of verilog, again Implementing combinational circits sing verilog Rles to avoid problems EE 36 Fall 23 University of Hawaii 3 Verilog Basic modle Combinational sbcircits Seqential sbcircits (on wed) EE 36 Fall 23 University of Hawaii 4 2

3 Verilog: Basic odle modle circitname(y,y2,clock,reset,select,,2,3) otpt y,y2; inpt clock, reset; inpt select,, 2, 3; wire h,h2,h3; reg k,k2; otpts: only wire variables // Instantiations Circit circit(h,h2,clock,h3,5,k,k2); modle inpts: wire vars, reg variables, constants EE 36 Fall 23 University of Hawaii 5 Combinational Circits Continos assign Procedral always Rles Eamples of errors ore rles EE 36 Fall 23 University of Hawaii 6 3

4 Verilog: Combinational Sbcircits 2 3 Combinational sbcircit y Continos assign assign y = ; wire var Formla ( no begin- blocks, if-else, case statements, or anything else) EE 36 Fall 23 University of Hawaii 7 Verilog: Combinational Sbcircits Procedral always or 2 or or k) A description of how to compte otpts from the inpts Eample: or 2) y = ; Sensitivity List Rle of thmb: List of all inpts From this description yo shold be able to write a trth table for the circit Be sre the table is complete, i.e., it covers all possible inpts OR For all inpt vales, there shold be an otpt vale EE 36 Fall 23 University of Hawaii 8 4

5 Eample: missing an inpt in // 2: mltipleer the sensitivity list // 2: mltipleer modle m(y, sel, a, b) inpt a, b, sel; otpt y; always (a or b or sel) begin if (sel == ) y = a; else y = b; modle modle m(y, sel, a, b) inpt a, b, sel; otpt y; always (a or b) begin if (sel == ) y = a; else y = b; modle Case of missing an inpt ( sel ) in the sensitivity list. EE 36 Fall 23 University of Hawaii 9 Eample: otpts are not defined for all inpts // 2: mltipleer modle m(y, sel, a, b) inpt a, b, sel; otpt y; always (a or b or sel) begin if (sel == ) y = a; else y = b; modle // 2: mltipleer modle m(y, sel, a, b) inpt a, b, sel; otpt y; always (a or b or sel) begin if (sel == ) y = a; modle Case of not pdating y for all inpts Possible hardware implementation a It s a transparent D latch 2: m sel y EE 36 Fall 23 University of Hawaii 5

6 Comptation proceeds downwards (jst like C langage) Variables inpts:, 2, s otpt: y intermediate vale: h Net, we ll present some rles to se procedral always to model combinational circits Eample or 2 or s) begin if (s == ) h = ; else h = ; case(h) : y = 2; // AND the inpts : y = &2; // OR the inpts case Trth table for circit Inpt Otpt s 2 y EE 36 Fall 23 University of Hawaii Rles for procedral-always to model combinational circits Assignments y = ; reg variable Blocking assignment (we ll discss blocking and nonblocking assignments shortly) Note that the left hand side is always an otpt or intermediate variable EE 36 Fall 23 University of Hawaii 2 6

7 Rles for procedral-always to model combinational circits Update variables at most once or 2) begin y = + 2; if (y > 4) y = ; else y = 2; or 2) begin r = + 2; if (r > 4) y = ; else y = 2; y cold be pdated more than once BUT otpts sholdn t change twice when inpts change We introdced a new reg variable r. Now r and y are pdated at most once. EE 36 Fall 23 University of Hawaii 3 Rles for procedral-always to model combinational circits or 2) begin blocking assigments (e.g., y = +2;) if-else case statements modle... or 2) begin Circit circ(y,,2); This won t work. A modle is not modle a C fnction. modle Circit(h,g,g2) otpt h; inpt g, g2 assign h=g+g2; modle EE 36 Fall 23 University of Hawaii 4 7

8 Some rles to design combinational circits with always Sensitivity list shold have all inpts Otpts shold have vales for all possible inpts Variables that are pdated (left side of blocking assignments) shold be a register variable Update each variable at most once per change in inpt. odle instantiations are not C fnction calls Use blocking assignments, case, if-else, maybe others sch as for bt be carefl. EE 36 Fall 23 University of Hawaii 5 Wednesday Seqential circits with verilog Electronic Design Atomation (EDA) EE 36 Fall 23 University of Hawaii 6 8

9 Seqential Circits Procedral always Eamples Nonblocking and blocking assignments EE 36 Fall 23 University of Hawaii 7 Rles for procedral-always to model seqential circits 2 3 state clock y y2 clock) Update the state = state we ll assme this Eample: D flip flop clock) q <= d; Eample: T flip flop clock) if (t == ) q <= ~q; state vars are reg vars. nonblocking assignments EE 36 Fall 23 University of Hawaii 8 9

10 Nonblocking Assignments clock A B C D Q D Q D Q All flip flops get pdated together on a positive clock clock clock clock edge. clock) begin A <= ; B <= A; C <= B; All nonblocking assignments are pdated together on the positive edge of the clock. Eample A B C D Q D Q D Q A B C D Q D Q D Q clock clock clock clock clock clock clock clock After clock edge Before clock edge EE 36 Fall 23 University of Hawaii 9 Nonblocking Assignments A B C D Q D Q D Q clock clock clock clock Sppose initially (A,B,C) = (,,) begin A <= ; B <= A; C <= B; begin A = ; B = A; C = B; (A,B,C) = (,,) (A,B,C) = (,,) EE 36 Fall 23 University of Hawaii 2

11 Eample: 2-bit conter d[] d[] s[] s[] clock q[] q[] modle conter2(q,clock,s,d) ot [:] q; // 2-bit otpt in clock; s [:] s; // Select inpt in [:] d; // Parallel load inpt s = : reset q = s = : cont p s = 2: cont down s = 3: load reg [:] q; // This is or state variable clock) begin case (s) : q<=; : q<=q+; // Conting p. Note that the cont wraps arond // when it goes past the vale 3 2: q<=q-; // Conting down. Also has wrap arond 3: q<=d; // Parallel load case // Actally, the begin- is nnecessary modle EE 36 Fall 23 University of Hawaii 2 Eample: Lights s[] s[] clock y[3] y[2] y[] y[] modle Lights(y,clock,s,d) ot [3:] y; // 4-bit otpt in clock; s [:] s; // Select inpt in [:] d; // Parallel load inpt s = : reset y= s = : rotate right s = 2: rotate left s = 3: hold reg [:] q; // This is or state variable clock) begin case (s) : q<=; : q<=q+; // Conting p. Note that the cont wraps arond // when it goes past the vale 3 2: q<=q-; // Conting down. Also has wrap arond 3: q<=q; // Hold case // Actally, the begin- is nnecessary // Contined EE 36 Fall 23 University of Hawaii 22

12 Eample: Lights s[] s[] clock y[3] y[2] y[] y[] // Contined case (q) : y=4 b; : y=4 b; 2: y=4 b; 3: y=4 b; case modle s = : reset y= s = : rotate right s = 2: rotate left s = 3: hold EE 36 Fall 23 University of Hawaii 23 Electronic Design Atomation Simlator EDA process Test bench EE 36 Fall 23 University of Hawaii 24 2

13 Simlators, e.g., veriwell and odelsim Simlator will simlate what a circit will do over time. Time is divided into time nits (fictitios) bt yo can think of them as some small time dration, e.g.,.ns A variable keeps track of the crrent time (e.g., $time) Initially, crrent time = (or ) Update variable vales at time based pon vales at time Update variable vales at time 2 based pon vales at time and so on. EE 36 Fall 23 University of Hawaii 25 Eample $time = $time = new vale based on $time = 2 EE 36 Fall 23 University of Hawaii 26 3

14 Simlator verilog circit modle verilog testbench modle synthesizer project hardware simlator verify that yor circit works (debgging) EE 36 Fall 23 University of Hawaii 27 Test Bench Protoboard 5V Gnd IC Chip Clock Generator LEDs (probes) inpts to ecite the circit otpts to observe behavior EE 36 Fall 23 University of Hawaii 28 4

15 modle testbench; reg clock; reg [:] A; reg [2:] B; wire [2:] C; // Clock signal // Inpts A and B to ecite // Otpt C to observe icchip c(a,b,c,clock); // Instantiation of the circit to test init clock = ; // Clock generation, with clock period = 2 time nits always # clock = ~clock; init // Changing inpts to ecite icchip c begin: Inpt vales for testing A = ; B = ; #2 A = ; // After 2 time nits, A is changed to. # B = 3; // After another time nit, B changes to 3. #2 $stop; // After 2 more time nits, the simlation stops init // Display of otpts begin: Display $display("a B C clock time"); // Displayed once at $time = $monitor("%d %d %d %d %d",a,b,c,clock,$time); // Displayed whenever variable changes // Note that $monitor can occr at most once in verilog code // while $display can occr many times. modle EE 36 Fall 23 University of Hawaii 29 Friday Bilding single cycle IPS naive way IPS-L: 6 bit version of IPS Bild it in stages IPS-L: eectes only R-type instrctions Tips on testing and debgging IPS-L, L2, L3 EE 36 Fall 23 University of Hawaii 3 5

16 Bilding Single Cycle IPS How NOT to bild a single cycle IPS in verilog.. Bild all the components in verilog. 2. Test/debg each component 3. Pt everything together into the single cycle IPS 4. Simlate --> synta errors 5. Fi synta errors, and then simlate --> 6. Hmmm. aybe I m nlcky. Simlate again. 7. Hmmm. st be the simlator. Reset PC. Simlate again. 8. Problem too hard -- it s a complicated compter after all First three steps are okay. Bt need improvement after that. EE 36 Fall 23 University of Hawaii 3 IPS-L To eperience bilding a moderately large circit, yo will bild a IPS compter Homework A and B IPS-L: 6 bit version of IPS Description Simplified version IPS-L Only R-type arithmetic instrctions odified register file: RegFileL EE 36 Fall 23 University of Hawaii 32 6

17 IPS-L Description Instrctions (and integer ) are 6 bits long Word = 6 bits Addresses are 6 bits Eight general prpose registers $-$7 $ is always eqal to emory is byte-addressable and big Endian Addresses of words are divisible by 2 EE 36 Fall 23 University of Hawaii 33 IPS-L Register Convention Name $zero Register Nmber Usage the constant Preserved on call? n.a. $v-$v $t-$t vales for reslts and epression evalation temporaries No No $sp 6 stack pointer Yes $ra 7 retrn address No EE 36 Fall 23 University of Hawaii 34 7

18 IPS-L Instrction Formats Name Fields Comments Field Size 3 bits 3 bits 3 bits 3 bits 4 bits ALL IPS-L instrctions 6 bits R- format op rs rt rd fnct Arithmetic instrction format I- format op rs rt rd Address/ immediate Transfer, branch, immediate format J- format op target address Jmp instrction format EE 36 Fall 23 University of Hawaii 35 IPS-L achine Instrctions Name Format Eample Comments add R 3 bits 3 bits 2 3 bits 3 3 bits 4 bits add $,$2,$3 sb R 2 3 sb $,$2,$3 and R and $,$2,$3 or R or $,$2,$3 slt jr R R slt $,$2,$3 jr $7 lw I 4 2 lw $,($2) sw I 5 2 sw $,($2) beq I 6 2 (offset to )/2 beq $,$, addi j I J addi $,$2, j jal J 3 5 jal EE 36 Fall 23 University of Hawaii 36 8

19 Single Cycle IPS-L Instrction [25 ] Shift Jmp address [3 ] left PC+4 [3 28] Add reslt 4 Add RegDst Jmp Branch Shift left 2 Instrction [3 26] Control em emtoreg Op em Src Reg PC address Instrction [3 ] Instrction memory This thing s got a cycle in it. Not good. Bild it in stages Instrction [25 2] Instrction [2 6] Instrction [5 ] Instrction [5 ] register register 2 Registers register Instrction [5 ] EE 36 Fall 23 University of Hawaii Sign et control Zero reslt Address Data memory The following is JUST A SUGGESTION IPS-L Something even simpler: IPS-L Only eectes R format arithmetic instrctions Register File RegFileL Register $5 = always Register $4 = 2 always Control: Same as IPS-L EE 36 Fall 23 University of Hawaii 38 9

20 IPS-L Instrction emory (RO) iaddr i IPS-L alot alina alinb reset clock Used to verify correctness Everything is 6 bits ecept reset and clock EE 36 Fall 23 University of Hawaii 39 IPS-L Describe IPS-L Eample Program emory Eample testbench General testbench of simple combination circits Bilding Single Cycle IPS-L Pre IPS-L, yet even simpler Debgging tips Bilding Single Cycle IPS-L EE 36 Fall 23 University of Hawaii 4 2

21 reset clock IPS-L iaddr i (instrction) PC + 4 Reg= r2 r3 r RegFileL alina alot alinb Op=2 Control EE 36 Fall 23 University of Hawaii 4 Eample Instrction emory // Instrction memory // Program has only 8 instrctions modle I(addr, dot) inpt [5:] addr; dot [5:] dot; reg [5:] dot; case (addr[3:]) : dot = {3 d,3 d4,3 d5,3 d3,4 d} // add $3,$4,$5 : dot = // sb $2,$4,$5 2: dot = // slt $,$4,$5 3: dot = // and $,$3,$5 4: dot = // slt $,$4,$3 5: dot = // sb $,$3,$5 6: dot = // add $3,$,$2 7: dot = // add $3,$5,$ case modle EE 36 Fall 23 University of Hawaii 42 2

22 Eample Testbench // Testbench for program memory modle testbench_memory reg [5:] addr; wire [5:] dot; I pmem(addr, dot); // Instantiation of memory initial begin // Drive the memory addr = ; #2 addr = 2; #2 addr = 4;... #2 addr = 4; #2 $stop; initial begin // Display the otpts $monitor( time = %d, addr=%d, instr=(%d,%d,%d,%d,%d),$time,addr,dot[5:3],... modle EE 36 Fall 23 University of Hawaii 43 Simple Testbenches Declare reg variables to drive inpts Declare wire variables to tap into otpts and connect circits Clock generator signal (if necessary) Set p circit with instantiations and possible connections Initial procedre to change inpt signals over time (se delays # and $stop) Initial procedre to otpt reslts EE 36 Fall 23 University of Hawaii 44 22

23 Bilding IPS-L Bild the components and test Instrction memory Control Register file RegFileL Bild and test a Pre-IPS-L (see net slide) Bild and test a IPS-L (finally!) EE 36 Fall 23 University of Hawaii 45 reset clock Pre IPS-L iaddr i (instrction) PC is an arbitrary nmber 9 Reg= r2 r3 r RegFileL Op=2 Control alina alot alinb We got rid of the cycle EE 36 Fall 23 University of Hawaii 46 23

24 Pre IPS-L What do we gain by removing the cycle? If there s a bg, we can find it by tracing backwards Testbench Has an instantiation of IPS-LO and program memory Try different programs for testing EE 36 Fall 23 University of Hawaii 47 Pre IPS-L Rles of thmb for debgging Determine a set of inpt signals to test whether the circit works or not Inpt signals will vary over time Determine where to probe signals At otpts At intermediate points Determine by hand what signals to epect EE 36 Fall 23 University of Hawaii 48 24

25 Pre IPS-L Rles of thmb for debgging Create test bench that generates the appropriate inpt signals over time otpts the signals yo want Rn the test bench and see if the circit works If not, pt probe signals pstream to determine where the problem is EE 36 Fall 23 University of Hawaii 49 Probing Upstream probe This is spposed to be. Check pstream ntil yo find a device that isn t working, e.g., otpts don t match inpts EE 36 Fall 23 University of Hawaii 5 25

26 Pre IPS-L Rles of thmb for debgging Change inpt signals to REALLY verify that the circit will work nder all conditions Eample: change program EE 36 Fall 23 University of Hawaii 5 IPS-L After verifying correctness of Pre IPS- LO, bild and test IPS-L This is Homework A EE 36 Fall 23 University of Hawaii 52 26

27 IPS-L Bild the IPS-L in stages Stage IPS-L Inclde addi and j Use ordinary register file Inclde Control circit Stage 2 IPS-L2: inclde beq odify for zero otpt EE 36 Fall 23 University of Hawaii 53 IPS-L Stage 3 IPS-L3 (final) Inclde lw and sw Have the RA store 28 words. RA is implemented like a register file Have the program read and write to RA and check if it does so properly Verification can be done by checking inpts and otpts This is Homework B EE 36 Fall 23 University of Hawaii 54 27

28 Testbenching Yor testbench shold inclde Yor IPS-L Program memory Don t be afraid to try different programs for testing Last slide nless there s more time EE 36 Fall 23 University of Hawaii 55 Single Cycle IPS Instrction [25 ] Shift Jmp address [3 ] left PC+4 [3 28] Add reslt 4 Add Instrction [3 26] Control RegDst Jmp Branch em emtoreg Op em Src Reg Shift left 2 set these mltipleers so that PC=PC+4 PC address Instrction [3 ] Instrction memory Instrction [25 2] Instrction [2 6] Instrction [5 ] register Instrction [5 ] Bild this first. Yor program shold have R-type, lw, sw, and j instrctions only register 2 Registers register Instrction [5 ] EE 36 Fall 23 University of Hawaii Sign et control Zero reslt Address Data memory 28

29 Single Cycle IPS Instrction [25 ] Shift Jmp address [3 ] left PC+4 [3 28] Add reslt 4 Add Instrction [3 26] Control RegDst Jmp Branch em emtoreg Op em Src Reg Shift left 2 set these mltipleers so that PC=PC+4 PC address Instrction [3 ] Instrction memory Instrction [25 2] Instrction [2 6] Instrction [5 ] register register 2 Registers register 2 Zero reslt Address Data memory Check controller otpts Instrction [5 ] 6 32 Sign et Instrction [5 ] control EE 36 Fall 23 University of Hawaii 57 Single Cycle IPS Instrction [25 ] Shift Jmp address [3 ] left PC+4 [3 28] Add reslt 4 Add RegDst Jmp Branch Shift left 2 Instrction [3 26] Control em emtoreg Op em Src Reg Reg= while testing at this stage PC address Instrction [3 ] Instrction memory Instrction [25 2] Instrction [2 6] Instrction [5 ] register register 2 Registers register 2 Zero reslt Address Data memory Instrction [5 ] 6 32 Sign et Check register control Instrction [5 ] file otpts. Yo mst initialize register vales somehow EE 36 Fall 23 University of Hawaii 58 29

30 Single Cycle IPS Instrction [25 ] Shift Jmp address [3 ] left PC+4 [3 28] Add reslt 4 Add RegDst Jmp Branch Shift left 2 PC address Instrction [3 ] Instrction memory Instrction [3 26] Instrction [25 2] Instrction [2 6] Instrction [5 ] Control em emtoreg Op em Src Reg register register 2 Registers register 2 Reg= and em = while testing at this stage Zero reslt Address Data memory Instrction [5 ] Complete path bt not writing to anything Instrction [5 ] 6 32 Sign et EE 36 Fall 23 University of Hawaii 59 control Single Cycle IPS Instrction [25 ] Shift Jmp address [3 ] left PC+4 [3 28] Add reslt 4 Add RegDst Jmp Branch Shift left 2 Instrction [3 26] Control em emtoreg Op PC address Instrction [3 ] Instrction memory Instrction [25 2] Instrction [2 6] Instrction [5 ] em Src Reg register register 2 Registers register 2 em = while testing at this stage Zero reslt Address Data memory Program jst has R-type and j instrctions Instrction [5 ] Instrction [5 ] 6 32 Sign et EE 36 Fall 23 University of Hawaii 6 control 3

31 Single Cycle IPS Instrction [25 ] Shift Jmp address [3 ] left PC+4 [3 28] Add reslt 4 Add RegDst Jmp Branch Shift left 2 Instrction [3 26] Control em emtoreg Op em Src Reg PC address Instrction [3 ] Instrction memory Instrction [25 2] Instrction [2 6] Instrction [5 ] register register 2 Registers register 2 Zero reslt Address Data memory Instrction [5 ] 6 32 Sign et control Instrction [5 ] EE 36 Fall 23 University of Hawaii 6 3