Exceptions and interrupts

Transcription

1 Eceptions and interrpts An eception or interrpt is an nepected event that reqires the CPU to pase or stop the crrent program. Eception handling is the hardware analog of error handling in software. Classes don t often talk abot errors, so it s easy to forget them. Proper error handling is very important in real systems, and a lot of effort is often devoted to error checking and recovery. We ll find that eception handling reqires spport from both hardware and software (the operating system) sides. April 7, Howard Hang

2 Eception handling Eceptions are typically errors that occr within the processor. The CPU tries to eecte an illegal instrction opcode. An arithmetic instrction overflows, or attempts to divide by. There are two possible ways of resolving these errors. The operating system can force a program with a serios error to qit. Smaller errors may case an error message to be sent to the program. odern langages like Java allow programmers to catch eceptions so applications can deal with errors more graceflly. April 7, 23 Eceptions and interrpts 2

3 Interrpt handling Interrpts are eternal errors that reqire the processor s attention. The ser presses the machine s sleep or reset bttons. Peripherals and other I/O devices may need attention. The virtal memory system needs to access the hard disk to complete a lw or sw instrction. These sitations are not really errors. They happen normally. (We ll talk abot memory and I/O later on.) The interrpted program sally needs to resme eection after the interrpt is handled. It is the operating system s responsibility to do the right thing, sch as: Save the crrent state and sht down the hardware devices. Find and load the correct from the hard disk Transfer to/from the I/O device, or install drivers. April 7, 23 Eceptions and interrpts 3

4 The hardware/software interface again The most niform approach is to have the operating system handle both eceptions and interrpts. The operating system code contains an eception handler, which decides how eceptions and interrpts shold be processed. The eception handler needs to know two things. The case of the eception (e.g., overflow or page falt). What instrction was eecting when the eception occrred. This helps the operating system report the error or resme the program. This is another eample of interaction between software and hardware, as the case and crrent instrction mst be spplied to the operating system by the processor. April 7, 23 Eceptions and interrpts 4

5 The CPU s basic responsibility The CPU first stores the relevant information for the operating system. The eception is stored in a special Case register. The instrction that was eecting when the eception occrred is stored in the EPC (eception program conter) register. Then the processor transfers control to the operating system by placing the eception handler s address into the PC. We ll look at how this might work in or mlticycle path, and then also point ot some isses with a pipelined path. April 7, 23 Eceptions and interrpts 5

6 The original mlticycle path PC PC IorD ALUSrcA em Address emory em em Data IR [3-26] [25-2] [2-6] [5-] [5-] RegDst register register 2 register Reg 2 Registers A B ALU Zero Reslt ALUOp ALU Ot PCSorce Instrction register emory register Sign etend Shift left 2 ALUSrcB emtoreg April 7, 23 Eceptions and interrpts 6

7 Eceptions for or mlticycle CPU There are only two possible eceptions in or simple processor. An illegal instrction can be detected by the control nit when it tries to decode the instrction word. We can modify the ALU to generate an overflow signal for arithmetic overflows. The control nit then checks the overflow signal and cases an eception if needed. If an eception occrs, the control nit needs to do several things.. Store the crrent PC in the EPC register (the diagram on the following page actally stores PC + 4 for simplicity). 2. Store the eception case in the Case register. We ll say illegal instrctions are Case =. Overflows will be represented by Case =. 3. Finally, set the PC to the address of the operating system s interrpt handler. This address mst be known by the CPU; we ll assme it s at memory location C in headecimal. April 7, 23 Eceptions and interrpts 7

8 lticycle path with eceptions PC EPC Case PC IorD EPC Case Case Control ALUSrcA em Address emory em em Data IR [3-26] [25-2] [2-6] [5-] [5-] RegDst register register 2 register Reg 2 Registers A B ALU Reslt Zero Overflow ALUOp ALU Ot C 2 PCSorce Instrction register emory register Sign etend Shift left 2 ALUSrcB emtoreg April 7, 23 Eceptions and interrpts 8

9 lticycle control nit changes Instrction fetch and PC increment IorD = em = IR = ALUSrcA = ALUSrcB = ALUOp = PCSorce = PC = Register fetch and branch comptation ALUSrcA = ALUSrcB = ALUOp = Op = BEQ ALUSrcA = ALUSrcB = ALUOp = PCSorce = PC = Zero Branch completion Overflow Overflow eception Case = Case = EPC = PCSorce = PC = Op = nknown Op = R-type ALUSrcA = ALUSrcB = ALUOp = fnc R-type eection RegDst = emtoreg = Reg = R-type writeback Illegal instrction Case = eception Case = EPC = PCSorce = PC = Op = LW/SW Effective address comptation ALUSrcA = ALUSrcB = ALUOp = Op = SW Op = LW emory write IorD = em = IorD = em = emory read lw register RegDst = write emtoreg = Reg = April 7, 23 Eceptions and interrpts 9

10 When to interrpt the processor An arithmetic instrction will pdate its destination register even if an overflow occrs, becase the R-type writeback step occrs before the overflow eception step. This may not always be what is desired. For eample, if the overflowed instrction was add $t, $t, $t2 Op = R-type ALUSrcA = ALUSrcB = ALUOp = fnc R-type eection Case = Case = EPC = PCSorce = PC = Overflow RegDst = emtoreg = Reg = Overflow eception R-type writeback the writeback stage wold overwrite the original vale of $t before the eception occrs, possibly making debgging mch harder. April 7, 23 Eceptions and interrpts

11 Other kinds of eceptions Eceptions can occr in different instrction eection stages, depending on the actal instrction set architectre and path design. For eample, a virtal memory page falt might be raised dring the instrction fetch or memory stages. Eternal interrpts can also arrive at any time. Eception handling is a major challenge in CPU design. Handling all of the possible eceptions can reslt in a very large state diagram and a very comple control nit. Remember that yo have to be carefl not to make the control nit too complicated, or cycle times will increase. As an analogy, error handling in programs sally yields longer and more comple code. April 7, 23 Eceptions and interrpts

12 Or pipelined path ID/EX PCSrc Control WB EX/E WB E/WB 4 IF/ID EX WB Add P C Reg Shift left 2 Add address Instrction [3-] register register 2 2 ALU Zero Reslt em Address Instrction memory register Registers ALUSrc ALUOp Data memory emtoreg Instr [5 - ] Instr [2-6] Instr [5 - ] Sign etend RegDst em April 7, 23 Eceptions and interrpts 2

13 Pipelining and eceptions In a pipelined design, eceptions are another form of control hazard jst like branches, they alter the normal program flow so it s not always clear what the net instrction shold be. Handling eceptions is mch more difficlt with pipelining, since there are several instrctions eecting at once. The control nit has to determine which of the several instrctions in the pipeline cased the eception. It s also possible for mltiple eceptions to occr in the same cycle! For eample, an instrction in its EX stage cold overflow at the same time another instrction cases an illegal opcode eception. April 7, 23 Eceptions and interrpts 3

14 Precise eceptions Deciding where to interrpt or stop the pipeline is also difficlt. Ideally, a processor wold implement precise eceptions. All instrctions before the offending one shold complete eection. The CPU shold stop on the ecepting instrction, storing its address in the EPC register. Instrctions after that one shold not be eected. In a pipelined CPU, this means that the control nit mst ensre some of the instrctions in the pipeline complete, while others are flshed. Again this can lead to very comple control. Flshing for eceptions can limit the performance of deep pipelines, jst like flshing for branches. If an instrction in stage 7 cases an eception, then the following 6 instrctions are flshed and might need to be re-eected. Precise eceptions are not difficlt to implement in a single or mlticycle path, since there is only one instrction active in any given cycle. April 7, 23 Eceptions and interrpts 4

15 Smmary Eceptions and interrpts are different hardware events that force the CPU to either pase or stop the rnning program. The operating system and processor work together to handle eceptions. The OS provides an eception handler to process the errors. The processor records and passes the eception program conter and eception case to the operating system. Handling all possible eceptions and interrpts can lead to comple and slow control nits and processors. Eception handling presents special challenges for pipelined paths. ltiple eceptions can occr simltaneosly, so spporting precise eceptions is difficlt. Complicated control nits and ecessive flshing can redce the CPU performance. April 7, 23 Eceptions and interrpts 5