Review. A single-cycle MIPS processor

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1 Review If three instrctions have opcodes, 7 and 5 are they all of the same type? If we were to add an instrction to IPS of the form OD $t, $t2, $t3, which performs $t = $t2 OD $t3, what wold be its opcode? How can yo tell if the immediate field is positive or negative? Cold the distance J jmps be increased by sing an opcode of fewer bits? A single-cycle IPS processor An instrction set architectre is an interface that defines the hardware operations available to software Any instrction set can be implemented in many different ways. Over the net few weeks we ll see several possibilities In a basic single-cycle implementation all operations take the same amont of time a single cycle A mlticycle implementation allows faster operations to take less time than slower ones, so overall performance can be increased Finally, pipelining lets a processor overlap the eection of several instrctions, potentially leading to big performance gains 2

2 Single-cycle implementation We describe the implementation of a simple IPS-based instrction set spporting jst the following operations Arithmetic: add sb and or slt Transfer: lw sw Control: beq Today we ll bild a single-cycle implementation of this instrction set All instrctions will eecte in the same amont of time; this will determine the clock cycle time for or performance eqations We ll eplain the path first, and then make the control nit 3 Compters are state machines A compter is jst a big fancy state machine.,, hard disks and other storage form the state The processor keeps reading and pdating the state, according to the instrctions in some program CPU State 4 2

3 John von Nemann In ancient times, programming involved actally changing a machine s physical configration by flipping switches or connecting wires A compter cold rn jst one program at a time emory only stored that was being operated on Then arond 944 Atanasoff, Eckert and achley (and others) got the idea to encode instrctions in a format that cold be stored in jst like The processor interprets and eectes instrctions from One machine cold perform many different tasks, jst by loading different programs into John von Nemann wrote the first eplanation of their idea, so the stored program design is often called a Von Nemann machine 5 emories It s easier to se a Harvard architectre at first, with programs and stored in separate memories To fetch instrctions and read & write words, we need these memories to be 32-bits wide (bses are represented by dark lines here). We still want byte ability, so these are memories Instrction [3-] Instrction em em 6 3

4 ore emories Ble lines represent control signals em and em shold be set to if the is to be read or written respectively, and otherwise When a control signal does something when it is set to, we call it active high (vs. active low) becase is sally a higher voltage than For now, we will assme yo cannot write to the instrction Pretend it s already loaded with a program, which doesn t change while it s rnning Instrction [3-] Instrction em em 7 Instrction fetching The CPU is always in an infinite loop, fetching instrctions from and eecting them The program conter or PC holds the of the crrent instrction IPS instrctions are each for bytes long, so the PC shold be incremented by for to read the net instrction in seqence PC Instrction [3-] Instrction 4 Add 8 4

5 Start With R-type instrctions Last lectre, we saw encodings of IPS instrctions as 32-bit vales Register-to- arithmetic instrctions se the R- type format op is the instrction opcode, and fnc specifies a particlar arithmetic operation rs, rt and rd are sorce and destination s op rs rt rd shamt fnc 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits An eample instrction and its encoding: add$s4, $t, $t2 9 and s R-type instrctions mst access s and an The file stores thirty-two 32-bit vales Each specifier is 5 bits long Yo can read from two s at a time Reg is if a shold be written 2 Reg 2 5

6 and s R-type instrctions mst access s and an The file stores thirty-two 32-bit vales Each specifier is 5 bits long Yo can read from two s at a time Reg is if a shold be written Here s a simple with five operations, selected by a 3-bit control signal Fnction and or add sbtract slt 2 Reg 2 Eecting an R-type instrction. an instrction from the instrction 2.The sorce s, specified by instrction fields rs and rt, shold be read from the file 3.The performs the desired operation 4.Its reslt is stored in the destination, which is specified by field rd of the instrction word Reg Instrction [3-] Instrction I [25-2] I [2-6] I [5 - ] 2 2 Reslt op rs rt rd shamt fnc

7 Encoding I-type instrctions The lw, sw and beq instrctions are all I-type encoding rt is the destination for lw, bt a sorce for beq and sw is a 6-bit signed constant op rs rt 6 bits 5 bits 5 bits 6 bits Two eample instrctions: lw $t, 4($sp) sw $a, 6($sp) 3 Accessing For lw $t, 4($sp), the base $sp is added to a sign-etended constant to get a So the mst accept either a operand for arithmetic instrctions, or a sign-etended immediate operand for lw and sw. We ll add a mltipleer, controlled by Src, to select either a operand () or a constant operand () Instrction Instrction [3-] I [25-2] I [2-6] I [5 - ] I [5 - ] 2 Reg 2 Sign etend Src Reslt em em emtoreg 4 7

8 emtoreg The file s inpt has a similar problem. It mst be able to store either the otpt of R-type instrctions, or the otpt for lw We add a m, controlled by emtoreg, to select between saving the reslt () or the otpt () to the s Instrction Instrction [3-] I [25-2] I [2-6] I [5 - ] I [5 - ] 2 Reg 2 Sign etend Src Reslt em em emtoreg 5 A final annoyance is the destination of lw is in rt instead of rd We add one more m, controlled by, to select the destination from either the rt () or rd () Instrction Instrction [3-] op rs rt I [25-2] I [2-6] I [5 - ] I [5 - ] 2 lw $rt, ($rs) Reg 2 Sign etend Src Reslt em em emtoreg 6 8

9 Branches For branch instrctions, the constant is not an bt an instrction offset from the crrent program conter to the desired. beq $at, $, L add $v, $v, $ add $v, $v, $v j Somewhere L: add $v, $v, $v The target L is three instrctions past the beq, so the encoding of the branch instrction has for the field. op rs rt Instrctions are for bytes long, so the actal offset is 2 bytes. 7 The steps in eecting a beq. Fetch the instrction, like beq $at, $, offset, from 2. the sorce s, $at and $, from the file 3. Compare the vales by sbtracting them in the 4. If the sbtraction reslt is, the sorce operands were eqal and the PC shold be loaded with the target, PC (offset 4) 5. Otherwise the branch shold not be taken, and the PC shold jst be incremented to PC + 4 to fetch the net instrction seqentially 8 9

10 Branching hardware We need a second adder, since the is already doing sbtraction for the beq. PC Instrction Instrction [3-] 4 I [25-2] I [2-6] I [5 - ] I [5 - ] Add ltiply constant by 4 to get offset. 2 Reg 2 Sign etend Shift left 2 Src Add Reslt PCSrc PCSrc= branches to PC+4+(offset 4). PCSrc= contines to PC+4. em em emtoreg 9 The final path PC 4 Add Reg Shift left 2 Add PCSrc Instrction Instrction [3-] I [25-2] I [2-6] I [5 - ] 2 2 Src Reslt em em emtoreg I [5 - ] Sign etend 2