PIC Microcontroller. PIC Microcontroller (MCU) Typical Applications. PIC Families

Transcription

1 (MCU) PIC Microcontroller Widely used device from Microchip Technology Sold > billion PIC controllers Several device families Many devices per family Common development environment Widely available Large user base Extensive application notes Low cost Free / low cost development tools Basic architectural features Pipelined RISC microprocessor core ccumulator execution model ata width 8 / 6 / bits Instruction width / / 6 / bits PIC Families Typical pplications rchitecture 8 bit MCU 6 bit MCU bit MCU PIC / PIC / PIC6 PIC8 PIC dspic Family Baseline Mid Range Integrated SP ata Width 8 bits 6 bits bits Instruction Width bits bits 6 bits 6 bits bits ata width 8 / 6/ bits Wider integer higher precision arithmetic Instruction width / / 6 / bits Wider instruction more complex instructions + higher precision arithmetic Baseline Replace discrete logic functions Gates, simple state machines, encoders/decoders, etc. isposable electronics rug / pregnancy testers, dialysis monitor, etc Mid-Range igital sensors, displays, controllers, telecom equipment Glucose / blood pressure set PIC8 Integration with peripherals + networks USB, Ethernet, MCU-to-MCU, etc Higher level analog peripherals, industrial control, major appliances PIC / dspic 6-bit LU with integrated SP Portable EGK PIC General purpose RISC microprocessor + controller MRI

2 5 Learning PIC rchitecture Some general observations Variety Hundreds of PIC devices in families and several sub-families Updates Microchip Technology upgrades devices frequently Familiar devices replaced with new model Instruction Set rchitecture 8 and 6 bit devices share approximately uniform instruction set PIC implements MIPS IS Caveats Course takes general pedagogical approach to PIC as typical MCU Focus on 8-bit devices Mid-Range + PIC8 Many books + websites on PIC with general-sounding titles Each device is unique Few statements are precisely true about each device 8 Bit PIC MCUs ata memory Program memory rchitecture Stack I/O devices Organized as 8 bit registers Some devices also store data on EEPROM 6 B to KB ddressable unit = instruction word = / / 6 bits Smallest: Kword ( KB of bit instructions) Largest: 6 Kword (8 KB of 6 bit instructions) Pipelined RISC to 77 instructions Stores (no stack) to instruction addresses Used for function calls 8 bit parallel ports Synchronous / asynchronous serial ports Timers + watchdog timer / + / converters Pulse width modulators 6 8 Bit PIC Operation Model LU sources Special WORKING register W ata register or immediate LU destination ata register or W Transfer operations ata register W Status register Flags produced by LU operations ata Bus Status ata Memory rithmetic Logic Unit (LU) W Pipeline Operation Instruction cycles (CY) Instruction Fetch Instruction Memory Execute ecode ddress Instruction ddress ata Instruction Cycles ata Memory 5 I fetch execute I fetch execute I fetch execute I fetch execute Branch instructions require instruction cycles W 7 8

3 9 Pipeline Operation Clock cycles (OSC) Instruction Cycle cycles of external clock (oscillator) CY = Q Q Q Q Instruction fetch Execution Q Q Q Q Q Q Instruction Cycles Update Program Pointer Fetch ecode and Execute PC PC + IR [PC] Operation dependent 5 QQQQ QQQQ QQQQ QQQQ QQQQ I fetch execute I fetch execute I fetch execute I fetch execute IR instruction register PC program counter Clock Types RC oscillator Least expensive Can be used for non-critical frequency accuracy and stability Some devices have internal RC oscillator at MHz Crystal oscillator Most stable External clock Provided by external digital system Specific modes LP mode frequencies between khz and khz XT mode frequencies between khz and MHz HS mode frequencies between 8 MHz and MHz Sleep Mode Low-power mode Main oscillator stopped Most MCU functions stopped Watchdog time continues Power consumed < m for some models Instruction SLEEP MCU sleep mode ata register values stable Pipeline locked Sleep instruction executes next instruction already fetched On wake up Next instruction executes Recommendation instruction after sleep = NOP Watchdog timer counter reset Wake Up Events Reset Fetch instruction from address Watchdog timer overflow Normal execution of instruction following sleep Interrupt Interrupt not enabled ignore interrupt Enabled Normal execution of instruction following sleep PC jumps to address in program memory Finds interrupt routine

4 Watchdog Timer Some Typical 8 bit PIC evice Families WT oscillator (clock) Independent from main clock Continues in low power mode May be disabled WT timeout Timeout = 8 ms Non-sleep mode MCU resets Sleep mode MCU wakes up executes instruction following sleep Reset WT CLRWT resets timeout = 8 ms Prescaler ivide time-base by k, k =,..., 7 Extend timeout up to ms Instruction word Instructions Program memory ROM ata memory (bytes) Interrupts Pins I/O pins Stack Timers Bulk price PICFxx bits 56 5 words Flash 6 6 levels $.5 PICF5xx bits 5 words Flash levels $.5 PIC6F5xx bits 8 words Flash 5 levels $.5 $.85 PICFxx PICF6xx PIC6F6xx bits words Flash int / ext levels $.5 $.5 PIC8F5xx 6 bits 8 Kwords 6 Kwords Flash 56 K int / ext levels 5 $. $8.5 Typical Baseline MCU PIC6X5xx Family Typical Mid Range MCU PIC6F87 8 bit data 8 bit data bit instruction bit instruction General I/O ports timer W+ LU Timers / URT Compare Capture Pulsewidth (CCP) Synchronous Serial Port (SSP) General I/O ports External Interrupt 5 6

5 7 Typical PIC8 MCU 8 bit data 6 bit instruction Mid Range PIC MCUs Timers / URT USB Compare Capture Pulsewidth (CCP) Controller rea Network (CN) General I/O ports External Interrupts 8 ata Memory / Registers Special / General Registers Register ddressable location in data memory 8-bit word (byte) GPR General Purpose Registers User program data STTUS OPTION Typical SFRs Status word + flags Timer options ata address space 9 bit address memory 9 = 5 bytes =.5 KB Memory partitioned into banks Bank = 7 = 8 = 8h registers (/8 KB) 7 bit file address isplacement in bank = h 7Fh Banks in address space 9-7 = banks to banks implemented in device Unimplemented banks Read as Write as NOP bits bank 7Fh h data address 7 bits file address bank SFR Special Function Registers Reserved for Control / configuration Peripheral access Indirect addressing Program counter Core SFRs ppear in every bank at same file address PCLTH PCL FSR INTCON, PIR, PIE, PIR, PIE PORT, TRIS, TMR, OPTION, INTCON, TXREG, TXST, RCREG, RCST, RESH, RESL, CON, EERH, EET, Components of program counter (PC) File Select for indirect data addressing Components of interrupt handling ccess to parallel ports Timer ccess to serial port ccess to / converter ccess to EEPROM and Flash memory 9

6 ata Memory Map Notes (,) Not all locations implemented on all devices () Common RM accessible in all banks (on applicable devices) (5) Not implemented on smaller devices Status Register Core SFR accessible at file address h in every bank Name Writable Reset value IRP RP, RP TO# P# C C 7 IRP R/W Bank Select State of WT Low power ero flag 6 RP R/W Half byte carry (bits,) Carry out 5 RP R/W T# RO irect Register Pointer P# RO Indirect Register Pointer on LU zero on non zero C on carry (ddition) C on borrow (Subtraction) R/W C on carry (ddition) C on borrow (Subtraction) x C R/W TO# on WT overflow TO# on power on reset, CLRWT, SLEEP P# on SLEEP P# on CLRWT and power on reset x C R/W x ddressing ata Memory ddressing ata Memory REG<b> REG<a:b>.B Notation Bit b in register REG Bits a to b in register REG Concatenation of and B ( bits followed by B bits) irect addressing Program specifies data address Bank selection 8 STTUS bits RP and RP On reset RP = RP = bank selected Bank switching Write to STTUS<6:5> File ddress Literal field in instruction RP bank RP 7 7 bits from instruction file address 6 5 Indirect addressing Program writes to Special Function Registers (SFRs) ddress formed from SFRs Instructions can increment/decrement SFR values Similar to pointer arithmetic File Select Register (FSR) Core SFR accessible at file address 8h in all banks File ddress IRP FSR<6:> bank Bank IRP.FSR<7> STTUS bit IRP (Indirect Register Pointer) On small devices or banks = 8 or 56 bytes of data memory 8 bit FSR address covers banks IRP not implemented (read / write = NOP) 8 bits of FSR file address 5

7 5 INF Register INF Core SFR accessible at file address h in all banks Virtual pointer not physical register Tracks contents of FSR Simplifies pointer arithmetic Example In register file, [5] = h [6] = h Load FSR 5 ; FSR points to file address 5 [INF] = h ; INF points to file address 5 FSR++ ; increment FSR FSR = 6 [INF] = h ; INF points to file address 6 Instruction Memory Space ll 8 bit MCUs Instruction address n bit location address Location = instruction n instructions Instruction width / / 6 bits Page Partition of instruction memory space k instructions / page k bit offset n k bits page n bit address k bits offset Page Page Page instruction instruction instruction instruction instruction instruction instruction instruction instruction instruction instruction instruction Memory page offset Location ddress 6 Instruction Memory Space Mid-Range instruction memory -bit instruction word n = = 89 instruction words k = Page = = 8 = 8h words Program counter (PC) PC<:> = page number pages PC<:> = offset Reserved addresses ddress h Reset vector pointer to reset routine ddress h bits page Interrupt vector pointer to interrupt service routine bit PC bits offset PC ccess PC register details PC low (PCL) = PC<7:> ccessible by instruction reads/writes PC high (PCH) = PC<:8> Not directly accessible to instructions PC latch high (PCLTH) Core SFR accessible at file address h in all banks PCH = PC<:8> = PCLTH<:> PCLTH<7:5> not implemented PC page PCH offset PCLTH PCL 7 8

8 9 PC Updates Reset PC Non-branch instruction PC PC + literal Branch types irect branch PCLTH GOTO instruction PCH<:> PCLTH<:> Offset = PC<:> literal<:> from instruction Indirect branch Computed GOTO Write to PCL as register Copies PCL LU result Forces PCH PCLTH<:> page PCH offset PC PCLTH PC PCH PC PCLTH PCL PCL LU<7:> Call / Return Stack 8 level FILO buffer Holds bit instruction addresses on CLL/RETURN STCK CLL RETURN literal Function entry CLL instruction STCK PC<:> PCL literal<:> from instruction PCH<:> PCLTH<:> Function exit RETURN instruction PC<:> STCK PCLTH not updated May be different from PCH after RETURN PC PCLTH 5 Instruction Format opcode opcode opcode d opcode b f k k f Byte oriented d = destination = W d = destination = f f = 7 bit file address Bit oriented b = bit position in register f = 7 bit file address General literal k = 8 bit literal (immediate) CLL / GOTO k = bit literal (immediate) Instruction Set ata transfer CLRW Mnemonic MOVF f, d MOVF f, MOVF f, W MOVF f, MOVF f, f MOVF f MOVWF f MOVLW k CLRF f f d k Operation d f W f f f f W W k f W Operands name / address of register destination literal Comment Move f to d d = W d = f Move W to f Move literal to W Clear f Clear W Flags destination = W, d = f, d =

9 Instruction Set rithmetic and Logic Instruction Set rithmetic and Logic Mnemonic WF f, d LW k SUBWF f, d SUBLW k INCF f, d ECF f, d NWF f, d NLW k Operation d f + W W k + W d f W W k W d f + d f d f and W W k and W Comment dd w to f dd k to W Sub W from f Sub W from k Inc f to d ec f to d nd w with f nd k with W Flags C, C, C, C, C, C, C, C, Mnemonic IORWF f, d IORLW k XORWF f, d XORLW k RLF f, d RRF f, d COMF f, d SWPF f, d Operation d f or W W k or W d f xor W W k xor W d left rotate f,c d right rotate f,c d #f (not f) d f L f H Comment OR w with f OR k with W XOR W with f XOR W with k compliment f to d nibble swap (nibble = half byte) Flags C C C f d k Operands name / address of register destination literal destination = W, d = f, d = f d k Operands name / address of register destination literal destination = W, d = f, d = Instruction Set Control Instruction Set Other Mnemonic GOTO a Operation branch to address Mnemonic BCF f, b Operation f<b> Flags BTFSC f, b skip one instruction if f<b> = BSF f, b f<b> BTFSS f, b skip one instruction if f<b> = NOP no operation INCFS f, d d f +, skip one if result = CLRWT WT TO#, P# ECFS f, d d f -, skip one if result = SLEEP go to low power consumption TO#, P# CLL a call subroutine in address a RETURN subroutine return RETFIE interrupt return RETLW k return from subroutine with k in W f d k Operands name / address of register destination literal a b bit address bit location f b Operands name / address of register bit location 5 6

10 7 Sample Program Fragments RM Initialization CLRF STTUS ; STTUS MOVLW x ; W st address in GPR bank MOVWF FSR ; Indirect address register W Bank_LP CLRF INF ; address in GPR INCF FSR ; FSR++ (next GPR address) BTFSS FSR, 7 ; skip if (FSR<7> == ) FSR = 8h GOTO Bank_LP ; continue ; ** IF EVICE HS BNK ** MOVLW x ; W st address in GPR bank MOVWF FSR ; Indirect address register W Bank_LP CLRF INF ; address in GPR INCF FSR ; FSR++ (next GPR address) BTFSS STTUS, C ; skip if (STTUS<> == ) FSR = h GOTO Bank_LP ; continue Sample Program Fragments Branch to address in new page Prog: movlw HIGH Prog ; W Prog<5:8> ; operator HIGH reads bits <5:8> of pointer movwf PCLTH ; PCLTH W goto Prog ; PC<:> Prog<7:> ; PC<:> PCLTH<:> Prog: ; ; Prog labels some address in program memory ; 8 Sample Program Fragments Computed goto movlw HIGH Prog movwf PCLTH movlw LOW Prog movwf PCL ; W Prog<5:8> ; PCLTH W ; W Prog<7:> ; PCL Prog<7:> ; PCH PCLTH<:> Prog: ; ; Prog labels some address in program memory ; Sample Programs Fragments if else branch btfss f,b ; skip one instruction if ; bit b in register f = goto ction ction: ; instructions for ction goto ction ction: ; instructions for ction ction: ; instructions for ction 9

11 Sample Programs Fragments Static loop movlw times ; W times movwf COUNTER ; COUNTER W (times) Loop: ; ; loop instructions ; decfsz COUNTER, f ; COUNTER-- ; COUNTER = skip next instruction goto Loop ; next iteration End: ; ; Sample Programs Fragments ata table in instruction memory ; Function call returns data at Table.INEX movlw HIGH Table ; W Table<5:8> movwf PCLTH ; PCLTH W movf INEX, W ; W INEX call Table ; Call to subroutine table ; Table: addwf PCL, f ; PCL PCL + W = PCL + INEX ; computed goto retlw '' ; return with W '' retlw 'B' retlw 'C' retlw '' retlw 'E' PIC MCU and the Outside World Oscillator Generates device clock Four device clock periods per instruction cycle Ports ata I/O pins Electrical connections to external circuits Configured to function as igital I/O nalog inputs to / converter Peripheral Modules Share data pins with general ports Timer / Comparator USRT CCP PIC Counts clock cycles interrupt on preset count Samples analog level converts to digital representation Samples analog levels outputs bit ( > ) Bit-parallel bit-serial converter for communications Capture/Compare/PWM (Pulse Width Modulation) OSC Ports Controls Controls evice dependent Power + ground Interrupt (INT) External clock Configurable Oscillator Modes Quartz crystal time base Crystal connected between PIC pins OSC and OSC Vibrates in electric field piezoelectric resonance in voltage Modes LP Low Frequency / Low Power Crystal khz to khz XT Crystal/Resonator khz to MHz HS High Speed Crystal/Resonator 8 MHz to MHz Resistor/Capacitor time base Capacitor discharges through resistor in time = πrc Oscillator frequency f = / (πrc) Modes EXTRC External RC connected between PIC pin OSC and ground INTRC Internal MHz RC CLKOUT EXTRC or INTRC with instruction clock (= f/) output on OSC

12 5 Interrupts Interrupt Instruction at current PC executes Instruction at current PC+ fetched Stack PC+ PC interrupt pointer On return from interrupt PC stack Interrupt sources External interrupt pin Pin RB on some PIC devices (separate pin on other devices) Peripheral modules General internal interrupt / Timer Comparator USRT CCP Interrupt Control Register Interrupt Control Register (INTCON) GIE PEIE TIE INTE RBIE TIF INTF RBIF GIE 7 PEIE 6 Global Interrupt Enable Peripheral Interrupt Enable Overflow Interrupt Enable External Interrupt Enable TIE RB Port Change Interrupt Enable Overflow Interrupt Flag External Interrupt Flag RB Port Change Interrupt Flag 5 INTE RBIE TIF = Enables all un masked interrupts = isables all interrupts = Enables INT external interrupt = isables INT external interrupt = TMR register has overflowed = TMR register did not overflow INTF = Enables all un masked peripheral interrupts = isables all peripheral interrupts = Enables TMR overflow interrupt = isables TMR overflow interrupt = Enables RB port change interrupt = isables RB port change interrupt = INT external interrupt occurred = INT external interrupt did not occur = t least one of RB7:RB pins changed state = None of RB7:RB pins have changed state RBIF 6 Peripheral Interrupt Enable (PIE) Number of PIE registers device dependent TMRIE TMRIE CCPIE CCPIE SSPIE RCIE TXIE IE CIE OVFIE PSPIE EEIE LCIE CMIE TMR Overflow TMR to PR Match CCP CCP Synchronous Serial Port USRT Receive USRT Transmit / Converter Slope / Converter Comparator Trip Slope / TMR Overflow Parallel Slave Port Read/Write EE Write Complete LC Comparator = enable device interrupt = disable device interrupt Peripheral Interrupt Register (PIR) Number of PIR registers device dependent TMRIE TMRIE CCPIE CCPIE SSPIE RCIE = TMR register overflowed = TMR register did not overflow Same as TMRIE CCP Interrupt Flag bit Capture Mode = TMR register capture occurred = No TMR register capture occurred Compare Mode = TMR register compare match occurred = No TMR register compare match occurred PWM Mode Unused in this mode Same as CCPIE = Transmission/reception complete = Waiting to transmit/receive = USRT receive buffer RCREG full = USRT receive buffer is empty 7 8

13 9 Peripheral Interrupt Register (PIR) Number of PIR registers device dependent TXIE IE CIE OVFIE PSPIE EEIE LCIE CMIE = USRT transmit buffer TXREG empty = USRT transmit buffer is full = / conversion complete = / conversion not complete = / conversion complete = / conversion not complete = Slope / TMR overflow = Slope / TMR did not overflow = Read or write operation occurred = Read or write did not occur = ata EEPROM write operation complete = ata EEPROM write operation not complete = LC interrupt occurred = LC interrupt did not occur = Comparator input changed = Comparator input not changed Interrupt Latency On interrupt. Current instruction execution completes. Current instruction fetch completes. PC interrupt pointer Latency ~ to instruction cycles 5 Interrupt Initialization + Enabling PIE_MSK EQU B ; ; CLRF STTUS CLRF INTCON CLRF PIR BSF STTUS, RP MOVLW PIE_MSK MOVWF PIE BCF STTUS, RP BSF INTCON, GIE ; Interrupt Enable ; Register mask (device ; dependent) ; Bank ; isable interrupts during ; configuration ; Clear flags ; Bank ; set PIE via W ; Bank ; Enable Interrupts Macros for Register Save / Restore PUSH_MCRO MCRO MOVWF W_TEMP SWPF STTUS,W MOVWF STTUS_TEMP ENM POP_MCRO MCRO SWPF STTUS_TEMP,W MOVWF STTUS SWPF W_TEMP,F SWPF W_TEMP,W ENM ; Save register contents ; Temporary register W ; W swap STTUS nibbles ; Temporary register STTUS ; End this Macro ; Restore register contents ; W swap STTUS ; STTUS W ; W_Temp swap W_Temp ; W swap W_Temp s ; no affect on STTUS ; End this Macro 5 5

14 5 Typical Interrupt Service Routine (ISR) org ISR_R ; store at ISR address PUSH_MCRO ; save context registers W, STTUS CLRF STTUS ; Bank ; switch implementation in PIC assembly language BTFSC PIR, TMRIF ; skip next if (PIR<TMRIF> == ) GOTO T_INT ; go to Timer ISR BTFSC PIR, IF ; skip next if (PIR<IF> == ) GOTO _INT ; go to / ISR BTFSC PIR, LCIF ; skip next if (PIR<LCIF> == ) GOTO LC_INT ; go to LC ISR BTFSC INTCON, RBIF ; skip next if (PIR<RBIF> == ) GOTO PORTB_INT ; go to PortB ISR GOTO INT_ERROR_LP ; default ISR Typical Interrupt Service Routine (ISR) T_INT ; Timer overflow routine : BCF PIR, TMRIF ; Clear Timer overflow interrupt flag GOTO EN_ISR ; Leave ISR _INT ; Routine when / completes : BCF PIR, IF ; Clear / interrupt flag GOTO EN_ISR ; Leave ISR LC_INT ; LC Frame routine : BCF PIR, LCIF ; Clear LC interrupt flag GOTO EN_ISR ; Leave ISR PORTB_INT ; PortB change routine : EN_ISR ; Leave ISR POP_MCRO ; Restore registers RETFIE ; Return and enable interrupts 5 Timers Watchdog Timer (WT) Watchdog timer (WT) Normal program resets timer before timeout (8 ms) Timeout Non-sleep mode MCU resets Sleep mode MCU wakes up executes instruction following sleep Configured in OPTION_REG SFR Timer Generic programmable 8-bit timer/counter Shares prescaler (divide by k, k =,...,8) with WT Configured in OPTION_REG SFR Timer Generic programmable 6-bit timer/counter Read / write two 8-bit registers Timer Generic programmable 8-bit timer/counter Time base for PWM mode Time base Internal RC oscillator Timer clock source 55 56

15 57 OPTION_REG SFR (File ddress 8h) Timer RBPU INTEG TCS RBPU Weak Pull up Enable INTEG Interrupt Edge Select TCS TMR Clock Source Select TSE TMR Source Edge Select PS Prescaler ssignment TSE PS PS PS = Interrupt on rising edge of INT pin = Interrupt on falling edge of INT pin = Transition on TCKI pin = Internal instruction cycle clock (CLKOUT) = Prescaler is assigned to the WT (watchdog) = Prescaler is assigned to the Timer module PS = Weak pull ups are disabled = Weak pull ups are enabled by port latch values Underline active = / inactive = = Increment on high to low transition on TCKI pin = Increment on low to high transition on TCKI pin 8-bit timer/counter Readable / writable at TMR SFR (File ddress 8h) 8-bit software programmable prescaler ivide input pulse train (slows time scale) Scale by :, :, :,..., :8 Selectable clock source External / internal Interrupt on overflow FFh h Edge select (phase synchronization with external clock) PS:PS Prescaler Rate Select PS:PS TMR : : :8 :6 WT : : : :8 PS:PS TMR : :6 :8 :56 WT :6 : :6 :8 58 Timer Operation Timer mode TCS = TMR++ on every instruction cycle (without prescaler) Write to TMR register no increment for two instruction cycles Counter mode TCS = TMR++ on every rising or falling edge of TCKI (external clock) Edge determined by TSE bit Prescaler Set by PS control bits TMR Interrupt Generated on overflow FFh h Sets bit TIF (INTCON<>) Timer interrupt service routine Clear TIF Re-enable interrupt Initialize Timer with Internal Clock Source CLRF TMR ; Clear Timer register CLRF INTCON ; isable interrupts and clear TIF BSF STTUS, RP ; Bank MOVLW xc ; isable PortB pull-ups ; C = MOVWF OPTION_REG ; Interrupt on rising edge of RB ; Timer increment from internal clock ; Prescale = :6. BCF STTUS, RP ; Bank T_OVFL_WIT BTFSS INTCON, TIF ; poll overflow bit GOTO T_OVFL_WIT ; on timer overflow 59 6

16 6 Timer 6-bit timer/counter TMR pair TMRH:TMRL Readable and writable 8-bit registers Counter h to FFFFh with rollover to h Generate Timer interrupt on rollover (if enabled) Modes Synchronous timer TMR++ on every instruction cycle (F OSC / ) synchronous counter TMR++ on rising edge of input pin Synchronous counter TMR++ on rising edge of sampled input pin Synchronized to internal clock T OSC Sample input pin on rising edge of T OSC Input must be high / low for at least T OSC Input Sample Clock Sampled Input TCON SFR 7 TCKPS TCKPS TOSCEN TSYNC TMRCS TMRON 6 Timer On TCKPS 5 Timer Input Clock Prescale Select Timer Oscillator Enable Timer External Clock Input Synchronization Select Timer Clock Source Select TCKPS TOSCEN = :8 Prescale value = : Prescale value = Enables Timer = Stops Timer TSYNC TMRCS = (Counter Mode) = synchronous Counter Mode = Synchronous Counter Mode TMRCS = (Timer Mode) Ignored = Oscillator mode enabled = Oscillator mode disabled TMRCS TMRON = : Prescale value = : Prescale value = Counter Mode (count external clock) = Timer Mode (count internal clock F OSC / ) 6 Timer Operation Reading Timer CLK In / OSC out Oscillator Mode TCKI TOSI Counter Mode Timer Mode sync Input Sampling ; ll interrupts disabled MOVF TMRH, W ; W high byte MOVWF TMPH ; TMPH W MOVF TMRL, W ; W low byte MOVWF TMPL ; TMPL W ; TMRL can roll-over between reads of high and low bytes MOVF TMRH, W ; W high byte again SUBWF TMPH, W ; Verify high byte BTFSC STTUS, ; bad read ( = not equal) re-do GOTO CONTINUE ; New reading good value. MOVF TMRH, W ; W high byte MOVWF TMPH ; TMPH W MOVF TMRL, W ; W low byte MOVWF TMPL ; TMPL W ; Re-enable interrupts (if required) CONTINUE ; Continue 6 6

17 65 Writing Timer ; ll interrupts are disabled CLRF TMRL ; Clear Low byte ; Prevents rollover to TMRH MOVLW HI_BYTE ; W HI_BYTE MOVWF TMRH, F ; TMRH W MOVLW LO_BYTE ; W LO_BYTE MOVWF TMRL, F ; TMRL W Timer Readable / writable 8-bit timer Prescaler Period register PR Readable / writable TMR = PR reset (TMR ) Postscaler Counts TMR = PR resets Triggers TMRIF interrupt flag ; Re-enable interrupts (if required) CONTINUE ; Continue 66 TCON SFR Ports 7 TOUTPS 6 TOUTPS 5 TOUTPS TOUTPS TMRON TCKPS TCKPS I/O pins Electrical connections to external circuits Configurable in SFR CON as PIC OSC Ports Controls TOUTPS: TMRON Timer Output Postscale Select Timer On = : Postscale = : Postscale = : Postscale = : Postscale : = :6 Postscale = Timer is on = Timer is off igital I/O nalog inputs to / converter Mid-Range PIC configurations Minimal Port (6 pins) + Port B (8 pins) Maximal Port (6 pins), Port B (8 pins),..., Port G (8 pins) Special Function Registers ata PORT,..., PORTG PORTi<x> = data bit on pin x of port i TCKPS: Timer Clock Prescale Select = Prescaler is = Prescaler is x = Prescaler is 6 irection TRIS,..., TRISG TRISi<x> = pin x of port i is Input TRISi<x> = pin x of port i is Output 67 68

18 69 Port ccess Output Set TRISi<x> = Write data bit to PORTi<x> Input Set TRISi<x> = Read data bit from PORTi<x> Order of operations Read Reads levels on physical I/O pins (not data register file) Write Implemented as read modify Causes update of all input data registers from physical I/O pins Program must read all required inputs before any write PORT 5 general purpose I/O pins R5 and R:R Standard electrical behavior TTL input levels and CMOS output drivers Special input R Schmitt trigger input Threshold decision converts input to binary (R > threshold) Open drain output Permits specialize electrical functions on output Wired-OR, analog weighting,... 7 Initializing PORT PORTB CLRF STTUS CLRF PORT BSF STTUS, RP MOVLW xcf MOVWF TRIS ; Bank ; Initialize PORT ; Select Bank ; Initialize data directions ; CFh = ; = x x Out Out In In In In ; PORT<:> = inputs ; PORT<5:> = outputs ; TRIS<7:6> always read 8 general purpose I/O pins RB7:RB Standard electrical behavior TTL input levels and CMOS output drivers Interrupt on change Input pins RB7:RB Inputs compared with previous read of PORTB OR(compare bits) = RB Port Change Interrupt Can wake device from SLEEP Example wake-up on key press Clear interrupt Read or write PORTB Clear flag bit RBIF 7 7

19 7 Ports C to G Ports C to E 8 binary I/O pins Ri7:Ri, i = C,, E Schmitt trigger on each input pin Ports F and G Ri7:Ri, i = F, G 8 binary inputs Schmitt trigger on each input 8 LC driver outputs irect connection to 7-segment display nalog to igital (/) Converter Module Converts analog input signals Sample and hold One of 8 analog inputs (channels) Conversion to 8-bit binary number nalog reference voltage Software selectable evice supply voltage Voltage level on V REF pin Can operate in sleep mode Three registers / Result Register (RES) / Control Register (CON) / Control Register (CON) 7 CON SFR CON SFR CS CS CHS CHS CHS GO/ONE Resv ON PCFG PCFG PCFG / Conversion Clock Select PCFG:PCFG N7 N6 N5 N N N N N CS:CS = f OSC / = f OSC /8 = f OSC / = f RC (internal / RC osc) nalog Channel Select V REF V REF CHS:CHS = channel (N) = channel (N) = channel (N) = channel (N) : = channel 7 (N7) x V REF GO/ONE = in progress / Conversion Status = not in progress Port pin configured for analog input Port pin configured for digital I/O Reserved ON = activated / On = deactivated N = V REF N = Conversion compares to reference voltage V REF = voltage on N Conversion compares to reference voltage V REF = device supply voltage 75 76

20 77 Operation of / Converter Configure / module nalog pins + voltage reference + digital I/O in CON Select / input channel (CON) Select / conversion clock (CON) ctivate / module (CON) Configure / interrupt (optional) Clear IF Set IE + GIE Start conversion Set GO/ONE bit (CON) Wait for / conversion to complete Poll GO/ONE until cleared or wait for / interrupt Read result / Result register (RES) Repeat / Conversion BSF STTUS, RP ; Bank CLRF CON ; Configure inputs as analog BSF PIE, IE ; Enable / interrupts BCF STTUS, RP ; Bank MOVLW xc ; Ch = MOVWF CON ; Internal RC, / active, Channel BCF PIR, IF ; Clear / interrupt flag BSF INTCON, PEIE ; Enable peripheral interrupts BSF INTCON, GIE ; Enable all interrupts ; ; Wait required sampling time for selected input ; BSF CON, GO ; CON<> Start conversion ; On completion IF bit and GO/ONE 78 Comparator Comparator Modes Two analog comparators Inputs shared with I/O pins ccess via CMCON SRF (device-dependent file address) Operation nalog input at V IN + < V IN output = binary nalog input at V IN + > V IN output = binary CMCON SFR COUT 7 COUT 6 5 CIS CM CM CM COUT COUT CIS CM:CM Comparator Outputs Comparator Input Switch = V IN + > V IN = V IN + > V IN See table on following slides response time 79 8

21 8 Comparator Modes Initialize Comparator FLG_REG EQU x ; FLG_REG points to address h CLRF FLG_REG ; flag register CLRF PORT ; PORT NLW xc ; Mask comparator bits W<5:> IORWF FLG_REG,F ; FLG_REG FLG_REG OR W MOVLW x ; Init comparator mode MOVWF CMCON ; CM<:> = ( common reference) BSF STTUS,RP ; Bank MOVLW x7 ; Initialize data direction MOVWF TRIS ; Set R<:> as inputs ; R<:> as outputs ; TRIS<7:5> read BCF STTUS,RP ; Bank CLL ELY ; ms delay MOVF CMCON,F ; Read CMCON (enter read mode) BCF PIR,CMIF ; Clear pending interrupts BSF STTUS,RP ; Bank BSF PIE,CMIE ; Enable comparator interrupts BCF STTUS,RP ; Bank BSF INTCON,PEIE ; Enable peripheral interrupts BSF INTCON,GIE ; Global interrupt enable 8 USRT Universal Synchronous / synchronous Receiver / Transmitter Serial Communications Interface (SCI) PC serial port / modem Transmit Parallel serial ata byte as 8 serial bits Receive Serial parallel ssemble 8 bits as data byte Modes synchronous Full duplex simultaneous transmit + receive Synchronous Half duplex transmit or receive Master synchronize data to internal clock Slave synchronize data to external clock USRT Transmit Operation ata Byte TXREG framing TSR bit FIFO TX pin Framing add start bit / parity bit Interrupt on empty TXREG Transmit Speed Parity bit TSR full / empty Port Enable 8 8

22 85 USRT Receive Operation ata RX pin bit FIFO RSR RCREG byte Framing Identify data between stop bits Check for parity error Port Enable Continuous Receive Enable Sample + FIFO RCREG full Parity bit Overrun Error Framing Error Capture / Compare / PWM (CCP) Module SFRs CCP control register (CPCON) CCPR High byte / Low byte (CCPRH / CCPRL) I/O pin CPP pin (CPPx) device-dependent pin configured in TRIS SFR Capture Mode Captures 6-bit value of register TMR on CCPx event Every falling edge / rising edge / th rising edge / 6th rising edge Triggers interrupt Compare mode Compare 6-bit (CCPR == TMR) Configurable response on match CCPx / Period Interrupt with no change on CPPx uty cycle Pulse Width Modulation (PWM) mode Generates duty cycle waveform on CCPx 86 CCPxCON SFR Capture Mode 7 6 CxB 5 CxB CCPxM CCPxM CCPxM CCPxM Event Input pin CCPx divided by prescaler sampled on rising / falling edge CxB:CxB PWM uty Cycle bit and bit Cx:Cx of bit PWM duty cycle Cx9:Cx in CCPRxL Interrupt flag, x =, CCPxM:CCPxM CCPx Mode Select bits = Capture/Compare/PWM off (resets CCPx module) = Capture mode, every falling edge = Capture mode, every rising edge = Capture mode, every th rising edge = Capture mode, every 6th rising edge = Compare mode, CCP low to high = Compare mode, CCP high to low = Compare mode, software interrupt on match = Compare mode, Trigger special event xx = PWM mode Configuration CCP control register, x =, CCPxR = CCPRxH:CCPRxL, x =, 6 bit value in Timer 87 88

23 89 Compare Mode 6-bit compare (CCPRx == TMR), x =, Pulse Width Modulation (PWM) mode Generates duty cycle waveform Reset Timer Interrupt Set duty cycle Period = (PR + ) prescale T OSC 6 bit preset value in CCPRx uty cycle = C prescale T OSC Period uty cycle PR 55 C 6 bit value of Timer Set period 9 uty Cycle uty Cycle PWM ON PWM PWM T = C P T ON ΔT = P T ON PWM ΔT = P T OSC OSC OSC T = (PR+ ) P T PWM TON C P TOSC C = = T PR+ P T PR+ T T Controllability ( ) ( ) OSC ( ) C PR+ ΔTON P TOSC = = T PR+ P T PR+ Resolution ( ) ( ) OSC OSC OSC ( ( + ) ) ( ) r T log PR P ON C ( PR+ ) = ( PR+ ) P r= T log uty Cycle Example Frequency and duty cycle from given parameters OSC PWM PWM PWM PWM OSC ( ) ON - ( ) f = MHz T = MHz = 5 ns P= PR = 6 T = 6 5 ns =.8 μs ( ) ( ) - f =.8 μ s = 78.5 khz C = T = 5 ns =.6 ms TON = =.5 =.5% T 6 ΔTON = = =.965 T 6 56 T log 56 = = = T log r ON 6 r 8 OSC 9 9

24 9 PWM Example Choosing parameters Internal oscillator f OSC = MHz T OSC =.5 μs PWM frequency T PWM = ms = (PR + ) P.5 μs = (PR + ) P μs Require (PR + ) P = Preset and PR P = PR + = 5 PR = 9 = xf9 ΔT ON = P T OSC = μs uty cycle = % Oscillator frequency = MHz Produce output with khz frequency (T PWM = ms) % duty cycle T ON =. ms = μs C =. (PR + ) = = x6 CH = x9 = 5 CL = PWM Example Code List p = 6F87 include "P6F87.INC" Init_pwm: movlw x ; Stop Timer movwf TCON ; Prescaler clrf CCPCON ; Reset module CCP clrf TMR ; Timer movlw.5 ; % duty cycle movwf CCPRL ; CB9:CB bsf STTUS, RP ; Bank movlw.9 ; Timer movwf PR bcf PIE, TMRIE ; isable Timer interrupt bcf PIE, CCPIE ; isable CCP interrupt bcf TRISC, ; Pin CCP = output bcf STTUS, RP ; Bank clrf PIR ; Clear interrupt flags movlw xc ; CCP in PWM mode movwf CCPCON ; CB:CB bsf TCON, TMRON ; Start Timer return TON_pwm: movwf CCPRL ; Call to change return ; uty cycle end 9 ata EEPROM dditional long term data memory Internal EEPROM Indirect addressing Not directly mapped in register file space ccess through SFRs EECON Control bits EECON Initiates read / write operation Virtual register not physically implemented EET 8-bit data for read / write EER ccess address in EEPROM 8-bit address 56 EEPROM locations EECON SFR 7 EEIF WRERR WREN WR R 6 Write Operation Interrupt Flag Error Flag Write Enable Write Control Read Control 5 EEIF WRERR WREN = Write operation completed = Write operation not complete / not started = Write operation prematurely terminated = Write operation completed = llows write cycles = Inhibits write to data EEPROM = Initiates write cycle = Write cycle to data EEPROM is complete (cleared by hardware) = Initiates read = oes not initiate an EEPROM read (cleared by hardware) WR R 95 96

25 97 EECON SFR Not physical register Read EECON SFR access to EEPROM write hardware ata EEPROM write sequence EET data EER address_for_write W 55h EECON W W h EECON W ; EECON 55h EECON<WR> ; initiate (write control bit set) EEPROM Read / Write / Verify Read BCF STTUS, RP ; Bank MOVLW CONFIG_R ; ddress in ata EEPROM MOVWF EER ; Set read address BSF STTUS, RP ; Set Bank BSF EECON, R ; Initiate EEPROM Read BCF STTUS, RP ; Set Bank MOVF EET, W ; W EET Write BSF STTUS, RP ; Bank BCF INTCON, GIE ; isable INTs BSF EECON, WREN ; Enable write MOVLW 55h ; W 55h MOVWF EECON ; EECON W MOVLW h ; W h MOVWF EECON ; EECON W BSF EECON,WR ; Set WR bit (initiates write) BSF INTCON, GIE ; Enable INTs 98 EEPROM Read / Write / Verify Verify BCF STTUS, RP ; Bank MOVF EET, W ; copy write request data to W BSF STTUS, RP ; Bank RE BSF EECON, R ; Initiate read BCF STTUS, RP ; Bank SUBWF EET, W ; W write request read BTFSS STTUS, ; Skip next if ( == ) GOTO WRITE_ERR ; Handle write error PIC Configuration Bits etermines certain device modes Oscillator mode, WT reset, copy protection Sets device state on power-up Configured during EEPROM programming Mapped to program memory location 7h Not accessible at run time CP:CP P BOEN PWRTE MCLRE Code Protection ata EEPROM Code Protection Brown out Reset Enable Power up Timer Enable MCLR (master clear) Pin Function = Code protection off = device dependent = device dependent = memory code protected = Code protection off = ata EEPROM Memory code protected = BOR enabled = BOR disabled = PWRT disabled = PWRT enabled = Pin function = MCLR = Pin function = digital I/O 99

26 PIC Configuration Bits WTE FOSC:FOSC Watchdog Timer Enable Oscillator Selection For devices with no internal RC = WT enabled = WT disabled = RC oscillator = HS oscillator = XT oscillator = LP oscillator FOSC:FOSC Oscillator Selection For devices with internal RC = EXTRC oscillator, with CLKOUT = EXTRC oscillator = INTRC oscillator, with CLKOUT = INTRC oscillator = Reserved = HS oscillator = XT oscillator = LP oscillator