EECS150 - Digital Design Lecture 9- CPU Microarchitecture. Watson: Jeopardy-playing Computer
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1 EECS150 - Digital Design Lecture 9- CPU Microarchitecture Feb 15, 2011 John Wawrzynek Spring 2011 EECS150 - Lec09-cpu Page 1 Watson: Jeopardy-playing Computer Watson is made up of a cluster of ninety IBM Power 750 servers (plus additional I/O, network and cluster controller nodes in 10 racks) for a total of 2880 POWER7 processor cores and 16 Terabytes of RAM. Each Power 750 server uses a 3.5 GHz POWER7 eight core processor, with four threads per core. and it still takes ~15 seconds a question. Each core can do 8 double-precision FLOPS/cycle. So total is 2880*3.5*8 > 80 TFLOPS Spring 2011 EECS150 - Lec09-cpu Page 2
2 Processor Microarchitecture Introduction Microarchitecture: how to implement an architecture in hardware Good examples of how to put principles of digital design to practice. Introduction to final project. Spring 2011 EECS150 - Lec09-cpu Page 3 MIPS Processor Architecture For now we consider a subset of MIPS instructions: R-type instructions: and, or, add, sub, slt Memory instructions: lw, sw Branch instructions: beq Later we ll add addi and j Spring 2011 EECS150 - Lec09-cpu Page 4
3 MIPS Micrarchitecture Oganization Datapath + Controller + External Memory Controller Spring 2011 EECS150 - Lec09-cpu Page 5 How to Design a Processor: step-by-step 1. Analyze instruction set architecture (ISA) datapath requirements meaning of each instruction is given by the data transfers (register transfers) datapath must include storage element for ISA registers datapath must support each data transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the data transfer. 5. Assemble the control logic. Spring 2011 EECS150 - Lec09-cpu Page 6
4 Review: The MIPS Instruction R-type I-type J-type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt address/immediate 6 bits 5 bits 5 bits 16 bits 26 op target address 6 bits 26 bits The different fields are: op: operation ( opcode ) of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the op field address / immediate: address offset or immediate value target address: target address of jump instruction Spring 2011 EECS150 - Lec09-cpu Page 7 add, sub, or, slt addu rd,rs,rt subu rd,rs,rt lw, sw lw rt,rs,imm16 sw rt,rs,imm16 beq beq rs,rt,imm16 Subset for Lecture op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 26 Spring 2011 EECS150 - Lec09-cpu Page op rs rt immediate 6 bits 5 bits 5 bits 16 bits op rs rt immediate 6 bits 5 bits 5 bits 16 bits
5 Register Transfer Descriptions All start with instruction fetch: {op, rs, rt, rd, shamt, funct} IMEM[ PC ] OR {op, rs, rt, Imm16} IMEM[ PC ] THEN inst Register Transfers add R[rd] R[rs] + R[rt]; PC PC + 4 sub R[rd] R[rs] R[rt]; PC PC + 4 or R[rd] R[rs] R[rt]; PC PC + 4 slt R[rd] (R[rs] < R[rt])? 1 : 0; PC PC + 4 lw R[rt] DMEM[ R[rs] + sign_ext(imm16)]; PC PC + 4 sw DMEM[ R[rs] + sign_ext(imm16) ] R[rt]; PC PC + 4 beq if ( R[rs] == R[rt] ) then PC PC {sign_ext(imm16), 00} else PC PC + 4 Spring 2011 EECS150 - Lec09-cpu Page 9 Microarchitecture Multiple implementations for a single architecture: Single-cycle Each instruction executes in a single clock cycle. Multicycle Each instruction is broken up into a series of shorter steps with one step per clock cycle. Pipelined (variant on multicycle ) Each instruction is broken up into a series of steps with one step per clock cycle Multiple instructions execute at once. Spring 2011 EECS150 - Lec09-cpu Page 10
6 CPU clocking (1/2) Single Cycle CPU: All stages of an instruction are completed within one long clock cycle. The clock cycle is made sufficient long to allow each instruction to complete all stages without interruption and within one cycle. 1. Instruction Fetch 2. Decode/ Register Read 3. Execute 4. Memory 5. Reg. Write Spring 2011 EECS150 - Lec09-cpu Page 11 CPU clocking (2/2) Multiple-cycle CPU: Only one stage of instruction per clock cycle. The clock is made as long as the slowest stage. 1. Instruction Fetch 2. Decode/ Register Read 3. Execute 4. Memory 5. Reg. Write Several significant advantages over single cycle execution: Unused stages in a particular instruction can be skipped OR instructions can be pipelined (overlapped). Spring 2011 EECS150 - Lec09-cpu Page 12
7 MIPS State Elements Determines everything about the execution status of a processor: PC register 32 registers Memory Note: for these state elements, clock is used for write but not for read (asynchronous read, synchronous write). Spring 2011 EECS150 - Lec09-cpu Page 13 Single-Cycle Datapath: lw fetch First consider executing lw STEP 1: Fetch instruction R[rt] DMEM[ R[rs] + sign_ext(imm16)] Spring 2011 EECS150 - Lec09-cpu Page 14
8 Single-Cycle Datapath: lw register read R[rt] DMEM[ R[rs] + sign_ext(imm16)] STEP 2: Read source operands from register file Spring 2011 EECS150 - Lec09-cpu Page 15 Single-Cycle Datapath: lw immediate R[rt] DMEM[ R[rs] + sign_ext(imm16)] STEP 3: Sign-extend the immediate Spring 2011 EECS150 - Lec09-cpu Page 16
9 Single-Cycle Datapath: lw address R[rt] DMEM[ R[rs] + sign_ext(imm16)] STEP 4: Compute the memory address Spring 2011 EECS150 - Lec09-cpu Page 17 Single-Cycle Datapath: lw memory read R[rt] DMEM[ R[rs] + sign_ext(imm16)] STEP 5: Read data from memory and write it back to register file Spring 2011 EECS150 - Lec09-cpu Page 18
10 Single-Cycle Datapath: lw PC increment STEP 6: Determine the address of the next instruction PC PC + 4 Spring 2011 EECS150 - Lec09-cpu Page 19 Single-Cycle Datapath: sw DMEM[ R[rs] + sign_ext(imm16) ] R[rt] Write data in rt to memory Spring 2011 EECS150 - Lec09-cpu Page 20
11 Single-Cycle Datapath: R-type instructions Read from rs and rt Write ALUResult to register file Write to rd (instead of rt) R[rd] R[rs] op R[rt] Spring 2011 EECS150 - Lec09-cpu Page 21 Single-Cycle Datapath: beq if ( R[rs] == R[rt] ) then PC PC {sign_ext(imm16), 00} Determine whether values in rs and rt are equal Calculate branch target address: BTA = (sign-extended immediate << 2) + (PC+4) Spring 2011 EECS150 - Lec09-cpu Page 22
12 Complete Single-Cycle Processor Spring 2011 EECS150 - Lec09-cpu Page 23 Review: ALU F 2:0 Function 000 A & B 001 A B 010 A + B 011 not used 100 A & ~B 101 A ~B 110 A - B 111 SLT Spring 2011 EECS150 - Lec09-cpu Page 24
13 Control Unit Spring 2011 EECS150 - Lec09-cpu Page 25 Control Unit: ALU Decoder ALUOp 1:0 Meaning 00 Add 01 Subtract 10 Look at Funct 11 Not Used ALUOp 1:0 Funct ALUControl 2:0 00 XXXXXX 010 (Add) X1 XXXXXX 110 (Subtract) 1X (add) 010 (Add) 1X (sub) 110 (Subtract) 1X (and) 000 (And) 1X (or) 001 (Or) Spring 2011 EECS150 - Lec09-cpu Page 26 1X (slt) 111 (SLT)
14 Control Unit: Main Decoder Instruction Op 5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp 1:0 R-type lw sw beq Spring 2011 EECS150 - Lec09-cpu Page 27 Control Unit: Main Decoder Instruction Op 5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp 1:0 R-type lw sw X X 00 beq X X 01 Spring 2011 EECS150 - Lec09-cpu Page 28
15 Single-Cycle Datapath Example: or Spring 2011 EECS150 - Lec09-cpu Page 29 Extended Functionality: addi No change to datapath Spring 2011 EECS150 - Lec09-cpu Page 30
16 Control Unit: addi Instruction Op 5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp 1:0 R-type lw sw X X 00 beq X X 01 addi Spring 2011 EECS150 - Lec09-cpu Page 31 Control Unit: addi Instruction Op 5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp 1:0 R-type lw sw X X 00 beq X X 01 addi Spring 2011 EECS150 - Lec09-cpu Page 32
17 Extended Functionality: j Spring 2011 EECS150 - Lec09-cpu Page 33 Control Unit: Main Decoder Instruction Op 5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp 1:0 Jump R-type lw sw X X 00 0 beq X X 01 0 j Spring 2011 EECS150 - Lec09-cpu Page 34
18 Control Unit: Main Decoder Instructi on Op 5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp 1:0 Jump R-type lw sw X X 0 0 beq X X 1 0 j X X X 0 X XX 1 Spring 2011 EECS150 - Lec09-cpu Page 35 Review: Processor Performance Program Execution Time = (# instructions)(cycles/instruction)(seconds/cycle) = # instructions x CPI x T C Spring 2011 EECS150 - Lec09-cpu Page 36
19 Single-Cycle Performance T C is limited by the critical path (lw) Spring 2011 EECS150 - Lec09-cpu Page 37 Single-Cycle Performance Single-cycle critical path: T c = t pcq_pc + t mem + max(t RFread, t sext + t mux ) + t ALU + t mem + t mux + t RFsetup In most implementations, limiting paths are: memory, ALU, register file. T c = t pcq_pc + 2t mem + t RFread + t mux + t ALU + t RFsetup Spring 2011 EECS150 - Lec09-cpu Page 38
20 Single-Cycle Performance Example Element Parameter Delay (ps) Register clock-to-q t pcq_pc 30 Register setup t setup 20 Multiplexer t mux 25 ALU t ALU 200 Memory read t mem 250 Register file read t RFread 150 Register file setup t RFsetup 20 T c = Spring 2011 EECS150 - Lec09-cpu Page 39 Single-Cycle Performance Example Element Parameter Delay (ps) Register clock-to-q t pcq_pc 30 Register setup t setup 20 Multiplexer t mux 25 ALU t ALU 200 Memory read t mem 250 Register file read t RFread 150 Register file setup t RFsetup 20 T c = t pcq_pc + 2t mem + t RFread + t mux + t ALU + t RFsetup = [30 + 2(250) ] ps = 925 ps Spring 2011 EECS150 - Lec09-cpu Page 40
21 Single-Cycle Performance Example For a program with 100 billion instructions executing on a singlecycle MIPS processor, Execution Time = Spring 2011 EECS150 - Lec09-cpu Page 41 Single-Cycle Performance Example For a program with 100 billion instructions executing on a singlecycle MIPS processor, Execution Time = # instructions x CPI x T C = ( )(1)( s) = 92.5 seconds Spring 2011 EECS150 - Lec09-cpu Page 42
22 Pipelined MIPS Processor Temporal parallelism Divide single-cycle processor into 5 stages: Fetch Decode Execute Memory Writeback Add pipeline registers between stages Spring 2011 EECS150 - Lec09-cpu Page 43 Single-Cycle vs. Pipelined Performance Spring 2011 EECS150 - Lec09-cpu Page 44
23 Pipelining Abstraction Spring 2011 EECS150 - Lec09-cpu Page 45 Single-Cycle and Pipelined Datapath Spring 2011 EECS150 - Lec09-cpu Page 46
24 Corrected Pipelined Datapath WriteReg must arrive at the same time as Result Spring 2011 EECS150 - Lec09-cpu Page 47 Pipelined Control Same control unit as single-cycle processor Spring 2011 EECS150 - Lec09-cpu Page 48 Control delayed to proper pipeline stage
25 Pipeline Hazards Occurs when an instruction depends on results from previous instruction that hasn t completed. Types of hazards: Data hazard: register value not written back to register file yet Control hazard: next instruction not decided yet (caused by branches) Spring 2011 EECS150 - Lec09-cpu Page 49
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