Trading hardware overhead for communication performance in mesh-type topologies
|
|
- Dora Bond
- 5 years ago
- Views:
Transcription
1 Trading hardware overhead for communication performance in mesh-type topologies Claas Cornelius, Philipp Gorski, Stephan Kubisch, Dirk Timmermann 13th EUROMICRO Conference on Digital System Design (DSD) - Architectures, Methods and Tools University of Rostock
2 Outline Introduction Setup Scenarios BEAM Border-Enhanced Mesh Discussion Results Open issues Conclusion 2
3 Introduction Development of technology Continuous scaling of physical dimensions Smaller devices Higher integration density Higher performance >2000: Functional integration 1958: First IC 1981: Personal Computer (PC) 3
4 Introduction Development of technology Continuous scaling of physical dimensions Smaller devices Main challenges Higher integration density Productivity Power dissipation Reliability and robustness Higher performance To To cope with these challenges requires extensive research and development >2000: Functional integration 1958: First IC 1981: Personal Computer (PC) 4
5 Introduction What shines brighter than a bulb? Two bulbs Key characteristics: Parallelism Modularity 5
6 Introduction What shines brighter than a bulb? Two bulbs Crucial change Determining for for efficiency becomes Communication and Coordination Network-On-Chip (NOC) seems Key characteristics: an an appropriate design paradigm Parallelismto to cope with current concerns Modularity 6
7 Setup Selection of underlying platform 1. FPGA = Xilinx Virtex-4 Concerned with area usage 2. ASIC = STMicroelectronics 65 nm Concerned with power consumption Application scenarios 1. Application-specific Few heterogeneous resources Known requirements 2. Domain-specific 3. General purpose: Many homogeneous resources Unknown requirements 7
8 Setup Starting point: Mesh-type topologies Standard mesh Concentrated mesh J. Balfour and W. Dally, Design tradeoffs for tiled CMP on-chip networks, In Proc. of ICS,
9 Setup Starting point: Mesh-type topologies BEAM Clustered mesh S. Bourduas and Z. Zilic, A hybrid ring/mesh interconnect for network-onchip using hierarchical rings for global routing, In Proc. of NOCS,
10 Setup BEAM Border-Enhanced Mesh (BEAM) Key objectives: Reduced overall overhead Maintaining regularity Use of only low-radix routers * Cartesian addressing Dimension-ordered routing * A. Ferrante, S. Medardoni, and D. Bertozzi, Network interface sharing techniques for area optimized NoC architectures, In Proc. of DSD,
11 Setup BEAM Topology and its addressing 11
12 Setup BEAM Routing in BEAM 12
13 Results Analytical comparison 13
14 Results Communication characteristics I Saturation points 14
15 Results Communication characteristics II 15
16 Results Synthesis Number of routers only a first measure Higher radix hurts the frequency 16
17 Open issues Benchmarking Setup influences results drastically, consider Packet lengths, traffic patterns Presented metrics Necessary benchmark suites have to be platform-dependent and domain-specific. Comparison of of solutions and results becomes questionable without accepted measures. C. Grecu, et al., Towards open network-on-chip benchmarks, In Proc. of NOCS, E. Salminen, et al., Requirements for network-on-chip benchmarking, In Proc. of NORCHIP,
18 Open issues Reliability and robustness Complex systems will exhibit failures But most contributions on NOC assume faultless operation To be answered (an extract): Physical = Which causes to consider? Models = How to integrate models into the design process? Metrics = How to evaluate reliability and robustness? Suggestion: Energy-Reliability Ratio (ERR) ERR = Ptot t d Reliability = Energy Reliability 18
19 Conclusion Mesh-type topologies are beneficial for the use in complex Networks-On-Chip (NOC) Comparison of different mesh-type topologies Selection of best suited topology highly depends on given requirements Characteristics have to be traded off Open concerns that restrain further research on NOC Accepted benchmark suites are required Reliability has to be considered as a key design quality 19
High-Level Simulations of On-Chip Networks
High-Level Simulations of On-Chip Networks Claas Cornelius, Frank Sill, Dirk Timmermann 9th EUROMICRO Conference on Digital System Design (DSD) - Architectures, Methods and Tools - University of Rostock
More informationTrading hardware overhead for communication performance in mesh-type topologies
Trading hardware overhead for communication performance in mesh-type topologies Claas Cornelius Philipp Gorski Stephan Kubisch Dirk Timmermann Institute of Applied Microelectronics and Computer Engineering
More informationMapping a Pipelined Data Path onto a Network-on-Chip
Mapping a Pipelined Data Path onto a Network-on-Chip Stephan Kubisch, Claas Cornelius, Ronald Hecht, Dirk Timmermann {stephan.kubisch;claas.cornelius}@uni-rostock.de University of Rostock Institute of
More informationFCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow Abstract: High-level synthesis (HLS) of data-parallel input languages, such as the Compute Unified Device Architecture
More informationButterfly vs. Unidirectional Fat-Trees for Networks-on-Chip: not a Mere Permutation of Outputs
Butterfly vs. Unidirectional Fat-Trees for Networks-on-Chip: not a Mere Permutation of Outputs D. Ludovici, F. Gilabert, C. Gómez, M.E. Gómez, P. López, G.N. Gaydadjiev, and J. Duato Dept. of Computer
More informationMinRoot and CMesh: Interconnection Architectures for Network-on-Chip Systems
MinRoot and CMesh: Interconnection Architectures for Network-on-Chip Systems Mohammad Ali Jabraeil Jamali, Ahmad Khademzadeh Abstract The success of an electronic system in a System-on- Chip is highly
More informationCCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers
CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers Stavros Volos, Ciprian Seiculescu, Boris Grot, Naser Khosro Pour, Babak Falsafi, and Giovanni De Micheli Toward
More informationJoint consideration of performance, reliability and fault tolerance in regular Networks-on-Chip via multiple spatially-independent interface terminals
Joint consideration of performance, reliability and fault tolerance in regular Networks-on-Chip via multiple spatially-independent interface terminals Philipp Gorski, Tim Wegner, Dirk Timmermann University
More informationParameters of a On-Chip Network for Multi-Processor System-on-Chip Environments
Parameters of a On-Chip Network for Multi-Processor System-on-Chip Environments Sang Kyun Kim skkim38@stanford.edu 1. INTRODUCTION Network-on-chips (NoC) are replacing the conventional way of on-chip communication
More informationNetwork on Chip Architectures BY JAGAN MURALIDHARAN NIRAJ VASUDEVAN
Network on Chip Architectures BY JAGAN MURALIDHARAN NIRAJ VASUDEVAN Multi Core Chips No more single processor systems High computational power requirements Increasing clock frequency increases power dissipation
More informationOverlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-Chip. Danella Zhao and Ruizhe Wu Presented by Zhonghai Lu, KTH
Overlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-Chip Danella Zhao and Ruizhe Wu Presented by Zhonghai Lu, KTH Outline Introduction Overview of WiNoC system architecture Overlaid
More informationRe-Examining Conventional Wisdom for Networks-on-Chip in the Context of FPGAs
This work was funded by NSF. We thank Xilinx for their FPGA and tool donations. We thank Bluespec for their tool donations. Re-Examining Conventional Wisdom for Networks-on-Chip in the Context of FPGAs
More informationRuntime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays
Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays Éricles Sousa 1, Frank Hannig 1, Jürgen Teich 1, Qingqing Chen 2, and Ulf Schlichtmann
More informationNoc Evolution and Performance Optimization by Addition of Long Range Links: A Survey. By Naveen Choudhary & Vaishali Maheshwari
Global Journal of Computer Science and Technology: E Network, Web & Security Volume 15 Issue 6 Version 1.0 Year 2015 Type: Double Blind Peer Reviewed International Research Journal Publisher: Global Journals
More informationUltra-Fast NoC Emulation on a Single FPGA
The 25 th International Conference on Field-Programmable Logic and Applications (FPL 2015) September 3, 2015 Ultra-Fast NoC Emulation on a Single FPGA Thiem Van Chu, Shimpei Sato, and Kenji Kise Tokyo
More informationWITH the development of the semiconductor technology,
Dual-Link Hierarchical Cluster-Based Interconnect Architecture for 3D Network on Chip Guang Sun, Yong Li, Yuanyuan Zhang, Shijun Lin, Li Su, Depeng Jin and Lieguang zeng Abstract Network on Chip (NoC)
More informationOpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel
OpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel Hyoukjun Kwon and Tushar Krishna Georgia Institute of Technology Synergy Lab (http://synergy.ece.gatech.edu) hyoukjun@gatech.edu April
More informationDesign and Implementation of a Packet Switched Dynamic Buffer Resize Router on FPGA Vivek Raj.K 1 Prasad Kumar 2 Shashi Raj.K 3
IJSRD - International Journal for Scientific Research & Development Vol. 2, Issue 02, 2014 ISSN (online): 2321-0613 Design and Implementation of a Packet Switched Dynamic Buffer Resize Router on FPGA Vivek
More informationA Survey of Techniques for Power Aware On-Chip Networks.
A Survey of Techniques for Power Aware On-Chip Networks. Samir Chopra Ji Young Park May 2, 2005 1. Introduction On-chip networks have been proposed as a solution for challenges from process technology
More informationNetwork-on-Chip Architecture
Multiple Processor Systems(CMPE-655) Network-on-Chip Architecture Performance aspect and Firefly network architecture By Siva Shankar Chandrasekaran and SreeGowri Shankar Agenda (Enhancing performance)
More informationMeet in the Middle: Leveraging Optical Interconnection Opportunities in Chip Multi Processors
Meet in the Middle: Leveraging Optical Interconnection Opportunities in Chip Multi Processors Sandro Bartolini* Department of Information Engineering, University of Siena, Italy bartolini@dii.unisi.it
More informationFast Flexible FPGA-Tuned Networks-on-Chip
This work was funded by NSF. We thank Xilinx for their FPGA and tool donations. We thank Bluespec for their tool donations. Fast Flexible FPGA-Tuned Networks-on-Chip Michael K. Papamichael, James C. Hoe
More informationon Chip Architectures for Multi Core Systems
Wireless Network on on Chip Architectures for Multi Core Systems Pratheep Joe Siluvai, Qutaiba Saleh pi4810@rit.edu, qms7252@rit.edu Outlines Multi-core System Wired Network-on-chip o Problem of wired
More informationFastTrack: Leveraging Heterogeneous FPGA Wires to Design Low-cost High-performance Soft NoCs
1/29 FastTrack: Leveraging Heterogeneous FPGA Wires to Design Low-cost High-performance Soft NoCs Nachiket Kapre + Tushar Krishna nachiket@uwaterloo.ca, tushar@ece.gatech.edu 2/29 Claim FPGA overlay NoCs
More informationUtilizing Parallelism of TMR to Enhance Power Efficiency of Reliable ASIC Designs
Utilizing Parallelism of TMR to Enhance Power Efficiency of Reliable ASIC Designs Hagen Sämrow, Claas Cornelius, Jakob Salzmann, Andreas Tockhorn, Dirk Timmermann 30/11/2010, Cairo Institute of Applied
More informationHiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip
HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip Rickard Holsmark 1, Maurizio Palesi 2, Shashi Kumar 1 and Andres Mejia 3 1 Jönköping University, Sweden 2 University of Catania,
More informationDesign And Verification of 10X10 Router For NOC Applications
Design And Verification of 10X10 Router For NOC Applications 1 Yasmeen Fathima, 2 B.V.KRISHNAVENI, 3 L.Suneel 2,3 Assistant Professor 1,2,3 CMR Institute of Technology, Medchal Road, Hyderabad, Telangana,
More informationAdaptive Hardware in Autonomous and Evolvable Embedded Systems
Adaptive Hardware in Autonomous and Evolvable Embedded Systems Stephan Kubisch, Ronald Hecht, Dirk Timmermann stephan.kubisch@uni-rostock.de University of Rostock, Institute of Applied Microelectronics
More informationDynamic Packet Fragmentation for Increased Virtual Channel Utilization in On-Chip Routers
Dynamic Packet Fragmentation for Increased Virtual Channel Utilization in On-Chip Routers Young Hoon Kang, Taek-Jun Kwon, and Jeff Draper {youngkan, tjkwon, draper}@isi.edu University of Southern California
More informationNetwork on Chip Architecture: An Overview
Network on Chip Architecture: An Overview Md Shahriar Shamim & Naseef Mansoor 12/5/2014 1 Overview Introduction Multi core chip Challenges Network on Chip Architecture Regular Topology Irregular Topology
More informationFIST: A Fast, Lightweight, FPGA-Friendly Packet Latency Estimator for NoC Modeling in Full-System Simulations
FIST: A Fast, Lightweight, FPGA-Friendly Packet Latency Estimator for oc Modeling in Full-System Simulations Michael K. Papamichael, James C. Hoe, Onur Mutlu papamix@cs.cmu.edu, jhoe@ece.cmu.edu, onur@cmu.edu
More informationDesign methodology for multi processor systems design on regular platforms
Design methodology for multi processor systems design on regular platforms Ph.D in Electronics, Computer Science and Telecommunications Ph.D Student: Davide Rossi Ph.D Tutor: Prof. Roberto Guerrieri Outline
More informationDynamic Routing of Hierarchical On Chip Network Traffic
System Level Interconnect Prediction 2014 Dynamic outing of Hierarchical On Chip Network Traffic Julian Kemmerer jvk@drexel.edu Baris Taskin taskin@coe.drexel.edu Electrical & Computer Engineering Drexel
More informationDesign of a System-on-Chip Switched Network and its Design Support Λ
Design of a System-on-Chip Switched Network and its Design Support Λ Daniel Wiklund y, Dake Liu Dept. of Electrical Engineering Linköping University S-581 83 Linköping, Sweden Abstract As the degree of
More informationMapping and Configuration Methods for Multi-Use-Case Networks on Chips
Mapping and Configuration Methods for Multi-Use-Case Networks on Chips Srinivasan Murali CSL, Stanford University Stanford, USA smurali@stanford.edu Martijn Coenen, Andrei Radulescu, Kees Goossens Philips
More informationInterconnection Networks: Topology. Prof. Natalie Enright Jerger
Interconnection Networks: Topology Prof. Natalie Enright Jerger Topology Overview Definition: determines arrangement of channels and nodes in network Analogous to road map Often first step in network design
More informationA Flexible Design of Network on Chip Router based on Handshaking Communication Mechanism
A Flexible Design of Network on Chip Router based on Handshaking Communication Mechanism Seyyed Amir Asghari, Hossein Pedram and Mohammad Khademi 2 Amirkabir University of Technology 2 Shahid Beheshti
More informationNetworks-on-Chip Router: Configuration and Implementation
Networks-on-Chip : Configuration and Implementation Wen-Chung Tsai, Kuo-Chih Chu * 2 1 Department of Information and Communication Engineering, Chaoyang University of Technology, Taichung 413, Taiwan,
More informationAnalyzing the Effectiveness of On-chip Photonic Interconnects with a Hybrid Photo-electrical Topology
Analyzing the Effectiveness of On-chip Photonic Interconnects with a Hybrid Photo-electrical Topology Yong-jin Kwon Department of EECS, University of California, Berkeley, CA Abstract To improve performance
More informationOn the Physicl Layout of PRDT-Based NoCs
On the Physicl Layout of PRDT-Based NoCs Guoqiang Yang, Mei Yang, Yulu Yang, Yingtao Jiang Department of Computer Science, Nankai University, Tianin, 000, China Department of Electrical and Computer Engineering,
More informationCOMPARATIVE PERFORMANCE EVALUATION OF WIRELESS AND OPTICAL NOC ARCHITECTURES
COMPARATIVE PERFORMANCE EVALUATION OF WIRELESS AND OPTICAL NOC ARCHITECTURES Sujay Deb, Kevin Chang, Amlan Ganguly, Partha Pande School of Electrical Engineering and Computer Science, Washington State
More informationPrediction Router: Yet another low-latency on-chip router architecture
Prediction Router: Yet another low-latency on-chip router architecture Hiroki Matsutani Michihiro Koibuchi Hideharu Amano Tsutomu Yoshinaga (Keio Univ., Japan) (NII, Japan) (Keio Univ., Japan) (UEC, Japan)
More informationAchieving Lightweight Multicast in Asynchronous Networks-on-Chip Using Local Speculation
Achieving Lightweight Multicast in Asynchronous Networks-on-Chip Using Local Speculation Kshitij Bhardwaj Dept. of Computer Science Columbia University Steven M. Nowick 2016 ACM/IEEE Design Automation
More informationDesigning Energy-Efficient Low-Diameter On-chip Networks with Equalized Interconnects
Designing Energy-Efficient Low-Diameter On-chip Networks with Equalized Interconnects Ajay Joshi, Byungsub Kim and Vladimir Stojanović Department of EECS, Massachusetts Institute of Technology, Cambridge,
More informationSynchronized Progress in Interconnection Networks (SPIN) : A new theory for deadlock freedom
ISCA 2018 Session 8B: Interconnection Networks Synchronized Progress in Interconnection Networks (SPIN) : A new theory for deadlock freedom Aniruddh Ramrakhyani Georgia Tech (aniruddh@gatech.edu) Tushar
More informationECE/CS 757: Advanced Computer Architecture II Interconnects
ECE/CS 757: Advanced Computer Architecture II Interconnects Instructor:Mikko H Lipasti Spring 2017 University of Wisconsin-Madison Lecture notes created by Natalie Enright Jerger Lecture Outline Introduction
More informationSTG-NoC: A Tool for Generating Energy Optimized Custom Built NoC Topology
STG-NoC: A Tool for Generating Energy Optimized Custom Built NoC Topology Surbhi Jain Naveen Choudhary Dharm Singh ABSTRACT Network on Chip (NoC) has emerged as a viable solution to the complex communication
More informationResearch on Topology and Policy for Low Power Consumption of Network-on-chip with Multicore Processors
2015 International Conference on Computational Science and Computational Intelligence Research on Topology and Policy for Low Power Consumption of Network-on-chip with Multicore Processors Juan Fang College
More informationLecture 2: Topology - I
ECE 8823 A / CS 8803 - ICN Interconnection Networks Spring 2017 http://tusharkrishna.ece.gatech.edu/teaching/icn_s17/ Lecture 2: Topology - I Tushar Krishna Assistant Professor School of Electrical and
More informationHiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip
HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip Rickard Holsmark, Shashi Kumar Dept. of Electronics and Computer Engineering Jönköping University Sweden Maurizio Palesi Dept.
More informationFast, Accurate and Detailed NoC Simulations
Fast, Accurate and Detailed NoC Simulations Pascal T. Wolkotte and Philip K.F. Hölzenspies and Gerard J.M. Smit University of Twente, Department of EEMCS P.O. Box 217, 75 AE Enschede, The Netherlands P.T.Wolkotte@utwente.nl
More informationFault-Tolerant Multiple Task Migration in Mesh NoC s over virtual Point-to-Point connections
Fault-Tolerant Multiple Task Migration in Mesh NoC s over virtual Point-to-Point connections A.SAI KUMAR MLR Group of Institutions Dundigal,INDIA B.S.PRIYANKA KUMARI CMR IT Medchal,INDIA Abstract Multiple
More informationA 2 OLPC Performance Impact of SMP-Cluster on the On-chip Large-scale Parallel Computing Architecture
A 2 OLPC Performance Impact of SMP-Cluster on the On-chip Large-scale Parallel Computing Architecture Shenggang Chen, Shuming Chen, and Yaming Yin National University of Defense Technology Changsha, China
More informationOn Packet Switched Networks for On-Chip Communication
On Packet Switched Networks for On-Chip Communication Embedded Systems Group Department of Electronics and Computer Engineering School of Engineering, Jönköping University Jönköping 1 Outline : Part 1
More information3D WiNoC Architectures
Interconnect Enhances Architecture: Evolution of Wireless NoC from Planar to 3D 3D WiNoC Architectures Hiroki Matsutani Keio University, Japan Sep 18th, 2014 Hiroki Matsutani, "3D WiNoC Architectures",
More informationReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
1 ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology Mikkel B. Stensgaard and Jens Sparsø Technical University of Denmark Technical University of Denmark Outline 2 Motivation ReNoC Basic
More informationA Literature Review of on-chip Network Design using an Agent-based Management Method
A Literature Review of on-chip Network Design using an Agent-based Management Method Mr. Kendaganna Swamy S Dr. Anand Jatti Dr. Uma B V Instrumentation Instrumentation Communication Bangalore, India Bangalore,
More informationRouting Algorithms, Process Model for Quality of Services (QoS) and Architectures for Two-Dimensional 4 4 Mesh Topology Network-on-Chip
Routing Algorithms, Process Model for Quality of Services (QoS) and Architectures for Two-Dimensional 4 4 Mesh Topology Network-on-Chip Nauman Jalil, Adnan Qureshi, Furqan Khan, and Sohaib Ayyaz Qazi Abstract
More informationA Novel Design Framework for the Design of Reconfigurable Systems based on NoCs
Politecnico di Milano & EPFL A Novel Design Framework for the Design of Reconfigurable Systems based on NoCs Vincenzo Rana, Ivan Beretta, Donatella Sciuto Donatella Sciuto sciuto@elet.polimi.it Introduction
More informationEvaluating Bufferless Flow Control for On-Chip Networks
Evaluating Bufferless Flow Control for On-Chip Networks George Michelogiannakis, Daniel Sanchez, William J. Dally, Christos Kozyrakis Stanford University In a nutshell Many researchers report high buffer
More informationDesigning 3D Tree-based FPGA TSV Count Minimization. V. Pangracious, Z. Marrakchi, H. Mehrez UPMC Sorbonne University Paris VI, France
Designing 3D Tree-based FPGA TSV Count Minimization V. Pangracious, Z. Marrakchi, H. Mehrez UPMC Sorbonne University Paris VI, France 13 avril 2013 Presentation Outlook Introduction : 3D Tree-based FPGA
More informationBARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs
-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs Pejman Lotfi-Kamran, Masoud Daneshtalab *, Caro Lucas, and Zainalabedin Navabi School of Electrical and Computer Engineering, The
More informationFuture Gigascale MCSoCs Applications: Computation & Communication Orthogonalization
Basic Network-on-Chip (BANC) interconnection for Future Gigascale MCSoCs Applications: Computation & Communication Orthogonalization Abderazek Ben Abdallah, Masahiro Sowa Graduate School of Information
More informationSURVEY ON LOW-LATENCY AND LOW-POWER SCHEMES FOR ON-CHIP NETWORKS
SURVEY ON LOW-LATENCY AND LOW-POWER SCHEMES FOR ON-CHIP NETWORKS Chandrika D.N 1, Nirmala. L 2 1 M.Tech Scholar, 2 Sr. Asst. Prof, Department of electronics and communication engineering, REVA Institute
More informationVarious Concepts Of Routing and the Evaluation Tools for NOC
Int. Conf. on Signal, Image Processing Communication & Automation, ICSIPCA Various Concepts Of Routing and the Evaluation Tools for NOC Smita A Hiremath 1 and R C Biradar 2 1 MTech Scholar smitaahiremath@gmail.com
More informationNoC Round Table / ESA Sep Asynchronous Three Dimensional Networks on. on Chip. Abbas Sheibanyrad
NoC Round Table / ESA Sep. 2009 Asynchronous Three Dimensional Networks on on Chip Frédéric ric PétrotP Outline Three Dimensional Integration Clock Distribution and GALS Paradigm Contribution of the Third
More informationA Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Networks-on
A Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Networks-on on-chip Donghyun Kim, Kangmin Lee, Se-joong Lee and Hoi-Jun Yoo Semiconductor System Laboratory, Dept. of EECS, Korea Advanced
More informationAn Efficient Network-on-Chip (NoC) based Multicore Platform for Hierarchical Parallel Genetic Algorithms
An Efficient Network-on-Chip (NoC) based Multicore Platform for Hierarchical Parallel Genetic Algorithms Yuankun Xue 1, Zhiliang Qian 2, Guopeng Wei 3, Paul Bogdan 1, Chi-Ying Tsui 2, Radu Marculescu 3
More informationFast Scalable FPGA-Based Network-on-Chip Simulation Models
We thank Xilinx for their FPGA and tool donations. We thank Bluespec for their tool donations and support. Computer Architecture Lab at Carnegie Mellon Fast Scalable FPGA-Based Network-on-Chip Simulation
More informationVdd Programmable and Variation Tolerant FPGA Circuits and Architectures
Vdd Programmable and Variation Tolerant FPGA Circuits and Architectures Prof. Lei He EE Department, UCLA LHE@ee.ucla.edu Partially supported by NSF. Pathway to Power Efficiency and Variation Tolerance
More informationNetwork-on-chip (NOC) Topologies
Network-on-chip (NOC) Topologies 1 Network Topology Static arrangement of channels and nodes in an interconnection network The roads over which packets travel Topology chosen based on cost and performance
More informationSort vs. Hash Join Revisited for Near-Memory Execution. Nooshin Mirzadeh, Onur Kocberber, Babak Falsafi, Boris Grot
Sort vs. Hash Join Revisited for Near-Memory Execution Nooshin Mirzadeh, Onur Kocberber, Babak Falsafi, Boris Grot 1 Near-Memory Processing (NMP) Emerging technology Stacked memory: A logic die w/ a stack
More informationFPGA BASED ADAPTIVE RESOURCE EFFICIENT ERROR CONTROL METHODOLOGY FOR NETWORK ON CHIP
FPGA BASED ADAPTIVE RESOURCE EFFICIENT ERROR CONTROL METHODOLOGY FOR NETWORK ON CHIP 1 M.DEIVAKANI, 2 D.SHANTHI 1 Associate Professor, Department of Electronics and Communication Engineering PSNA College
More informationReconfigurable Cell Array for DSP Applications
Outline econfigurable Cell Array for DSP Applications Chenxin Zhang Department of Electrical and Information Technology Lund University, Sweden econfigurable computing Coarse-grained reconfigurable cell
More informationPOLYMORPHIC ON-CHIP NETWORKS
POLYMORPHIC ON-CHIP NETWORKS Martha Mercaldi Kim, John D. Davis*, Mark Oskin, Todd Austin** University of Washington *Microsoft Research, Silicon Valley ** University of Michigan On-Chip Network Selection
More informationMPSoCSim: An extended OVP Simulator for Modeling and Evaluation of Network-on-Chip based heterogeneous MPSoCs
MPSoCSim: An extended OVP Simulator for Modeling and Evaluation of Network-on-Chip based heterogeneous MPSoCs Philipp Wehner, Jens Rettkowski, Tobias Kleinschmidt, Diana Göhringer Ruhr-University Bochum,
More informationOPAL: A Multi-Layer Hybrid Photonic NoC for 3D ICs
OPAL: A Multi-Layer Hybrid Photonic NoC for 3D ICs 4B-1 Sudeep Pasricha, Shirish Bahirat Colorado State University, Fort Collins, CO {sudeep, shirish.bahirat}@colostate.edu Abstract - Three-dimensional
More informationDesign of an Efficient Communication Protocol for 3d Interconnection Network
Available online at: http://www.ijmtst.com/vol3issue10.html International Journal for Modern Trends in Science and Technology ISSN: 2455-3778 :: Volume: 03, Issue No: 10, October 2017 Design of an Efficient
More informationAn FPGA Architecture Supporting Dynamically-Controlled Power Gating
An FPGA Architecture Supporting Dynamically-Controlled Power Gating Altera Corporation March 16 th, 2012 Assem Bsoul and Steve Wilton {absoul, stevew}@ece.ubc.ca System-on-Chip Research Group Department
More informationDo we need a crystal ball for task migration?
Do we need a crystal ball for task migration? Brandon {Myers,Holt} University of Washington bdmyers@cs.washington.edu 1 Large data sets Data 2 Spread data Data.1 Data.2 Data.3 Data.4 Data.0 Data.1 Data.2
More informationNetSpeed ORION: A New Approach to Design On-chip Interconnects. August 26 th, 2013
NetSpeed ORION: A New Approach to Design On-chip Interconnects August 26 th, 2013 INTERCONNECTS BECOMING INCREASINGLY IMPORTANT Growing number of IP cores Average SoCs today have 100+ IPs Mixing and matching
More informationHARDWARE IMPLEMENTATION OF PIPELINE BASED ROUTER DESIGN FOR ON- CHIP NETWORK
DOI: 10.21917/ijct.2012.0092 HARDWARE IMPLEMENTATION OF PIPELINE BASED ROUTER DESIGN FOR ON- CHIP NETWORK U. Saravanakumar 1, R. Rangarajan 2 and K. Rajasekar 3 1,3 Department of Electronics and Communication
More informationPerformance Evaluation of Mesh with Source Routing for Packet Loss
International Journal of cientific Research Engineering & Technology (IJRET) Volume 1 Issue 5 pp 124-129 August 212 www.ijsret.org IN 2278-882 Performance Evaluation of Mesh with ource Routing for Packet
More informationA Layer-Multiplexed 3D On-Chip Network Architecture Rohit Sunkam Ramanujam and Bill Lin
50 IEEE EMBEDDED SYSTEMS LETTERS, VOL. 1, NO. 2, AUGUST 2009 A Layer-Multiplexed 3D On-Chip Network Architecture Rohit Sunkam Ramanujam and Bill Lin Abstract Programmable many-core processors are poised
More informationA Mixed-Priority Scheduler for Network-on-Chip Wormhole Routers
A Mixed-Priority Scheduler for Network-on-Chip Wormhole Routers Ridha SALEM, Yahia SALAH and Mohamed ATRI Laboratory of Electronics and Microelectronics Faculty of Sciences, University of Monastir Monastir,
More informationApplication-Specific Network-on-Chip Architecture Customization via Long-Range Link Insertion
Application-Specific Network-on-Chip Architecture Customization via Long-Range Link Insertion Umit Y. Ogras Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh, PA 15213-3890,
More informationA Novel Energy Efficient Source Routing for Mesh NoCs
2014 Fourth International Conference on Advances in Computing and Communications A ovel Energy Efficient Source Routing for Mesh ocs Meril Rani John, Reenu James, John Jose, Elizabeth Isaac, Jobin K. Antony
More informationCHAPTER 2 WIRELESS SENSOR NETWORKS AND NEED OF TOPOLOGY CONTROL
WIRELESS SENSOR NETWORKS AND NEED OF TOPOLOGY CONTROL 2.1 Topology Control in Wireless Sensor Networks Network topology control is about management of network topology to support network-wide requirement.
More informationSanaz Azampanah Ahmad Khademzadeh Nader Bagherzadeh Majid Janidarmian Reza Shojaee
Sanaz Azampanah Ahmad Khademzadeh Nader Bagherzadeh Majid Janidarmian Reza Shojaee Application-Specific Routing Algorithm Selection Function Look-Ahead Traffic-aware Execution (LATEX) Algorithm Experimental
More informationFinal Presentation. Network on Chip (NoC) for Many-Core System on Chip in Space Applications. December 13, 2017
Final Presentation Network on Chip (NoC) for Many-Core System on Chip in Space Applications December 13, 2017 Dr. ir. Gerard Rauwerda Gerard.Rauwerda@recoresystems.com NoC round table Network-on-Chip (NoC)
More informationDesign of network adapter compatible OCP for high-throughput NOC
Applied Mechanics and Materials Vols. 313-314 (2013) pp 1341-1346 Online available since 2013/Mar/25 at www.scientific.net (2013) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/amm.313-314.1341
More informationDesign and Implementation of Buffer Loan Algorithm for BiNoC Router
Design and Implementation of Buffer Loan Algorithm for BiNoC Router Deepa S Dev Student, Department of Electronics and Communication, Sree Buddha College of Engineering, University of Kerala, Kerala, India
More informationA Novel Topology-Independent Router Architecture to Enhance Reliability and Performance of Networks-on-Chip
A Novel Topology-Independent Router Architecture to Enhance Reliability and Performance of Networks-on-Chip Khalid Latif 1,2, Amir-Mohammad Rahmani 1,2, Ethiopia Nigussie 1, Hannu Tenhunen 1,2 1 Department
More informationAn Application Mapping Scheme over Distributed Reconfigurable System
An Application Mapping Scheme over Distributed Reconfigurable System Chao Wang Lianghua Miao Bin Xie and Tianzhou Chen College of Computer Science Zhejiang University Hangzhou Zhejiang 310027 P. R. China
More informationOn an Overlaid Hybrid Wire/Wireless Interconnection Architecture for Network-on-Chip
On an Overlaid Hybrid Wire/Wireless Interconnection Architecture for Network-on-Chip Ling Wang, Zhihai Guo, Peng Lv Dept. of Computer Science and Technology Harbin Institute of Technology Harbin, China
More informationReduce Your System Power Consumption with Altera FPGAs Altera Corporation Public
Reduce Your System Power Consumption with Altera FPGAs Agenda Benefits of lower power in systems Stratix III power technology Cyclone III power Quartus II power optimization and estimation tools Summary
More informationDATA REUSE DRIVEN MEMORY AND NETWORK-ON-CHIP CO-SYNTHESIS *
DATA REUSE DRIVEN MEMORY AND NETWORK-ON-CHIP CO-SYNTHESIS * University of California, Irvine, CA 92697 Abstract: Key words: NoCs present a possible communication infrastructure solution to deal with increased
More informationIMPLEMENTATION OF LOW POWER DATA ENCODING TECHNIQUES FOR NoC
IMPLEMENTATION OF LOW POWER DATA ENCODING TECHNIQUES FOR NoC Swathi.Shivakumar 1 and Prasanna Kumar B. K 2 1,2 VLSI Design and Embedded Systems, Shridevi Institute of Engineering and Technology,Tumkur
More informationTechnical Report. Exploring networks-on-chip for FPGAs. Rosemary M. Francis. Number 828. January Computer Laboratory
Technical Report UCAM-CL-TR-828 ISSN 1476-2986 Number 828 Computer Laboratory Exploring networks-on-chip for FPGAs Rosemary M. Francis January 2013 15 JJ Thomson Avenue Cambridge CB3 0FD United Kingdom
More informationPacket Switch Architecture
Packet Switch Architecture 3. Output Queueing Architectures 4. Input Queueing Architectures 5. Switching Fabrics 6. Flow and Congestion Control in Sw. Fabrics 7. Output Scheduling for QoS Guarantees 8.
More information