CRISP reconfiguration in a fast changing world

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1 Designing for tomorrow means preparing for change. Scalable many-core architectures with dynamic resource management provide reconfigurability and flexibility to cope with uncertainties. Paul Heysters, Recore Systems, CEO CRISP reconfiguration in a fast changing world FP7 (ICT )

2 We need more flexible solutions to replace inflexible, expensive conventional computing architectures. Streaming applications are important drivers for a shift towards reconfigurable multi-core platforms. Henk van Zonneveld, Thales Processing Expert and Innovation Manager Streaming solutions THE ONLY CONSTANT IS CHANGE In the era Heraclitus said that, people would turn to the oracle of Delphi to have mysteries of the future unveiled. Many things have changed since then. An earthquake and barbarian invasions destroyed the oracle, and market research became our way of predicting the future: sometimes accurate, sometimes missing imminent change entirely. Today s chip designers are looking to programmable platform chips which offer maximum flexibility while keeping the advantages of speed, size, and energy that custom-made chips offer; just in case market research mispredicts and customers demand something different than anticipated. CRISP, the Cutting edge Reconfigurable ICs for Stream Processing project, addresses the call for FPGA-like flexibility combined with ASIC-like speed, size, and energy advantages with a radically scalable and dependable, dynamically reconfigurable multi-core system concept. CRISP created a General Stream Processor (GSP) for tomorrow s streaming applications in the consumer, automotive, medical and defense markets - all deploying the same platform. The scalable architecture targets flexibility, high performance, low power and a small footprint. CRISP RESEARCH CHALLENGES CRISP addresses optimal utilization, efficient programming, and dependability of reconfigurable many-cores for streaming applications. The research anticipates the further miniaturization of semiconductor technology translated into three essential questions: How can the intrinsic processing potential of a massive multi-core architecture be exploited optimally for a wide range of streaming applications? How can multi-core systems be programmed efficiently? How can large multi-core integrated circuits that use deep submicron semiconductor processes be made reliable and self-repairing? in a changing world PROOF OF CONCEPT The ambition of the CRISP platform is to scale from low-end consumer to highend professional applications using the same reconfigurable System-on-Chip (SoC) template for a General Stream Processor, based on the fact that all streaming applications share key characteristics. Two applications at both ends of the complexity spectrum are used to validate the CRISP approach. Low-end consumer: satellite navigation Satellite navigation systems have become omnipresent in e.g. cars, smart phones, and wrist watches, which makes navigation a practical proof of concept application for the low-end consumer market. A Global Navigation Satellite System (GNSS) application, compatible with GPS/NAVSTAR and Galileo, has been implemented on the CRISP General Stream Processor to determine the position, velocity, and time of the receiver. The application can run on any number of cores depending on the desired performance. As a proof of concept, the GNSS application uses five Xentium DSP cores for input preprocessing, satellite acquisition, and tracking of at least four satellites. High-end professional: digital beamforming Digital beamforming is chosen as a typical example of a high-end application with challenging throughput and computing demands. Digital beamforming is used in an increasing range of products like sonar systems, radar systems, radio astronomy telescope systems, and base stations for wireless telecommunications. A digital beamforming application, based on requirements from the radar field, has been implemented on the CRISP General Stream Processor. The application can run on any number of cores, depending on the desired speed, precision, number of received channels and number of computed beams. As a proof of concept, the beamforming application uses 39 Xentium DSP cores to process 16 receive channels and compute 8 beams. Implementing a relatively simple Global Satellite Navigation application in contrast with a complex digital beamforming application successfully demonstrates that the General Stream Processor is highly scalable. Jari Nurmi, Tampere University of Technology Professor in Computer Systems

3 Tomorrow s General Stream Processor Highlights of the 46-core GSP o Radically scalable architecture demonstrated in silicon; o Run-time resource management with reconfigurable allocation of communication bandwidth and tasks to cores; o On-chip dependability manager infrastructure for selftesting of Xentium DSP cores in a self-repairing chip; o Scalable Network-across-Chip through off-chip interfaces interconnecting the Network-on-Chips. RECONFIGURABLE FABRIC DEVICE (RFD) Multi-core SoC with 9 Xentium cores and 2 64 kb Smart Memory Tiles 32-bit Packet-Switched Network-on-Chip Reconfigurable memory mapped I/O 6 Multi-Channel Ports (MCP) + Die Link Interfaces (DLI) Dependability Infrastructural IP Clock and reset manager bit MACs/cycle, bit MACs/cycle, or bit complex MACs/cycle XENTIUM DSP IP CORE VLIW architecture 10 parallel execution units 16 kb data memory 8 kb instruction cache 4 16-bit MACs/cycle, 2 32-bit MACs/cycle, or 2 16-bit complex MACs/cycle 9 Xentium tile Xentium wrapper Xentium core tightly coupled data memory control datapath instruction cache NoC interface NoC GENERAL STREAM PROCESSOR (GSP) 46 core heterogeneous many-core platform 1 ARM General Purpose Device 5 RFDs with 9 Xentium cores each Network-across-Chip over Multi-Channel Ports bit MACs/cycle, bit MACs/cycle, or bit complex MACs/cycle 5 RFD block diagram RFD die photo DEMONSTRATOR PLATFORM Demonstrates the General Stream Processor (GSP) Cross-chip network connects the GSP chips and Xilinx Virtex-4 FPGA over Multi-Channel Ports Analog RF front-end interface Standard peripherals (Ethernet) 8 Gbps I/O test data bandwidth bit GMACs/s, bit GMACs/s, or bit complex GMACs/s RECONFIGURABLE FABRIC DEVICE (RFD) Xentium 9-core Chip-to-Chip Network-across-Chip interface UMC 90nm CMOS technology 200 MHz clock frequency 400-pin BGA package 1.0V core and 3.3V I/Os bit GMACs/s, bit GMACs/s, or bit complex GMACs/s GENERAL PURPOSE PROCESSOR DEVICE (GPD) ARM926 core Chip-to-Chip interface to RFD NoC UMC 130nm CMOS technology 200 MHz clock frequency 400-pin BGA package 1.2V core and 3.3V I/Os By using well-defined IP building blocks we were able to overcome the extraordinary design challenge of creating such a complex multi-core System-on- Chip within a very short time. Werner Brugger, Atmel Director R&D Design Center Ulm

4 Aside from new trade-offs in hardware architecture, this step towards many-cores provides new dependability solutions to manage processing and communication resources at run-time. Gerard Smit, University of Twente Professor in Computer Architectures for Embedded Systems Lifelong adjusting DEPENDABILITY The dependability of large scale multi-processor systems-on-chip is an important concern, for example in safety-critical applications. To allow for selftesting and self-repair in the GSP, we designed a dependability manager which tests for faulty cores and network path components combined with a run-time resource manager to allocate tasks to fault-free cores over sound communication links. GSP NETWORK DEPENDABILITY Dependability relies in the first place on the correct operation of the Networkon-Chip, extended with the correct operation of inter-die and even inter-board connections. for a healthy, long life RESOURCE ALLOCATION DURING RUN-TIME Allowing self-repair in the General Stream Processor only just begins once the test results of the dependability managers are available. A run-time resource manager in the GSP acts on information on faulty cores and network paths, and manages all working resources. The run-time resource manager, running on the GPD, keeps track of faulty cores and network paths, reassigns tasks to known good cores over sound communication links, keeps track of which tasks are running using which resources, and starts network and core dependability tests without compromising running tasks. Apart from self-repair, it allows new applications to start if the system can allocate all required resources both communication bandwidth and DSP cores and only if already assigned resources remain available to already running tasks. This creates the much-desired flexibility to adapt to new tasks and standards over the functional life of the General Stream Processor. Network dependability software, running on the General Purpose processor Device (GPD), periodically tests for faults within the communication infrastructure, routing test packets through the network for a complete network diagnosis. The network dependability test is based on an assumed faulty until proven good basis. Testing any network component and interface on a good path only once, and testing them twice if they are on a path with some faulty component in the first test, identifies the exact locations of all faulty components. XENTIUM DSP CORE TILE DEPENDABILITY Aside from the network dependability, individual tiles need to function reliably. Testing of Xentium DSP cores at run-time requires an on-chip infrastructure: a dependability manager on each RFD and a wrapper around each Xentium. ASSIGNING NEW TASKS TO RESOURCES It is unknown in advance when applications will be started or stopped, or when components break down. Therefore, the resource management algorithms optimize for the spatial domain, explicitly considering the (relative) location of resources to avoid inefficient resource allocation while optimizing towards minimal energy consumption and highest performance. To reduce the vast complexity of the resource allocation problem, we use the structure of a task graph to reason about the connectivity of the resource demands and provisions. The resource manager incorporates divide-and-conquer heuristics to break the resource allocation problem into sub-problems of variable size, exploiting the topology of the application and of the General Stream Processor to reduce the search space. Xentium dependability software on the GPD periodically starts background test activities. A run-time resource manager allocates the required resources if they are available: communication routes over the network, the dependability manager and three Xentium cores on the RFD. The dependability manager switches the wrappers of the target Xentium cores from functional to test mode, and multicasts deterministic test patterns. Its test response evaluator collects and compares the test responses. The Xentium dependability test is based on majority voting among peers: the odd one out is the test response from a faulty core. MENS SANA IN CORPORE SANO CRISP created a reconfigurable platform chip with an FPGA-like flexibility and ASIC-like speed, size, and energy advantages. The combination of dependability testing and ondemand resource allocation during run-time allows the General Stream Processor to stay fit during its entire functional life: it can reconfigure to multiple scenarios, changing tasks and changing standards over its lifetime. Using only sound components, it can degrade gracefully during a prolonged functional life. The combination of a dependability manager and a run-time resource manager forms the heart of a flexible reconfigurable General Stream Processor that can handle changing tasks and failing components during its entire fit life. Bart Vermeulen, NXP Senior Principal Scientist

5 THE CRISP CONSORTIUM Recore Systems is a fabless semiconductor company that develops advanced DSP platform chips and licenses reconfigurable semiconductor IP. Recore specializes in scalable reconfigurable multi-core designs that can instantly adapt to new situations and offer a unique combination of flexibility, high performance, low power and low cost. The chair Computer Architectures for Embedded Systems (CAES) of the University of Twente researches energy-efficient dependable networked embedded systems, by combining computer architectures, systems software, networking, and tools. Multi Processor Systems-on-Chip concepts are promising and one of our main research areas. caes.ewi.utwente.nl Founded in 1984, Atmel is a worldwide leader in the design and manufacture of microcontrollers, capacitive touch solutions, advanced logic, mixed-signal, nonvolatile memory and radio frequency (RF) components. Leveraging one of the industry's broadest intellectual property (IP) technology portfolios, Atmel is able to provide the electronics industry with complete system solutions. Thales Netherlands, part of the multinational Thales group, is a leading and globally operating company in the area of Naval defense systems for all type of operations and is developing their business in the security domain. Thales ranks first in the field of defense electronics within Europe and among the leading companies in the world. The Tampere University of Technology Department of Computer Systems focuses on embedded and application-specific processor architectures, on-chip communication, Network-on-Chip (NoC) and Multi-Processor System-on-Chip (MP-SoC) integration, and ASIC/FPGA implementations of digital communication and DSP systems. NXP Semiconductors provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise. These innovations are used in a wide range of automotive, identification, wireless infrastructure, lighting, industrial, mobile, consumer and computing applications. RESEARCH CONTEXT AND FUNDING The CRISP project is supported by the 7 th Framework Programme of the European Union under grant agreement ICT It is a successor of the 4S ( Smart chips for Smart Surroundings ) FP6 project. Research will continue along the path set out by CRISP in various projects, for example STARS ( and NEST ( MORE ON CRISP CRISP results were presented at more than 20 events. For a list of publications, see Project Coordinator: Dr. ir. Paul Heysters, Recore Systems, PO Box 77, 7500 AB Enschede, NL info@crisp-project.eu